JPH0399462A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To enhance an electrical insulating property between a semiconductor substrate and an element region by a method wherein an insulating film arranged on a semiconductor board of low resistivity, a semiconductor active layer of high resistivity arranged on the insulating film, and a high conductive member so formed as to reach the semiconductor substrate penetrating through the surface of the semiconductor active layer and to electrically connect them together are provided. CONSTITUTION:Semiconductor active layers of high resistivity which form semiconductor elements are isolated from each other by a semiconductor substrate 1 and an insulating layer 2, so that the semiconductor active layers are excellent in electrical insulation property between them and small in parasitic capacitance between them. When the same breakdown strength is realized between the active layers, the insulating layer 2 can be made small in thickness, so that a high conductive member 4 can be made small in length. Therefore, the high conductive member 4 can be made small in resistance without increasing it in area. As the high conductive member 4 can be made small in area, a semiconductor chip can be made large in scale of integration as a whole. The semiconductor active layer 3 and the semiconductor substrate 1 can be fully insulated from each other through the insulating layer 2, so that an integrated circuit device of this design can be protected against latch-up and lessened in parasitic capacitance.

Description

[Detailed Description of the Invention] [Summary] Regarding a semiconductor integrated circuit device having a power supply terminal on the back surface of a semiconductor chip, the electrical insulation between the semiconductor substrate, which is a part of the power supply path, and the element region is increased, The purpose is to provide a semiconductor integrated circuit device that can shorten the power supply path. The semiconductor active layer has a resistivity and a highly conductive member that reaches from the surface of the semiconductor active layer to the semiconductor substrate and is electrically connected to the semiconductor substrate.

[Industrial Application Field] The present invention relates to a semiconductor integrated circuit device, and particularly to a semiconductor integrated circuit device having a power supply terminal on the back surface of a semiconductor chip.

2. Description of the Related Art In recent years, semiconductor devices have become faster and more highly integrated, and along with the demand for a reduction in signal wiring length, there has been a demand for a reduction in the power supply wiring area.

As one solution, a structure has been proposed in which power is supplied from the back surface of the semiconductor chip.

[Prior Art] FIGS. 6A and 6B show a conventional npn bipolar transistor integrated circuit device.

FIG. 6(A) shows an example of a structure in which power is supplied from the back side of the substrate using a P-type substrate, in which a high-resistivity layer 52 is formed on a low-resistivity p-type silicon substrate 51; A high resistivity n-type epitaxial layer 54 for forming bipolar transistors and the like is formed thereon. A low resistivity n-type buried region 53 is formed on the surface of the high-resistivity p-type layer 52, forming a buried collector region of the bipolar transistor. This n+ type buried region 53 is led out to the surface by an n+ collector extraction region 63. A p-type base region 61 is formed on the surface of the epitaxial layer 54, and an n-type emitter region 62 is formed within this base region 61.
is formed. In order to derive a power supply voltage from the substrate 51 to the surface, a p+ type connection region 55 is formed through the p− type layer 52, and a p native type connection region 56 is formed through the n type epitaxial layer 54. . That is, the p-type substrate 5
1. The most negative power supply voltage is led out from the back side of the semiconductor chip to the front surface via the p+ type connection regions 55 and 56. Here, the p-type layer 52 is provided to improve the breakdown voltage between the buried collector region 53 and the p-type substrate 51.

FIG. 6(B) shows another example of the conventional technology, and shows an example of a structure in which the power supply voltage is derived from the back surface of the semiconductor chip using an n-type substrate. A - type high resistivity silicon layer 52 is formed, and an n - type epitaxial layer 54 serving as an active layer is formed thereon. p
On the surface of the - type high resistivity region 52 is an n-type buried region 53.
is formed. A bipolar transistor is formed on this n0 buried region 53 as shown in FIG. 6(A).
It is similar to

A hole is formed at a depth reaching from the semiconductor chip surface to the n-medium sized substrate 65, the side surface of the hole is covered with an insulating film 66, and the inside thereof is filled with a conductive connection region 67. This connection region 67 is formed of, for example, polycrystalline silicon doped with impurities. Further, a dielectric isolation region for isolating the bipolar transistors is provided surrounding the bipolar transistors. That is, a trench is formed surrounding the bipolar transistor, and the sidewalls of the trench are covered with an insulating film 7.
1 and filled with an undoped high resistivity polycrystalline region 72.

In the structure of FIG. 6(B), the high resistivity p-type semiconductor layer 52 is in an electrically floating state. This P-type semiconductor layer 5
In order to electrically stabilize the semiconductor layer 52, a p-type region 69 is provided from the surface of the semiconductor chip to connect the surface and the p-type semiconductor layer 52.
is connected to. The n+ type semiconductor substrate 65 is applied with the most positive power supply voltage and is led out to the semiconductor chip surface via the high conductivity connection region 67. The p-type high resistivity semiconductor layer 52 is inserted to increase the withstand voltage and reduce the capacitance between the n-type buried region 53 and the n-medium type substrate 65.

[The problem that the invention seeks to solve! ] According to the conventional technology described above, a P-type epitaxial layer is used between a semiconductor substrate and an active layer forming an element to increase the breakdown voltage. In order to increase the withstand voltage, it is necessary to make this epitaxial layer thicker, but making it thicker means that the power supply path becomes longer.

In order to suppress the resistance of the power supply path, the area of the power supply path must be increased.

Furthermore, when an n-type substrate is used, it is necessary to provide a contact region in order to stabilize the potential of the p-type cavity resistance epitaxial layer, and the area of the contact region is also required.

In this way, the area used for the semiconductor chip increases, and the degree of integration decreases.

Furthermore, a pn junction is present between the substrate and the semiconductor element region, resulting in parasitic capacitance, and a pnpn structure is partially formed, causing problems such as latch-up.

SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor integrated circuit device that can improve electrical insulation between a semiconductor substrate and an element region, which are part of a power supply path, and shorten the power supply path. It is.

Another object of the present invention is to reduce the resistance of a power supply path from the backside of a semiconductor chip without increasing the area thereof, and to reduce parasitic capacitance and prevent latch-up. An object of the present invention is to provide a circuit device.

[Means for Solving the Problems] FIG. 1 is a diagram illustrating the principle of the present invention. An insulating layer 2 is formed on a semiconductor substrate 1 having a low resistivity, and a semiconductor active layer 3 having a high resistivity is formed thereon.

A highly conductive member 4 is formed that reaches the semiconductor substrate 1 from the surface of the semiconductor chip. This highly conductive member electrically connects the semiconductor substrate 1 and the surface of the semiconductor chip. Further, an isolation region 5 is provided surrounding the element region of the semiconductor active layer 3.
is formed.

[Function] Since the high resistivity semiconductor active layer 3 forming the semiconductor element is separated from the low resistivity semiconductor substrate 1 via the insulating layer 2, electrical insulation is good and parasitic capacitance between them is reduced. will also become smaller.

When achieving the same withstand voltage, the thickness of the insulating layer 2 can be made thinner than the thickness of the high resistivity semiconductor layer 52 in the conventional technology, so the length of the highly conductive member 4 can be shortened. Therefore, the resistance of the highly conductive member 4 can be lowered without increasing its area.

Since the area of the highly conductive member 4 can be reduced,
A high degree of integration can be achieved as a whole semiconductor chip.

Furthermore, since the semiconductor active layer 3 and the semiconductor substrate 1 can be completely insulated by the insulating layer 2, latch-up can be prevented.
Parasitic capacitance can also be reduced.

[Embodiment] FIG. 2 shows a schematic cross-sectional view of a semiconductor integrated circuit according to an embodiment of the present invention.

The semiconductor substrate 1 is an n-type silicon wafer having a resistivity of about 0.1ΩC11 or less, and an oxide film 2 is formed thereon. An n-shaped buried layer 15 is provided on the oxidized WA2.
Mold 9932 layer 3 is placed.

This structure is achieved by forming an oxide film on at least one surface of two silicon wafers, bonding them together to create a bonded wafer with an oxide film sandwiched in between, and polishing one silicon wafer to achieve the desired shape. It is formed by thinning it to a thickness of . On the surface of the element wafer to be thinned, an n-soil layer that will become the buried layer 15 is formed in advance.Therefore, the n-type 9932 layer 3 and the n+ type buried layer 15 are placed on the oxide film 2; Has good crystallinity. A hole 11 is formed by penetrating the n-type 9932 layer 3, the n-type buried layer 15, and the oxide film 2 thereunder, the side surface of the hole 11 is covered with an insulating film 6, and the inside thereof is a doped polycrystalline semiconductor region. 7 to form a highly conductive connecting member 4.

On the other hand, the isolation region 5 in which the isolation region 5 is formed surrounding the element region defined in the n-type 9932 layer 3 is
The oxide film 2 is formed from the surface of the layer 3 through the n-type buried layer 15.
A trench 13 is formed, the surface of the trench 13 is covered with an insulating film 8, and the inside thereof is filled with a non-doped high resistivity polycrystalline semiconductor region 9.

A bipolar transistor is formed within the element region. An n-type collector extraction region 16 is formed that reaches the n-type buried layer 15 from the surface of the n-type 9932 layer 3. Furthermore, a p-type base region 17 is formed in the surface portion of the n-type 9932 layer 3, and an n+-type emitter region 18 is formed therein.
is formed.

A power supply electrode 20 is formed on the entire back surface of the substrate 1.

Further, a power supply extraction electrode 21 is formed on the surface of the doped polycrystalline silicon region 7. For example, the emitter region 18 of a bipolar transistor is connected to this power extraction electrode 21.

According to such a structure, the n-type 9 that forms the semiconductor element
The 932 layer 3 is completely insulated from the semiconductor substrate 1 by the insulating film 2. Furthermore, the device region defined within the n-type 9932 layer 3 is completely insulated from the surroundings by the dielectric isolation member 5. The oxide film 2 is, for example, 5i with a thickness of several thousand people.
02 film.

In place of the doped polycrystalline semiconductor region 7, a highly conductive material region such as silicide or metal may be used. The insulating film 6.8 is formed of, for example, a SiO□ film. A low resistivity semiconductor substrate 1 has an n-type 9922 layer 3 forming a semiconductor element.
Since it is dielectrically separated from the
A mold may be used as long as the semiconductor substrate 1 and the highly conductive filling member 7 form an electrically conductive path with low electrical resistance.

Examples of steps for manufacturing a semiconductor integrated circuit device as shown in FIG. 2 are shown in FIGS. 3A to 3H.

First, as shown in FIG. 3(A), an n-type silicon wafer 1 and an n-type silicon wafer 3 having an n+ type layer 15
Silicon oxide Jli2a and 2b are formed on the surface of a, respectively. For example, the thickness of each oxide film 2a, 2b is approximately 50 mm.
00 people. Note that a p-type wafer may be used as the wafer 1.

A pair of wafers prepared in this way are stacked on top of each other for about 10
They are bonded together by heat treatment at 00°C. By bonding, the n-type layer 15 becomes a buried layer.

As shown in FIG. 3(B), in the case of FIG.
The mold 9922 layer 3 is thinned, for example, to about 2μ.

Next, as shown in FIG. 3(C), the thinned semiconductor layer 3
is the semiconductor wafer surface, and a hole 11 is opened from the surface to a depth that penetrates through the oxide M2 and reaches the substrate 1. For example, the holes 11 are formed by forming a photoresist pattern having openings at the hole positions and performing directional reactive ion etching (RIE).

As shown in FIG. 3(D), an oxide film 6a is formed on the surface of the formed hole.

Next, as shown in Figure 3(E), directional etching (
For example, by performing RIE), the oxide film on the bottom of the hole is removed, leaving the oxide film 6 only on the side surfaces.

As shown in FIG. 3(F), the holes are filled with polycrystalline silicon by CVD or the like. In this embodiment, since the semiconductor substrate 1 is of n-type, a sufficient amount of n-type impurity such as phosphorus is added to the polycrystalline silicon region 7. In addition,
When a p-type wafer is used as the substrate 1, p-type impurities are added.

When creating isolation regions for elements, for example, by creating a photoresist mask and performing RIE, the third
As shown in Figure (G), trenches 13 are formed. This trench is oxidized! The depth is set to reach the inside of 7A2.

Next, as shown in FIG. 3H, an oxide film 8 is formed on the inner surface of the trench 13, and a non-doped high resistivity polycrystalline silicon region 9 is filled inside the oxide film 8.

Thereafter, a collector extraction region, a base region, and an emitter region are formed in the n-type 9932 layer 3 to produce a structure as shown in FIG.

FIG. 4 is a schematic cross-sectional view of a semiconductor integrated circuit device according to another embodiment of the present invention. In this embodiment, an insulating film is not formed on the bottom of the trench in the isolation region for the semiconductor element.

For example, a silicon oxide layer 2 is placed on a low resistivity p-type silicon substrate 1, and an n+ type silicon buried layer 15 and an n-type 9922 layer 3 are placed thereon. The surface of this semiconductor chip has an n-type 9922 layer 3, an n-type buried layer 15
A hole 11 is formed that penetrates the silicon oxide layer 2 and reaches the p-type semiconductor substrate 1, and the inner surface of the hole is covered with a silicon oxide film 6.
low resistivity P doped with p-type impurities.
A type polycrystalline silicon region 7 is filled. Further, a trench 13 surrounds the element region, the inner wall of the trench 13 is covered with a silicon oxide film 8a, and the inside is filled with a non-doped high resistivity polycrystalline silicon region 9. Here, the bottom surface of the silicon oxide film 8a has been removed. That is, 1, the high resistivity polycrystalline silicon region 9 is in contact with the silicon oxide layer 2.

In the n-type 9932 layer 3, there is an n-type collector extraction region 1.
6, a p-type base region 17 and an n+-type emitter region 18 are formed, forming a bibolar transistor structure.

Figure 5 (A) shows the process of manufacturing the structure shown in Figure 4.
- Shown in (D).

First, a bonded substrate is created through the steps shown in FIGS. 3(A) and 3(B). A photoresist mask 12 is placed on this bonded substrate as shown in FIG.
and provide an opening in the area where the hole is to be formed. By performing RIE through this photoresist mask,
A hole 11 is formed through the oxide film 2.

Next, as shown in FIG. 5(B), a new photoresist mask 14 is formed to cover this hole 11, and an opening is created in a portion where a trench is to be formed. By performing RIE through this photoresist mask 14, the trench 13 is
Create. This trench 13 reaches from the surface of the semiconductor chip to the middle of the oxide film 2.

After that, as shown in FIG. 5(C), the silicon oxide film 6
A, 8 is created to cover the surface of the hole 11 and trench 13.

Next, as shown in FIG. 5(D), RIB is performed to remove the bottom portions of the oxide films 6a and 8. Thereafter, the holes 11 and trenches 13 are filled with polycrystalline silicon, a mask is formed, and impurities are added to necessary portions to impart conductivity, thereby creating a desired structure. In this way, the fourth
The structure shown in the figure can be created. By providing a common process for hole 11 and trench 13, the total number of processes can be reduced.

Although the present invention has been described above with reference to examples, the present invention is not limited to these examples. For example, various modifications, improvements, and
It will be obvious to those skilled in the art that combinations and the like are possible.

[Effects of the Invention] As explained above, according to the present invention, the withstand voltage between the substrate and the element layer is increased, and a low-resistance power supply is provided from the back surface of the semiconductor chip to the front surface without increasing the area of the power supply path. Wiring can be provided.

Therefore, the degree of integration of the semiconductor integrated circuit device can be increased, parasitic capacitance can be reduced, and latch-up can be prevented.

This greatly contributes to improving the performance of semiconductor integrated circuit devices.

[Brief explanation of drawings]

FIG. 1 is a diagram explaining the principle of the present invention, FIG. 2 is a schematic cross-sectional view of a semiconductor integrated circuit device according to an embodiment of the present invention, and FIGS. 3 (A) to (H) are diagrams for manufacturing the structure shown in FIG. 2. 4 is a schematic sectional view of a semiconductor integrated circuit device according to another embodiment of the present invention, and FIGS. Cross-sectional views showing the manufacturing process. FIGS. 6(A) and 6(B) are schematic cross-sectional views showing examples of conventional technology. In the figure, 1 low resistivity semiconductor substrate 6, 1 3 12, 5 6 7 8 20, insulating layer high resistivity semiconductor active layer highly conductive member isolation region insulating film doped polycrystalline semiconductor region non-doped polycrystalline semiconductor region hole Trench mask Low resistivity buried layer Collector Lead-out region Base region Emitter region Power supply electrode G) Trench formation (D) WIi formation (H) Oxidation, polycrystal filling Figure 3 Figure 4 (A) Mask etching (C) Oxidation 1244: Mask Figure 5 (Alp type substrate (Example of Bin type board Fig. 6)

Claims (2)

[Claims] (1), a low resistivity semiconductor substrate (1), an insulating film disposed on the semiconductor substrate (1); (2); a semiconductor active layer (3) disposed on the insulating film (2) and having a higher resistivity than the semiconductor substrate; A semiconductor integrated circuit device having a highly conductive member (4) that is electrically connected. (2), the highly conductive member (4) is surrounded by an insulating film;
2. The semiconductor integrated circuit device according to claim 1, further comprising a polycrystalline semiconductor region doped with impurities.