JPH0397744U - - Google Patents
Info
- Publication number
- JPH0397744U JPH0397744U JP542690U JP542690U JPH0397744U JP H0397744 U JPH0397744 U JP H0397744U JP 542690 U JP542690 U JP 542690U JP 542690 U JP542690 U JP 542690U JP H0397744 U JPH0397744 U JP H0397744U
- Authority
- JP
- Japan
- Prior art keywords
- ram
- accessed
- external computer
- predetermined address
- port ram
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000011156 evaluation Methods 0.000 claims description 5
- 230000009977 dual effect Effects 0.000 claims description 3
- 238000010586 diagram Methods 0.000 description 1
Description
図面は、本考案の評価用マイクロコンピユータ
を示すブロツク図である。
1……評価用マイクロコンピユータ、2……R
OM、3……ホストコンピユータ、7……デユア
ルポートRAM、8……データポインタDP。
The drawing is a block diagram showing an evaluation microcomputer of the present invention. 1...Evaluation microcomputer, 2...R
OM, 3...Host computer, 7...Dual port RAM, 8...Data pointer DP.
Claims (1)
ピユータでアクセスされることによつて、前記所
定アドレスに対してデータの書き込み/読み出し
が行われるRAMを内蔵し、外部ROMのプログ
ラムデータを読み込んで動作する評価用マイクロ
コンピユータにおいて、 前記RAMを、前記アドレスカウンタ及び前記
外部コンピユータで非同期にアクセス可能なデユ
アルポートRAMとし、 前記評価用マイクロコンピユータの動作中、前
記外部コンピユータによつて、前記デユアルポー
トRAMの所定アドレスに対してデータの書き込
み/読み出しを可能としたことを特徴とする評価
用マイクロコンピユータ。[Claims for Utility Model Registration] A built-in RAM that writes/reads data to/from a predetermined address when the predetermined address is accessed by an address counter or an external computer, and stores program data in an external ROM. In the evaluation microcomputer that reads and operates, the RAM is a dual port RAM that can be accessed asynchronously by the address counter and the external computer, and during the operation of the evaluation microcomputer, the dual port RAM is accessed by the external computer. An evaluation microcomputer characterized in that it is possible to write/read data to/from a predetermined address of a port RAM.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP542690U JPH0397744U (en) | 1990-01-23 | 1990-01-23 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP542690U JPH0397744U (en) | 1990-01-23 | 1990-01-23 |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH0397744U true JPH0397744U (en) | 1991-10-08 |
Family
ID=31509140
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP542690U Pending JPH0397744U (en) | 1990-01-23 | 1990-01-23 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0397744U (en) |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS59216268A (en) * | 1983-05-25 | 1984-12-06 | Nec Corp | Information processing device having multiport ram |
JPS6290733A (en) * | 1985-10-16 | 1987-04-25 | Sanyo Electric Co Ltd | Device for displaying content of ram |
JPS6453240A (en) * | 1987-05-15 | 1989-03-01 | Nec Corp | Evaluating microprocessor |
JPH01309138A (en) * | 1988-06-07 | 1989-12-13 | Yokogawa Electric Corp | In-circuit emulator |
-
1990
- 1990-01-23 JP JP542690U patent/JPH0397744U/ja active Pending
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS59216268A (en) * | 1983-05-25 | 1984-12-06 | Nec Corp | Information processing device having multiport ram |
JPS6290733A (en) * | 1985-10-16 | 1987-04-25 | Sanyo Electric Co Ltd | Device for displaying content of ram |
JPS6453240A (en) * | 1987-05-15 | 1989-03-01 | Nec Corp | Evaluating microprocessor |
JPH01309138A (en) * | 1988-06-07 | 1989-12-13 | Yokogawa Electric Corp | In-circuit emulator |
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