JPH039616A - Organizational encoder - Google Patents

Abstract

PURPOSE:To easily make a circuit into an integrated circuit and to use it as the internal encoder of a sequential decoder by providing a parity generation circuit to generate a parity bit from the shift data of first and second shift registers, and an input switching circuit to switch and shift part of the parity bit to the second shift register. CONSTITUTION:A selector 18 selects input terminals 1A and 2A when a frequency division output signal (h) is set at '1', and inputs the parity bit (e) to a shift register 12 via a change-over switch 20. Also, the selector inputs the output signal (d) of a flip-flop 17 to a shift register 11 via the change-over switch 20. Also, the selector selects input terminals 1B and 2B when the frequency division signal (h) is set at '0', and inputs the output signal of the flip-flop 17 to the shift register 12 via the change-over switch 20, and inputs the output signal (c) of a flip-flop 16 to the shift register 11 via the change-over switch 20.

Description

[Detailed Description of the Invention] [Summary] The present invention relates to a systematic encoder that generates a systematic code with a high coding rate. , input data and
parity bits generated by convolution processing of the input data, and removes a part of the parity bits to obtain a high coding rate systematic code. a second shift register; a parity generation circuit that generates the parity bit from shift data of the second shift register; The present invention includes an input switching circuit that switches and shifts the input data to the second shift register, and also switches and shifts a part of the parity bits from the parity generation circuit to the second shift register.

[Industrial application field]

The present invention relates to a systematic encoder that generates a systematic code with a high coding rate.

In communication systems such as satellite communication systems in which the deterioration of line error rate is relatively large, convolutional codes with high error correction ability are used. This systematic code, which is a type of convolutional code, is a code that pairs data with a parity bit generated by convolution processing of that data, and one parity bit is added to one bit of data. , the coding rate is 1/2. By omitting some of the parity bits of this systematic code, a systematic code with a high coding rate can be obtained. For example, by omitting 2 parity bits, the coding rate can be increased to 3. /4.

Furthermore, the encoder on the transmitting side and the internal encoder of the decoder that receives and decodes the convolutional code have the same processing content, and it is desired to realize the encoder economically.

[Conventional technology]

For example, as shown in FIG. 4, the organizational code is input data II+12.13. ...and the parity bits P+, PzP 3 + generated by the convolution process.
..., for example, as I and Q channels in QPSK
It is transmitted by modulation, and the coding rate in this case is 1/2 as described above.

In such a systematic code, some of the parity bits,
For example, as shown in the figure, two parity bits P
+ + Pz + P4 + Ps + ・・
・Omits the input data, the channel is ■, and the input data and parity bit channel is Q, QPSK
It can be transmitted by modulation. The coding rate in this case is 3/4.

A conventional example for creating such a high coding rate systematic code is shown in FIG. The encoder 31 has a shift register 33 and a modulo 2 adder 34, and shows a connection configuration in which the generator polynomial G,/2 is GI/l = (111011), and from the adder 34 Parity bits P+, Pg, . . . are output.

Further, the punctured erase circuit 32 has a parity bit PI.
+ Pt + . . . and distributes the input data, and outputs a systematic code with a high coding rate as explained with reference to FIG. 4 as I and Q channels.

The configuration for erasing a part of the parity bits and the configuration of the decoder on the receiving side are, for example, as shown in Japanese Patent Publication No. 63-7690, where an erasure pattern is set in the memory, and the erasure pattern is In the decoder, an insertion pattern that is the same as the deletion pattern is set in the memory, and dummy bits are inserted according to the insertion pattern to generate a systematic code with a coding rate of 1/2. It is used to decode the data.

Furthermore, a Fano-type sequential decoder that can perform decoding without inserting dummy bits has been proposed by the present applicant in, for example, Japanese Patent Application No. 63-209512. To briefly explain this sequential decoder, as shown in FIG. 6, there is a buffer memory IJ41 for storing received symbols of I and Q channels that have been received and demodulated, and a pointer indicating the address of a node in path search. 42, and identifies whether the address is a symbol address that includes a parity bit, and outputs a path judgment switching signal that selects one of the two when the parity bit is included, and selects a path that selects one of the four when the parity bit is not included. a parity bit detection circuit 43 that outputs a switching signal; a branchmetric calculation unit 44 that calculates a maximum likelihood branch metric and decoded bits based on the path search direction and the path determination switching signal;
Calculate the path metric by integrating the branch metrics,
A direction control circuit 45 controls the path search direction based on the comparison result with the dark value, a path memory 46 stores decoded bits indicating path history, and counts clock signals from the demodulator to form symbol addresses. address counter 4
7.

With the above configuration, the decoding speed is improved by switching between the two-way selection (2-pass determination) when the parity bit is included and the four-way selection (4-bus determination) when the parity bit is omitted. It is possible to realize a symbol processing type sequential decoder that can perform decoding without inserting dummy bits.

FIG. 7 is a block diagram of the branch metric calculation section 44 in the above-mentioned sequential decoder, which includes a forward branch metric calculation circuit 51, a backward branch metric calculation circuit 52, and an internal encoder 53. The encoder 53 is
Shift registers 54 and 55 and flip-flops (FF
) 58 to 61, selectors 62, 63, and an adder, and the shift register 54, 55 and the adder have the same connection configuration as the encoder on the transmitting side, for example, The connection configuration is similar to that of the encoder 31 shown in FIG. Further, 5657 is a flip-flop (FF).

■ From the forward branch metric calculation circuit 51.

The decoded bits of the Q channel and the forward branch metric are output, and the decoded bits of the I and Q channels are added to the shift register 54.55 of the internal encoder 53, and during forward path search, the decoded bits of the I and Q channels are added to the shift register 54.55 of the internal encoder 53. It is added to the path memory 46 as a decoding bit of the Q channel. Also, when searching for a path by reversing, the path memory 4
The decoded bits from 6 are transferred to shift registers 54, 55 through selectors 62, 63 and flip-flops 59, 60.
is added to and shifted in the opposite direction. Also, according to the shift contents of shift registers 54 and 55.

The re-encoded signal corresponding to the Q channel is processed by the forward branch metric calculation circuit 51 and the backward branch metric calculation circuit 5.
It is added to 2.

[Problem to be solved by the invention]

The configuration for generating a conventional high coding rate systematic code is as follows:
As shown in FIG. 5, it requires an encoder 31 that generates a systematic code with a coding rate of 1/2 and a punctured erasure circuit 33 that erases part of the parity bits, and has a complicated configuration. In addition, there was a drawback that it was not easy to speed up the encoding process.

In addition, when decoding a systematic code with a high coding rate, it is common to insert dummy bits to restore the code to a systematic code with a coding rate of 1/2, and then decode it using maximum likelihood decoding means. However, the previously proposed sequential decoder shown in Figs. 6 and 7 does not insert dummy bits, so high-speed decoding is possible. .

Furthermore, the aforementioned encoder and decoder are each integrated into one chip, and the configurations of the encoder and the internal encoder of the decoder must be based on the same generator polynomial. Therefore, each time the generator polynomial or coding rate is changed, it is necessary to redevelop the encoder and decoder, resulting in cost savings.

An object of the present invention is to facilitate integration into an integrated circuit and to enable use as an internal encoder of a sequential decoder.

[Means to solve the problem]

The systematic encoder of the present invention is a symbol processing type systematic encoder that directly generates a systematic code with a high coding rate, and will be explained with reference to FIG.

In a systematic encoder that consists of input data and parity bits generated by convolution processing of this input data, and which removes a part of the parity bits to obtain a systematic code with a high coding rate, first. The second shift registers 1, 2 and the first . a parity generation circuit 3 that generates parity bits from the shift data of the second shift registers 1 and 2;
．． It is composed of an input switching circuit 4 that switches and shifts input data to the second shift registers 1 and 2, and also switches and shifts a part of the parity bits from the parity generation circuit 3 to the second shift register 2. It is.

[Effect]

The parity generation circuit 3 generates a parity bit by convolution processing based on the shift data of the shift registers 1 and 2, and inputs it to the second shift register 2 via the input switching circuit 4. By the switching circuit 4,
Part of the parity bits corresponding to the input data is erased, and the input data is changed to the first . Since it is distributed to the second shift register 1.2, the first shift register. The encoded outputs of the I and Q channels are obtained from the second shift register 1.2.

〔Example〕

Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 2 is a block diagram of an embodiment of the present invention, and 11.1
2 is the first. second shift register, 13.14.15 is a modulo 2 adder, 16.17 is a flip-flop;
18 is a selector, 19 is a frequency divider, and 20 is a changeover switch. The flip-flops 16 and 17, the selector 18, and the frequency divider 19 constitute the input switching circuit 4 shown in FIG. 14 and 15 constitute the parity generation circuit 3 of FIG. Furthermore, the shift registers 11 and 12 are the same as those shown in FIG. This figure corresponds to the second shift register 1.2 and shows a configuration for forming a systematic code with a coding rate of 3/4.

Input data is applied to the data terminal of flip-flop 16, and data clock signal a synchronized with this data is applied to clock terminal CK of flip-flop 16.17. Further, the output terminal Q1 of the flip-flop 16 is connected to the data terminal of the flip-flop 17 and the input terminal 2B of the selector 18.

The changeover switch 20 is connected to the terminals IY and 2Y of the selector 18 as indicated by the solid line when the changeover switch 20 is operated in conjunction and used as a systematic encoder, and is switched to the dotted line position when used as an internal encoder of a sequential decoder. It is something that is connected.

The selector 18 also divides the modem clock signal into a frequency divider 19.
The switching operation is performed by the signal frequency-divided by the input terminal 2.
Either the signal d applied to A or the signal C applied to input terminal 2B is switched and outputted to output terminal 2Y, and the signal e applied to input terminal IA (parity bit)
and the signal d applied to the input terminal IB are switched and outputted to the output terminal IY.

The shift registers 11 and 12 perform a shift operation in accordance with a modem clock signal, and can also be controlled to reverse the shift direction by a shift direction control signal (not shown). That is, shift register 1
1. ．． Reference numeral 12 indicates a structure capable of bidirectional shifting.

The generating polynomial G,/2 of the systematic code with a coding rate of 1/2 is expressed as C+/z = (a + at as---a
n ) - (1), the unit matrices of transformation are A and B, and the zero matrix is 0, then the generating polynomial 〇 for the shift data of the first shift register 11 is as follows. That is, by adding the output signal of the adder 13 and the output signal of the adder 14 by the adder 15, (
4) It is possible to generate parity bits according to the generating polynomial G of Eq.

In Fig. 2, if the format for converting the coding rate 1/2 to the coding rate 3/4 is defined as follows, then the generating polynomial G2 for the shift data of the shift register 12 of writing brush 2 is the unit of conversion. Matrices A, B, and O are as follows.

becomes. Therefore, the parity bit generating polynomial G is: G = C+ + Gz - (41 Therefore, the generating polynomial G by the adder 13 is G+/l
= (a+ az-a, l)= (111011)
Then, = (1101) −・(8)
The polynomial G2 generated by the adder 14 is =(0101) -(9), which indicates the connection configuration between the shift register 11.12 and the adder 1314.

By integrating the systematic encoder with the above-described configuration, it can be applied to the internal encoder 53 in the decoder shown in FIG. In that case, the changeover switch 20 is switched to the dotted line position, and the forward branch metric calculation circuit 51
The output sides of the shift registers 11 and 12 are connected to the path memory.

FIG. 3 is an explanatory diagram of the operation of the embodiment of the present invention, in which (a) shows the data clock signal a, and (b) shows the modem clock signal b.
, (e) is the output signal C1 of the output terminal Q1 of the flip-flop 16 (dl is the output signal C1 of the output terminal Q2 of the flip-flop 17
(e) is the parity bit e of the output signal of the adder 15, (ff) is the signal f applied to the first shift register 11, (g) is the signal g applied to the second shift register 12. , (hl indicates the output signal of the frequency divider 19 which divides the frequency of the modem clock signal.

The selector 18 selects the input terminals IA and 2A when the frequency-divided output signal is "1", inputs the parity bit e to the shift register 12 via the changeover switch 20, and inputs the output signal d of the flip-flop 17. is input to the shift register 11 via the changeover switch 20. In addition, when the frequency-divided output signal is "0", input terminals IB and 2B are selected, and the output signal d of the flip-flop 17 is inputted to the shift register 12 via the changeover switch 20, and the output signal d of the flip-flop 17 is
The output signal C of No. 6 is manually input to the shift register 11 via the changeover switch 20.

The flip-flops 16 and 17 operate at the rising edge of the data clock signal a shown in (a), and the shift register 11
．． 12 performs a shift operation at the rising edge of the modem clock signal S shown in (b). Therefore, when the input data is II+rZ+I'l,..., the output signal C of the flip-flop 16 is ( The output signal d of the flip-flop 17 is delayed by one modem clock signal as shown in (dl).

Further, the parity pin e from the adder 15 is as shown in (Ql) and is added to the input terminal IA of the selector 1. Therefore, the shift register 11.12 has the selector 1
Since the signals sequentially switched and outputted by 8 are manually input, the signals are switched and inputted to the shift register 11 as shown by the dashed line arrows from (C) and (dl, and as shown in (f), Iz, Tff+ Is, Ib .
t, r*, IS+ r6... Therefore, it is possible to convert to a high coding rate systematic code of coding rate 3/4 without first converting to a systematic code of coding rate 1/2.

The present invention is not limited only to the above-described embodiments, and can be modified in various ways. For example, it is also possible to use generating polynomials other than those in the embodiments.

〔Effect of the invention〕

As explained above, the present invention has the following features: It includes second shift registers 1 and 2, a parity generation circuit 3, and a manual switching circuit 4, and the input switching circuit 4 transfers input data to the first... In addition to distributing and inputting the second shift registers 1 and 2, the parity bit from the parity generation circuit 3 is
The signal is switched and inputted to the second shift register 2, and can be directly converted into a systematic code with a high coding rate without converting into a systematic code with a coding rate of 1/2. Therefore, high-speed processing is possible, and the puncture erase circuit in the conventional example can be omitted.
It also becomes easier to integrate the circuit.

In addition, by making the m-woven encoder into an integrated circuit and applying it to the internal encoder in the decoder, even when changing the code format, it is only necessary to develop it as an encoder, which reduces costs. It has the advantage of being able to

[Brief explanation of the drawing]

FIG. 1 is an explanatory diagram of the principle of the present invention, FIG. 2 is a block diagram of an embodiment of the present invention, and FIG. 3 is an explanatory diagram of the operation of an embodiment of the present invention.
FIG. 4 is an explanatory diagram of a high coding rate systematic code, FIG. 5 is an explanatory diagram of a conventional example, FIG. 6 is a block diagram of a sequential decoder, and FIG. 7 is a block diagram of a branch metric calculation section. 1.2 is the first. In the second shift register, 3 is a parity generation circuit, and 4 is an input switching circuit.

Claims (1)

[Scope of Claims] A systematic encoder consisting of input data and parity bits generated by convolution processing of the input data, and which removes a part of the parity bits to obtain a systematic code with a high coding rate. a parity generation circuit (3) that generates the parity bit from the shift data of the first and second shift registers (1, 2) and the first and second shift registers (1, 2); The input data is switched and shifted to the first and second shift registers (1, 2), and a part of the parity bits from the parity generation circuit (3) is transferred to the second shift register (1, 2). 1. A systematic encoder comprising: an input switching circuit (4) for switching to and shifting from 2) to 2).