JP2001230677A - Turbo decoder - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a turbo decoder, which further reduces power consumption, while suppressing the delay of processing speed. SOLUTION: The data position of low reliability in the soft decided result of a repeating process, outputted from a repeated decoding part composed of SISO decoders 1-1 and 1-2, interleavers 2-1 and 2-2 and a deinterleaver 3 is preserved in a low reliability data position preserving part 4, the logic of data at the data position preserved in the low reliability data position preserving part 4 is inverted by a bit inverter circuit 7-3, CRC checks are performed simultaneously by CRC check circuits 7-11. 7-12,..., 7-1m and 7-1n. When the absence of error in the CRC checked result is decided, the repetition of the decoding process is finished by a repetition control circuit 7-4 and the decoded result is outputted by a selector circuit 7-2.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a turbo decoder for performing turbo decoding by inputting turbo-coded data in a predetermined data sequence unit.

[0002]

2. Description of the Related Art In recent years, a communication system using a turbo encoder and a turbo decoder has been developed in order to enhance the error correction capability in a communication path such as mobile communication in which the intensity of received radio waves fluctuates rapidly (fading). Is attracting attention.

FIG. 2 is a diagram showing a circuit configuration in a conventional communication system using a turbo encoder and a turbo decoder.

FIG. 2 shows a turbo encoder 20 on the transmitting side.
0, a modulator 300, a communication path 400, and a demodulator 500 and a turbo decoder 100 on the receiving side.

[0005] The turbo encoder 200 includes a convolutional encoder 2
01 and 202 and an interleaver 203 are provided.
Binary variables u = (u ₁ , u ₂ ,..., U _N ) representing information bits are input to the turbo encoder 200. The input binary variable u is directly transmitted data X _s = (X ₁ ^s , X ₂
^s, ..., is outputted as X _N ^s), it is input to the convolutional encoder 201 and interleaver 203.

[0006] The convolutional encoder 201 includes a delay circuit (not shown) and an exclusive OR gate. The convolutional encoder 201 delays the input binary variable u by one bit by a delay circuit, and operates each of the delayed one bit by an exclusive OR gate to have a temporal context. Encoded data (convolutional code) X _p1 = (X ₁ ^p1 ,
X ₂ ^{p 1} ,..., X _N ^{p 1} ).

The interleaver 203 sequentially writes the input binary variable u into the memory, and writes the written binary variable u
Is read out according to a predetermined algorithm and input to the convolutional encoder 202.

The convolutional encoder 202 delays the data from the interleaver 203 and performs an exclusive OR operation in the same manner as the convolutional encoder 201 described above to perform coded data (convolutional code) X _p2 = ( X ₁ ^p2 , X ₂ ^p2 ,..., X _N ^p2 ).

[0009] The modulator 300 has transmission data X _s output from the turbo encoder 200 and coded data X _p1 and X _p2.
Is entered. The modulator 300 converts the input transmission data X _s and the encoded data X _p1 and X _p2 into a two-phase modulated signal (B
PSK: Binary Phase Shift Ke
ing) or four-phase modulation (QPSK: Qu)
addrture Phase Shift Keyi
ng) and the like, and transmits to the communication path 400 after being modulated.

In the communication channel 400, noise is added, and the transmission data X _s and the coded data X _p1 and X _p2 containing the noise are represented by:
Input to demodulator 500.

The demodulator 500 performs a soft decision process on the received data. The soft decision process is a process of dividing the voltage level of the demodulated signal into a plurality of levels of three or more levels and outputting the divided levels. For example, eight types of multilevel data (0, 1,.
Output to 7). From the demodulator 500, the received data Y _s = (Y ₁ ^s , Y ₂ ^s , for the transmitted data X _s and the encoded data X _p1 and X _p2 , which have been subjected to the soft decision processing in this manner.
..., Y _N ^s), the encoded data ^{_{Y p1 = (Y 1 p1,}} Y 2 p1, ...,
^{_{Y N p1), Y p2 =}} (Y 1 p2, Y 2 p2, ..., Y N p2) is outputted. These received data Y _s , encoded data Y _p1 , Y _p2
Is input to the turbo decoder 100.

The turbo decoder 100 includes soft output decoders 11 and 12, interleavers 13 and 14, deinterleavers 15 and 22, a hard decision unit 16, and arithmetic units 17 and 1.
8 are provided. As an algorithm for soft output decoding, MAP (MaximumA Posterior) is used.
i) Decoding and SOVA (Soft Output Vit)
erbi Algorithm) or the like. Hereinafter, a case where MAP decoding is used as an algorithm of soft output decoding will be described as an example.

First, what kind of reliability information (referred to as likelihood information) is used for understanding a turbo code will be described. For simplicity, the received data Y _s and the encoded data Y _p are assumed to be Y = (Y _s , Y _p ). Here, Y _p is a parity input of the soft output decoder, that is, Y _p1 or Y _p2 . The MAP decoder, the decoded result (decoding result) according to the following log-likelihood ratio, u _k = either a + 1 u _k = -1
Is determined.

[0014] _{L k (u k) = logP} (u k = + 1 | Y)
_{/ P (u k = -1 |} Y) log likelihood ratios With additive algorithm is calculated as follows. Let S _k be the state at time k. S _k takes a value from 0 to 2 ^M −1. Here, M is the number of storage elements in the encoder. The branch metric when the state changes from S _k−1 to S _k is calculated as follows.

[0015]

(Equation 1)

Here, Lσ _M is calculated by the soft output decoder 12 in the case of the soft output decoder 11, and
The case of 2 is the prior information likelihood calculated by the soft output decoder 11. L _c is a constant determined by the signal-to-noise ratio, and L _c = 4E _c / No. Here, E _c is the energy for each coded bit, and No is the noise spectral density. The forward recursive state metric and the backward recursive state metric are calculated by the following equations.

[0017]

(Equation 2)

However, max (upper and lower subscripts are omitted)
This is the maximum value function with the following correction term.

[0019]

(Equation 3)

The correction term is implemented using a small look-up table. Finally, the log likelihood ratio is calculated as follows.

[0021]

(Equation 4)

In the turbo code, the log likelihood ratio is divided into three terms.

[0023]

(Equation 5)

The last term is called external likelihood information, and is a value calculated only from parity information. Only this external likelihood information is fed back to the soft output decoder 11 as prior likelihood information.

Next, the configuration of the turbo decoder 100 will be described.

[0026] The soft output decoder 11 constituting the turbo decoder 100, a received data Y _s, and the encoded data Y _p1,
Prior likelihood information L ₁ (u), which is feedback information from deinterleaver 15, is input. At first,
The value of the prior likelihood information L ₁ (u) is '0'. In soft output decoder 11, and multiplied by a constant L _c estimates the channel value L _c · Y _s to the received data Y _s, based on the the channel values L _c · Y _s and the encoded data Y _p1 The soft output data L ₁ (u ^* ) is output. The constant _Lc is set by a control processor (not shown) according to the magnitude of the signal-to-noise ratio in the communication path 400.

The arithmetic unit 17 receives the soft output data L
_The external likelihood information Le ₁ (u) is estimated by subtracting the channel value L _c · Y _s from ₁ (u ^* ). Specifically, the value of the received data Y _s small noise only includes its received data Y _s reliability when high constant L _c is set large. Therefore, the soft output data L ₁ (u ^* ) is calculated using the large channel value L _c · Y _s , and turbo decoding is performed around the received data Y _s . On the other hand, the value of the received data Y _s the received data contains a large noise Y _s where reliability is low constant L _c is set small. For this reason, the soft output data L _{1 is obtained} by using the small channel value L _c · Y _s.
(U ^* ) is calculated, and turbo decoding is performed around the soft output data L ₁ (u ^* ).

The interleaver 14 sequentially writes the external likelihood information Le ₁ (u) from the arithmetic unit 17 into a memory in the interleaver 14 and then reads out the memory with the same algorithm as in the interleaver 203 described above. The prior likelihood information L ₂ (u) is estimated. This prior likelihood information L ₂ (u) is supplied to the soft output decoder 11
Is the external likelihood information given from the soft output data L ₁ (u ^* ) obtained in ( ₁ ).

The interleaver 13 outputs the received data Y _s ′ by sequentially writing the received data Y _s into a memory in the interleaver 13 and then reading out the memory with the same algorithm as in the interleaver 203 described above.

The soft output decoder 12 includes the interleaver 1
Received data Y from 3, 14_s′, Prior likelihood information L
_Two(U) is input. Also, the code from demodulator 500
Data Y_{p Two}Is also entered. This encoded data Y_p2Is
Generated via interleaver 203 as described above.
Received data Y_s’, Prior likelihood information
L_TwoThis is the same order data as in (u). Soft output decoding
The device 12 receives the received data Y_s’To the constant L_cMultiply by the communication path
Value L_c・ Y_s’. Also, the encoding is synchronized with this
Data Y_p2And the constant L_cAnd the communication channel value L_c・ Y_p2Push
And these communication path values L_c・ Y_s’, L_c・ Y_p2And prior likelihood
Degree information L_Two(U) based on the soft output data L_Two(U^*)
Output. Output soft output data L_Two(U^*) Is hard
It is input to the setting unit 16 and the arithmetic unit 18.

The hard decision section 16 outputs multivalued soft output data L ₂
A hard decision is made as to which (u ^* ) the binary data belongs to, and the binary data D via the deinterleaver 22 is determined.
Is output. If the decoding result is estimated only once, the process ends here. However, in general, the turbo decoder 100 performs n times (n
= 2, 3,...) The above operation is repeated to estimate the decoding result, so that the following operation is continuously performed.

The arithmetic unit 18 has soft output data L_Two(U^*)
And received data Y_s′ And prior likelihood information L_Two(U) is entered
Is forced. The arithmetic unit 18 receives the data Y_s’And prior likelihood
Information L_Two(U) based on the soft output data L_Two(U^*)
And the external likelihood information Le_Two(U) is estimated. This outside
Likelihood information Le_Two(U) shows n from the soft output decoder 12
-1 is the external likelihood information estimated from the first decoding result.
You. This external likelihood information Le _Two(U) is deinterleaver 1
5 is input.

The deinterleaver 15 converts treated by reverse algorithm to the input external likelihood information Le ₂ (u) algorithm described above to the same ordering as the received data Y _s priori likelihood information L ₁ (U) is estimated and fed back to the soft output decoder 11 and the arithmetic unit 17.

As described above, in the turbo decoder 100, the two soft output decoders repeatedly feed back the a priori likelihood information L ₁ (u) and L ₂ (u) to each other to perform decoding, thereby obtaining the data. Error correction capability can be improved. Further, by rearranging the data by the interleave processing, it is possible to accurately correct a data error due to noise generated in a specific portion of the communication channel 400.

[0035]

Although the signal-to-noise ratio of data in a communication channel changes from moment to moment, in the turbo decoder 100 described above, the number of decoding repetitions is
It is set in consideration of the worst signal-to-noise ratio. For this reason,
When a block having a relatively high signal-to-noise ratio is received, the turbo decoder 100 performs excessive repetition, and thus has a problem that extra power is consumed.

Therefore, a recently published paper (“Redu
sing Power Consumption of
Turbo Code Decoder Usage
Adaptive Iteration with
Variable Supply Voltage ”,
Proc. IEEE Intnl. Symp. on
Low Power Design, San Di
ego CA, pp. 76-81, Aug. 199
In 9), the power consumption is reduced by repeating the turbo decoding, performing an error correction process and performing a CRC check, and when it is determined that there is no error, ending the repetition and estimating the decoding result. Turbo decoders have been proposed. However, when a data sequence having a relatively low signal-to-noise ratio is received, turbo decoding is repeatedly performed a number of times before it is determined that there is no error in the CRC check. is there.

Japanese Patent Application Laid-Open No. 10-303759 discloses a technique in which input soft decision data is decoded into a bit sequence by a Viterbi decoder, and reliability information is added to each bit of the decoded bit sequence. The data sequence is estimated, and the data sequence is subjected to a CRC check. If it is determined that there is no error, the data sequence is output as a decoding result. If the data sequence is determined to be erroneous, the total sum of the reliability information becomes smaller. There has been proposed a technique of estimating a decoding result by performing bit inversion until it is determined that there is no error. However, in this technique, the CRC check is performed by adding the reliability information to the decoded bit sequence, so that the time required for the CRC check is long, and therefore, the processing speed for estimating the decoding result is low. There is a problem of delay.

The present invention has been made in view of the above circumstances, and has as its object to provide a turbo decoder in which power consumption is further reduced while suppressing a delay in processing speed.

[0039]

A turbo decoder according to the present invention that achieves the above object is a turbo decoder which performs turbo decoding by inputting turbo-coded data in a predetermined data sequence unit. And a iterative decoding unit that repeats a decoding process with soft decision a plurality of times by inputting a soft decision, a hard decision unit that generates a decoded data sequence by receiving a soft decision decoding result in the iterative decoding unit and makes a hard decision, A CRC checking unit that performs a CRC check on the decoded data sequence obtained by the determining unit; and a low-reliability data position storage unit that stores a low-reliability data position in the soft-decision decoding result in the iterative decoding unit. The above C
An RC checking unit performs a CRC check on the decoded data sequence obtained by the hard decision unit and, based on the decoded data sequence, saves the decoded data sequence in the low-reliability data position storage unit. It is characterized in that a CRC check is also performed on a data sequence obtained by inverting the logic of data at a data position with low reliability.

Since the turbo decoder of the present invention inverts the logic of data at a data position with low reliability in the result of soft decision decoding to estimate a data sequence and performs a CRC check, for example, the occurrence of fading may occur. Therefore, when a noise is included in a part of the data series, the logic of only the data including the noise in the data series is inverted and the CRC check is performed. Therefore, the probability that the CRC inspection determines that there is no error increases, and the aforementioned paper (1999)
IEEE Intnl. Symp. on Low Po
Compared to the technology proposed in (Wer Design), C
The time until it is determined that there is no error in the RC inspection is short, and the power consumption is further reduced. Also, it is necessary to perform a CRC check in comparison with a technique proposed in Japanese Patent Application Laid-Open No. 10-303759, which performs a CRC check by decoding soft decision data into a bit sequence and adding reliability information to the bit sequence. The time required for the decoding is short, and the delay in the processing speed until the decoding result is estimated can be suppressed.

Here, the low-reliability-data-position storage unit performs the following every time the iterative decoding unit repeats the decoding process.
The data position of low reliability in the soft decision result in the current iteration process is stored. The CRC checking unit stores the low reliability data position in the decoded data sequence obtained by the hard decision unit. Inverts the logic of the data at the data position stored in the previous
A repetition control unit for performing a C-check and for ending the repetition of the decoding process in the iterative decoding unit when a data sequence determined to be error-free in the CRC check result in the CRC check unit is obtained; Is preferred.

By doing so, it is possible to simultaneously save the data position with low reliability and perform the CRC check, and to immediately terminate the repetition of the decoding process when it is determined that there is no error in the CRC check result. Therefore, the decoding result can be estimated in a shorter time.

[0043]

Embodiments of the present invention will be described below.

FIG. 1 is a block diagram of a turbo decoder according to one embodiment of the present invention.

The turbo decoder 10 shown in FIG.
O (Soft Input Soft Output)
Decoders 1_1, 1_2 and interleavers 2_1, 2_
2, a deinterleaver 3, a low-reliability data position storage unit 4, and an HDU (Hard Decision Uni).
t) 5 and the CRC check circuits 7_11, 7_12,.
_1m, 7_1n, a selection circuit 7_2, a bit inversion circuit 7_3, and a repetition control circuit 7_4.

The SISO decoders 1_1, 1_2, the interleavers 2_1, 2_2, and the deinterleaver 3 correspond to the iterative decoding unit according to the present invention. .., 7_1m, 7_1n, a selection circuit 7_2, a bit inversion circuit 7_3, and a repetition control circuit 7.
_4 corresponds to the CRC inspection unit according to the present invention.

[0047] The SISO decoder 1_1, the received data Y _s and the encoded data Y _p1 output from the demodulator 500 shown in FIG. 2 described above, prior likelihood information L is a feedback information output from deinterleaver 13 ₁ (u)
Is entered. At the first time, the prior likelihood information L ₁ (u)
Is at '0'. In SISO data 1_1, and multiplied by a constant L _c estimates the channel value L _c · Y _s to the received data Y _s, the soft output based on the the channel values L _c · Y _s and the encoded data Y _p1 Estimate the data L ₁ (u ^* ). Note that the constant L _c
Is set according to the magnitude of the signal-to-noise ratio in the communication path 400 shown in FIG. Furthermore, SISO decoder 1_1, estimated soft output data L ₁ (u ^*) by subtracting the channel value L _c · Y _s external likelihood information Le ₁ (u)
Is generated and output. Since the value of the received data Y _s a small noise only Including and the received data Y _s reliability when high constant L _c is set larger, soft with a large channel value L _c · Y _s Output data L ₁ (u ^* ) is calculated, and turbo decoding is performed centering on the received data Y _s . On the other hand, the received data Y _s is low reliability of the received data Y _s contains a large noise is a constant L _c
Is set to be small, a small communication channel value L _c · Y _s
Soft output data L ₁ (u ^*) is calculated, so that the turbo decoding is performed around the soft output data L ₁ (u ^*) used.

The interleaver 2_2 sequentially writes the external likelihood information Le ₁ (u) from the SISO decoder 1_1 to a memory in the interleaver 2_2, and then reads the same algorithm from the memory as in the interleaver 203 shown in FIG. To estimate prior likelihood information L ₂ (u).

The interleaver 2_1 sequentially writes the received data Y _s into a memory in the interleaver 2_1, and then reads out the received data Y _s ′ from the memory according to the same algorithm as in the interleaver 203 described above.

The SISO1_2 decoder receives the received data Y _s ′ from the interleavers 2_1 and 2_2 and the prior likelihood information L ₂ (u). Also, encoded data Y _p2 from demodulator 500 is input. This encoded data Y _p2
Is the data generated via the interleaver 203 as described above, and is the same order data as the received data Y _s ′ and the prior likelihood information L ₂ (u). SIS
The O-decoder 1_2 multiplies the received data Y _s ′ by a constant L _c to estimate a channel value L _c · Y _s ′. Also, in synchronization with this, the encoded data Y _p2 is multiplied by a constant L _c to obtain a channel value L _c.
Estimate Y _p2, and estimate these channel values L _c · Y _s ', L _c · Y
_Soft output data L ₂ based on _p2 and prior likelihood information L ₂ (u)
Estimate (u ^* ). Further, the SISO decoder 1_2
Subtracts soft output data L ₂ (u ^* ) based on received data Y _s ′ and prior likelihood information L ₂ (u), and outputs external likelihood information Le.
₂ Generate (u) and output. This external likelihood information Le
₂ (u) is input to the deinterleaver 3.

The deinterleaver 3 converts was treated according to the inverse of the algorithm with input external likelihood information Le ₂ (u) algorithm described above to the same ordering as the received data Y _s, in the soft decision decoding result Some prior likelihood information L
₁ Outputs (u).

The low reliability data position storage unit 4 stores one or more data positions with low reliability in the prior likelihood information L ₁ (u) output from the deinterleaver 3. In other words, SISO decoders 1_1, 1_2, interleaver 2
Each time the iterative decoding unit including _1, _2, and deinterleaver 3 repeats the decoding process, it stores one or more data positions with low reliability in the soft decision result in the current iteration process.

The HDU 5 receives the prior likelihood information L ₁ (u) from the deinterleaver 3 and makes a hard decision as to which of the binary data it belongs to, and outputs a binary decoded data sequence D.

The bit inversion circuit 7_3 inverts the logic of the data at the data position stored in the low reliability data position storage unit 4 in the decoded data series D obtained by the
Generate a data series for RC inspection. For example, when there are two stored data positions, three data sequences for CRC inspection (excluding the original data sequence) are generated. In the present embodiment, it is assumed that a maximum of m data sequences for CRC inspection are generated.

The CRC check circuits 7_11, 7_12,...
The data series 1,..., M from the bit inversion circuit 7_3 and the current data series D from the HDU 5 are input to 7_1m and 7_1n. CRC inspection circuits 7_11, 7
_12,..., 7_1m, 7_1n, the input CR
, M, and D are simultaneously performed, and CRC check circuits 7_11, 7_12,
, 7_1m, and 7_1n, if it is determined that the CRC check result has no error, a signal indicating the error is repeatedly output to the control circuit 7_4.

Receiving this signal, repetition control circuit 7_4 outputs a control signal for ending the repetition of the turbo decoding process. Thereby, the SISO decoder 1_
1, 1_2, the interleaver 2_1, 2_2, and the repetition of the decoding process in the decoding unit including the deinterleaver 3 are completed.

The selection circuit 7_2 has a CRC check circuit 7_1.
CR of 1, 7 — 12,..., 7 — 1 m, 7 — 1 n
A data sequence in the CRC check circuit determined to have no error in the C check result is selected and output as decoded data.

As described above, the turbo decoder 1 of the present embodiment
0, the low-reliability data position in the soft decision result in the current iteration process is stored in the low-reliability data position storage unit 4.
, And reverses the logic of the data at the data position stored in the low-reliability data position storage unit 4 and performs a CRC check together with the data sequence D. If the CRC check result indicates that there is no error, the decoding process is performed. To end the repetition of, for example, if a part of the data series includes noise due to the occurrence of fading, in the data series,
The logic of only data containing noise is inverted and the CRC
An inspection is performed. Therefore, the probability that the CRC inspection determines that there is no error increases, and the above-mentioned paper (19)
99 IEEE Intnl. Symp. on Low
Compared with the technology proposed in Power Design, the time required to determine that there is no error in the CRC check is shorter, and the power consumption is further reduced. Also,
Compared with the technique proposed in JP-A-10-303759, which decodes soft decision data into a bit sequence, adds reliability information to the bit sequence and performs a CRC check,
The time required for performing the C inspection can be reduced, and a delay in processing speed can be suppressed. Further, in the CRC check circuits 7_11, 7_12,..., 7_1m, 7_1n,
Since the CRC check is performed simultaneously, the processing speed of the CRC check is further increased.

[0059]

As described above, according to the present invention,
Further reduction in power consumption can be achieved while suppressing delay in processing speed.

[Brief description of the drawings]

FIG. 1 is a block diagram of a turbo decoder according to an embodiment of the present invention.

FIG. 2 is a diagram showing a circuit configuration in a conventional communication system using a turbo encoder and a turbo decoder.

[Explanation of symbols]

1_1, 1_2 SISO decoder 2_1, 2_2 Interleaver 3 Deinterleaver 4 Low-reliability data position storage unit 5 HDU 7_2 Selection circuit 7_3 Bit inversion circuit 7_4 Repetition control circuit 7_11, 7_12, ..., 7_1m, 7_1n CR
C inspection circuit 10 Turbo decoder

──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H03M 13/29 H03M 13/29 13/41 13/41 13/45 13/45 F-term (Reference) 5B001 AA02 AA04 AA10 AB02 AC05 AD06 AE04 5J065 AC02 AD02 AD04 AD10 AE03 AE06 AF00 AG05 AG06 AH04 AH06 AH09 AH15 AH16 AH21 AH22

Claims (2)

[Claims] 1. A turbo decoder which performs turbo decoding by inputting turbo-coded data in a predetermined data sequence unit, wherein the iterative decoding unit which inputs the data sequence and repeats a decoding process with soft decision a plurality of times. A hard decision unit that receives a soft decision decoding result in the iterative decoding unit and performs a hard decision to generate a decoded data sequence; and a CRC for the decoded data sequence obtained in the hard decision unit.
A CRC checking unit for performing a check; and a low-reliability data position storage unit for storing a low-reliability data position in the soft-decision decoding result in the iterative decoding unit. A CRC check is performed on the obtained decoded data sequence, and based on the decoded data sequence, the logic of the data at the low reliability data position stored in the low reliability data position storage unit in the decoded data sequence is determined. A turbo decoder for performing a CRC check even on a data sequence obtained by inverting the above. 2. The low-reliability data position storage unit stores a low-reliability data position in a soft decision result in a current iteration process every time the iterative decoding unit repeats a decoding process. The CRC checker performs a CRC check by inverting the logic of the data at the data position stored in the previous low-repetition process in the low-reliability data position storage unit in the decoded data sequence obtained by the hard decision unit. A repetition control unit for ending the repetition of the decoding process in the iterative decoding unit when a data sequence determined to be error-free in the CRC check result in the CRC check unit is obtained. The turbo decoder according to claim 1, wherein: