JPH0393360A - Binary data conversion system for picture processing unit - Google Patents

Abstract

PURPOSE:To display a picture printed out onto a CRT by applying compression conversion to a binary data with high resolution into a low resolution with a picture element in the unit of blocks. CONSTITUTION:The unit consists of a conversion means 5 counting number of picture elements of a high level in a block comprising plural picture elements and converting the count into a picture data with a prescribed gradation, an IOT(image output terminal) 4 reproducing a picture data in dot picture and an output means including a CRT 7, and the conversion means 5 applies compression-conversion to a binary output picture data into a picture data of a low picture element number. Since the picture data is converted in the unit of blocks, the picture element number constituting the block is compressed into picture data of one picture element. Thus, when the resolution of the picture data after the compression is matched with the resolution of the CRT 7, the output picture data of the conversion means 5 is displayed on the CRT 7.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a binary data conversion method for an image processing apparatus that compresses and converts image data consisting of binary data.

[Conventional technology]

Many document reading devices employ CCD sensors, and such document reading devices can read a document and extract the information as image data using electrical signals. Therefore, color-separated image data can be easily obtained by, for example, attaching a color filter to the CCD sensor or by switching the light source. Furthermore, although the signal extracted from the CCD sensor is analog, by converting it to a digital signal, it becomes possible to freely process, convert, edit, etc. the image data, and also to record and save the image data. becomes easier.

When reproducing such digital image data as a halftone image, for example, if there are 256 gradations, the 8-bit image data is binarized as halftone on/off data, and the binary data is The laser beam is controlled by

[゛Problem to be solved by the invention]

However, in devices that process image read data, such as copying machines, even if the image data is digitally processed, the current situation is that the image data is not stored in memory.

That is, for example, in a copying machine, generally 16 dots/mm
, -256 gradation resolution is required, and assuming that the number of pixels in one line is 5000, a memory capacity of 5 kB (8 bits x 5 0 0 0) is required just for the ■ line. Therefore, the memory capacity is too large to store image data for one document.

On the other hand, when image data is processed digitally,
As described above, it becomes easy to temporarily store image data and perform processing such as editing. In this case, displaying the edited data on the display screen is effective in order to easily check the edited content. but,
In general, the resolution of a CRT is significantly lower than that of a copying machine as described above, so image data from the copying machine cannot be directly displayed on a CRT. Therefore, it is necessary to compress the image data.

The present invention solves the above problems, and its purpose is to compress binarized on/off image data. Another object of the present invention is to perform binarized on/off
This is to compress off image data into multivalued data.

Still another object of the present invention is to improve data compression accuracy. Another object of the present invention is to enable image data read by an image reading device such as a copying machine to be displayed on a CRT.

[Means and effects for solving the problem] To this end, the binary data conversion method of the image processing apparatus of the present invention is based on the multi-value data obtained by reading a document with an IIT (image input terminal) l, as shown in FIG. IPS digital image data
(Image processing system) Corrected and edited with 2,
In a system that binarizes and outputs the binarized data using a G (screen generator) 3, a conversion means 5 counts the number of ON pixels of a block composed of a plurality of pixels and converts the counted value into image data of a predetermined gradation; IOT (Image Output Terminal) 4 and CR that reproduce image data as a halftone image
The present invention is characterized in that it includes an output means including T7, and is configured such that the conversion means 5 compresses and converts binary input image data into image data with a low number of pixels.

Since image data is converted block by block with the above configuration, the number of pixels constituting a block can be compressed into image data of l pixels. Therefore, by matching the resolution of the compressed image data to the resolution of the CRT 7, the output image data of the converting means 5 can be displayed on the CRT 7.

The conversion means 5 has a threshold corresponding to the conversion gradation, and outputs the binarized image data by comparison with the threshold, and also converts the count value and the conversion value of the binarized image data into the conversion gradation. It is characterized by correcting the input count value based on the error between the two. Alternatively, the number of pixels constituting the block is used as the output gradation number, and the count value is output as image data expressed in gradation.

Further, the converting means 5 is characterized in that it generates image data by multiplying the ratio of the count value to the number of pixels constituting the block by the maximum gradation value, and further averages the image data using surrounding pixels.

According to the above configuration, when each pixel of the CRT 7 is a blinking binary display, a conversion means is adopted that also converts the compressed image data into a binary display, and when each pixel of the CRT 7 is a brightness modulation display,
By adopting a conversion means that outputs the count value as image data using gradation expression, any type of CRT
? However, it is possible to display the image data on the CRT 7 after being compressed by the converting means.

The conversion means 5 includes a memory 6 that stores compressed and converted data.
It is characterized in that the data stored in the memory 6 is output to the output means 7, and it is possible to select inversely converting the input binary data into level 6 and outputting it to the output means 4. .

Since the memory 6 stores the compressed and converted data, it is possible to store the image data with a storage capacity that is significantly smaller than that of the input image data.

〔Example〕

Hereinafter, the present invention will be explained in detail with reference to Examples.

In this embodiment, a color copying machine will be explained as an example of an image processing device, but it is not limited to this, and can be applied to printers, facsimile machines, and other image processing devices, and can also be applied to computers, CAD, etc. Needless to say, the present invention can also be applied to the case of connecting and outputting image data.

First, prior to explaining the examples, a table of contents will be shown.

(1) Binary data conversion processing <ff) N'S module configuration (I[) IPS hardware configuration (IV) Intermediate J binary data generation circuit (■) Binary data conversion processing using line sensor In a digital copying machine, normally, as shown in FIG. 1, for example, the IITl moves the scanner in the sub-scanning direction and electrically scans in the main-scanning direction to sequentially extract the original reading signal of each pixel. 2 manuscripts
One plane's worth of image data is obtained by scanning dimensionally. This image data is in the state of, for example, 256 gradation, 8-bit multi-value data in ■PS, conversion from a reflection signal to a density signal corresponding to toner image output, edge enhancement and smoothing processing, etc.
In the case of a color copying machine, various processes such as equivalent neutral density conversion, toner color conversion, undercolor removal, editing, etc. are performed. And then SG (screen generator) 3
is converted into on/off binary data for controlling the laser beam, and this binary data is sent to the IOT 4 equipped with the laser beam. Therefore, this binary data represents multi-value data as a halftone image, and represents gradation using a plurality of pixels.

In the binary data conversion process of the present invention, a signal conversion circuit 5 is provided for the binary data output from the SG 3 to extract the gradation expressed by a plurality of pixels and compress the image data at a desired resolution. It counts the number of ons in each block consisting of multiple pixels, and generates compressed data based on the count value. A specific example of the configuration will be explained below.

(1-1) Conversion to binary data FIG. 2 is a diagram showing an example of the configuration of a circuit that compresses and converts binary data in units of blocks.

When trying to display binary image data output from SG3 on a CRT that can only display 1 and 0,
As mentioned above, since the resolutions are different, it is first necessary to compress the number of pixels, and the compressed pixels must be used to express a predetermined gradation using 1 and O. FIG. 2 shows an example of a configuration for this purpose.

In FIG. 2, data 1l is nXm (for example, 2×8
), and the counter l2 counts the number of ON pixels of this data ll. The adder circuit l3 adds the count value of the counter l2 and the error detected by the error detection circuit l5, and the binarization circuit 14 generates binary data indicating on or off from the output of the adder circuit 13. It is something to do. The error detection circuit l5 detects an error between the input and output of the binarization circuit 14, and feeds it back to the input through the addition circuit l3.

That is, the binarization circuit 14 converts the data 11 of nXm pixels into
The error detection circuit 15 detects the count value of the number of on pixels in
The input value is the sum of the outputs of , and it compares with a certain threshold value to generate an output of ``O'' or ``1'', so ``0''
” or “l” nxm pixels are “0” or “1”
It will be compressed to one pixel. In this case, for a block of nxm pixels, the threshold is set to (nXm)/2, for example, and the output is "1" for inputs greater than or equal to this threshold, and the output is "0" for inputs less than the darkness value. produces the output of

Then, the value converted from the output “l” to the input value is (nX
m), so if the input is O and ( n .x m
), there is no error. However, if the input is 1~{ (i
+xm)/2} -1, the output is set to "0", so 1 to ((nxm)/2)-1 is an insufficient output, and the input is (nXm)/2 to (nXm)- In the case of 1, the output is set to "1", so 1 to (nXm)/2 becomes an excessive output, resulting in an error between the input and the output. The error detection circuit l5 detects this error and feeds it back to the input in the addition circuit 13.

For example, first of all, as the output of the counter 12, { (
When nxm)/2)-1 comes, the binarization circuit l4 outputs “0
'', but in this case, an error of ( (nxrn) /2} -1 occurs between the output and the input, so the error detection circuit l5 detects this and adds it to the input in the adder circuit l3. Therefore, even if the output of the counter l2 continues to be the same ((nxm)/2)-1, the output of the error detection circuit l5 is added to it in the adder circuit l3, and the output becomes (nXm)-1. 2, so the binarization circuit 1
4 produces an output of "l". Therefore, the error detected by the error detection circuit l5 is 2 because (nXm), which is obtained by converting the output "l" to the input value, is subtracted from the input (nXm〉-2). When the next value becomes 0, it becomes exactly the same as the first one, but when the next output of the counter l2 is l, the output of the error detection circuit 15 is added to this in the adder circuit l3, and the result is exactly the same as the threshold value ( nXm)
/2, so the binarization circuit 14 generates an output of "1". The error detected by the error detection circuit 15 at this time is O. In this way, the error detected by the error detection circuit l5 is the maximum (nxm>/2, and on the other hand, the error detected by the counter l2
Since the output of is the maximum (nXm), the input of the binarization circuit l4, which is the sum of these values, is 0 to 3 (nXm)/2.

As described above, the threshold value is set in the binarization circuit l4, and binarization is performed based on the threshold value, and the relative error between the binarized output and the input is detected and fed back to the input. Macroscopically, the reproduction density of the input image and the output image match, and it is possible to generate multi-tone binary data. In other words, the data 11 is, for example, binary data of 256 gradations, and the same 256-level data even after compression.
If you want to binarize tones, you can set the threshold to 128. In this case, if the number of pixels (nXm) constituting the block of data 11 is not 256 pixels, multiplying the count value by 2 5 6/ (n
It can be approximated to 56 gradations. Note that this calculation may be performed by the binarization circuit 14, although an arithmetic circuit may be provided between the counter 12 and the addition circuit l3.

Although 1/2 of the conversion gradation is set as the threshold, for example, when setting 256 gradations, even if the threshold is set to 1, 2
Even if it is set to 56, the error between the input and the output is detected and fed back to the input by the addition circuit 13, so the same reproduction can be performed. In other words, any value from 1 to the conversion gradation may be set as the threshold.

(1-2>Conversion to multi-value data FIG. 3 is a diagram showing another embodiment of the present invention for compressing binary data into multi-value data.

The above embodiment compresses binary data into the same binary data, but if the CRT is capable of brightness modulation, multi-value data can be generated as image data for display on the CRT. can.

FIG. 3 shows an example of the configuration of a compression system for multivalued data that can cope with such a case. This example is
As in the example shown in Fig. 2, the counter 2 counts the number of ON data 11 consisting of a block of nxm pixels, and based on this count value, the gradation conversion circuit l6 generates multi-value data of l pixels. be.

The gradation conversion circuit 16 performs the calculation of X×A (nXm), where the count value is x1 and the number of gradations converted is 8. Therefore, if the number of pixels in a block is directly converted into the number of gradations, A becomes (lxm), so the gradation conversion circuit 16 receives the input value X from the counter 2.
The data is output as is to the CRT as multivalued data.

For example, if you want to have 256 gradations, set A to 256. Therefore, in the gradation conversion circuit 16, when nxm is 16 and the count value is 8, the multi-value data is (8/1 6)
56 generates 128, and when the count value is 16, 256 is generated as multi-value data.

Furthermore, if the number of pixels nXm in a block is 16 and you try to convert it to 24 gradations, a fraction will occur, but in this case, if the gradation conversion circuit 16 uses that fraction as an error and then diffuses it, good. For example, if the count value continues as 7 and 7, the initial compression conversion value will be (7/1 6) x 2 4 = 1 0 + 8/1 6, so 10 will be generated and the next pixel will have an error of 8. Diffuse /16. As a result, for the next pixel, (7/1 6)x2 4+8/1 6=1 1.

In this way, it is possible to compress and generate multi-valued data with gradations different from the number of pixels nxm in the block.

FIG. 4 is a diagram showing an example of the configuration of a compressed multivalued data generation system equipped with a correction processing circuit.

Even when data of nXm pixels of binary data is compressed and converted into multi-value 1-pixel data as described above, the multi-value data before binary data generation cannot be reproduced. However, it is possible to further improve the reproducibility of the multivalued data generated as described above. FIG. 4 shows an example of the configuration.

In FIG. 4, the correction processing circuit 19 performs gradation averaging processing on the compressed multivalued image data together with the surrounding pixels, and the means for capturing the surrounding pixels is the PIF018. . In the example shown, 2
Since the FIF018 with line structure is used, if three pixels are taken in from each line, the correction processing circuit 19 can target a 3×3 block, and for example, the gradation value of a pixel can be If it is alj, then? =■Σ
By calculating Σa1 9 , gradation averaging processing can be performed.

H-3) Storage of converted data In copying machines and the like, multivalued data is expanded by a screen generator, converted into binarization, and sent to a device that outputs it as a halftone image. When binary data is compressed and converted as described above, the amount of data can be reduced, so the storage capacity of the memory can also be reduced, and the compressed and converted data can be easily stored in the memory. .

FIG. 5 is a diagram showing an example of a configuration in which a memory is inserted to store image data.

In FIG. 5, an encoding circuit 21 encodes a binary data string according to a certain algorithm such as MHSMR, which is used in facsimiles, etc.
The decoding circuit 23 decodes encoded data into a binary data string.

A memory 2 is provided between the encoding circuit 21 and the decoding circuit 23.
2 is inserted and connected to store the encoded data, the storage capacity can be reduced compared to storing the image information for the original M1 plane as a binary data string. The signal conversion circuit 24, whose binary data outputted from the decoding circuit 23 is explained above, is the one explained earlier with reference to FIGS. 2 to 4. So this example:
When applied to a copying machine, SG3 shown in FIG. 1 is connected to the input side of the encoding circuit 21, but output data from a facsimile or a personal computer may be connected to the input side of the encoding circuit 21. Of course.

Furthermore, as a configuration for storing image data, a memory 6 may be connected to the output side of the signal conversion circuit 5 as shown in FIG. 1, and the compressed and converted image data may be stored in the memory 6. If so, change the memory size and compression rate to CRT7
It is not necessarily necessary to match the screen size and resolution of the screen. In other words, when a part of the entire image is displayed on the CRT 7, it is natural that a compression rate corresponding to the display size is adopted. This is because the image will be partially cut out and displayed on the CRT 7. When the memory 6 is inserted and connected at such a position, the signal conversion circuit 5 may be provided with an inverse conversion function so that the image data stored in the memory 6 can be inversely converted and sent to the IOT 4.

(n) IPS module configuration First, an overview of the IPS (image processing system) that processes color image reading signals will be explained.

FIG. 6 is a diagram showing an outline of the module structure of the IPS.

In a color image forming apparatus, an IIT (image input terminal) uses a CCD line sensor to separate the light into primary colors B (blue), G (green), and R (red), reads a color original, and converts this into the primary colors of toner. It is converted into Y (yellow), M (magenta), C (cyan), and even K (black or black), and then exposed and developed with a laser beam at ■○T (image output terminal) to reproduce a color image. There is. In this case, a copying process (
A full-color image is created by performing a total of four copy cycles, one copy cycle for M%CSK (pitch) and one copy cycle for M%CSK each as a process color, and superimposing the images of these halftone dots. is being reproduced. Therefore, color separated signals (B, G, R signals)
When converting into toner signals (YSM, CSK signals), how to adjust the color balance and IIT
Problems include how to reproduce the color in accordance with the reading characteristics of the image and the output characteristics of the ■○T, how to adjust the balance of density and contrast, and how to adjust edge emphasis, blurring, and moiré.

■PS inputs B, G, and R color separation signals from IIT, performs various data processing to improve color reproducibility, gradation reproducibility, definition reproducibility, etc., and develops color It converts the toner signal of
uivalent N neutral density
y; equivalent neutral density conversion) module 30h color masking module 302, original size detection module 3
03, Color conversion module 304, UCR (Und
er Color Remova1; Undercolor removal) &
Black generation module 305, spatial filter 306, TR
C (Tone Reproduction Cont.
rol; Color tone correction control> module 307, reduction/enlargement processing module 308, screen generator 309, I
○T interface module 310, area generation circuit and switch mask} Area image control module 311 with IJ box, area command memory 312, color palette video switch circuit 313, and font buffer 31
It consists of an editing control module, etc. with 4 etc.

Then, the 8-bit data (256 gradations) of the B%G, H color separation signals from IIT are input to the END conversion module 301, and after being converted into Y1M, C1K toner signals, the process color toner signal is selected, converted into a binary value, and outputted from the IOT interface module 310 to the IOT interface module 310 as the output/off data of the toner signal of the process color. therefore,
In the case of full color (4 colors), first the document size is detected, the editing area is detected, and other document information is detected using Briscan, and then, for example, the process color toner signal X is first set to Y for a copy cycle, and then Each time a copy cycle is sequentially executed in which the process color toner signal X is M, signal processing corresponding to four document reading scans is performed.

At IIT, a CCD sensor is used to read one pixel of each of 81G and H at a size of 16 dots/mm, and the data is divided into 24 bits (3 colors x 8 bits;
256 gradations). The CCD sensor has 16 dots with B%G and H filters attached to the top surface.
/mm density and 300mm length, 190,5m
Since scanning is performed at 16 lines/mm at a process speed of m/secC, read data is output at a rate of approximately 15M pixels per second for each color.

Then, at IIT, the analog data of the B and G%R pixels are converted into logs to convert the reflectance information into density information, and further into digital data.

Next, each module will be explained.

FIG. 7 is a diagram for explaining each module constituting the IPS.

(A) END Conversion Module The END conversion module 301 is a module for adjusting (converting) the optical reading signal of a color original obtained at IIT into a gray-balanced color signal. The amount of toner in a color image is equal in the case of gray, and gray is the standard. However, the values of the B, G, and H color separation signals input when a gray original is read from the IIT are not equal because the spectral characteristics of the light source and color separation filter are not ideal. Therefore, a conversion table (LUT'; lookup table) as shown in FIG.
END conversion uses . Therefore, the conversion table has the characteristic that when a gray original is read, it is always converted into B, G, and H color separation signals at the same gradation corresponding to the level (black and white) and output. , 11T. Further, 16 conversion tables are prepared, of which 11 are tables for film 7 projectors including negative films, and 3 are tables for normal copying, photography, and generation copying.

(B) Color masking module The color masking module 302 converts the B, G, and R signals into signals corresponding to the toner amounts of Y, M, and C by performing matrix calculations, and by END conversion. The signal after gray balance adjustment is processed.

The conversion matrix used for color masking is a 3x3 matrix that calculates Y%M1C purely from B, G, and R, but not only B%G1R but also B
Of course, various matrices or other matrices may be used to take into account the precepts of G, GR, RBSB2, and G'R2. Two sets of conversion matrices are provided: one for normal color adjustment and one for intensity signal control in monochrome mode.

In this way, when processing IIT video signals with IFS, gray balance adjustment is performed first and foremost. If this were to be performed after color masking, the conversion table would become more complex because it would be necessary to perform gray balance adjustment using the gray original in consideration of the characteristics of color masking.

(C) Original Size Detection Module Not only standard size originals but also originals of arbitrary shapes such as cutouts or other forms may be copied. In this case, it is necessary to detect the document size in order to select a paper of an appropriate size corresponding to the document size. Furthermore, when the copy paper is larger than the original size, erasing the outside of the original can improve the quality of the copy. Therefore, the document size detection module 303 performs document size detection during briscanning and platen color erasing (frame erasing) processing during document reading and scanning. For this purpose, the platen color is set to a color that can be easily distinguished from the original, for example, black, and the upper and lower limits of the platen color identification are set in the threshold register 303 as shown in FIG. 7(b).
Set to l. During pre-scanning, a signal X converted (γ-converted) into information close to the reflectance of the document (using the output of the spatial filter 306, which will be described later) and the upper limit value/lower limit value set in the threshold register 3031 are connected to a comparator. 3032 and edge detection circuit 3034
The edge of the document is detected and the position Pix. The maximum and minimum values of y are stored in the maximum/minimum sorter 3035.

For example, as shown in Figure 7(d), if the document is tilted or not rectangular, the maximum and minimum values ("
IC+. X2,'ll. Y2) is detected and stored.

Also, when reading and scanning a document, the comparator 303
3, the original YSM, C and threshold register 303
The upper limit value/lower limit value set in l are compared, and the platen color erasing circuit 3036 erases the outside of the edge, that is, the read signal of the platen, and performs frame erasing processing.

(D) Color Conversion Module The color conversion module 305 enables conversion of a specified color in a specific area, and as shown in FIG. 7(C), a window comparator 305
2. A threshold register 3051, a color palette 3053, etc. are provided, and when performing color conversion, the upper and lower limits of each YSM, C of the converted color are set in the threshold register 3051, and each Y, C of the converted color is set.
Set the MSC value in the color palette 3053. Then, the Nando game} 3054 is controlled according to the area signal input from the area image control module, and if it is not in the color conversion area, the Y, M, and C of the original are sent out as they are from the selector 3055, and when it enters the color conversion area, The Y, M, and C signals of the original are the threshold register 3.
When the value falls between the upper and lower limit values of Y, M, and C set to 051, the output of the window comparator 3052 switches the selector 3055 and sends out the converted colors Y, M, and C set in the color palette 3053. .

Specified colors can be specified by pointing directly at the document with the digitizer, and by pointing the digitizer directly at the document.
The designated color is recognized by taking the average of 25 pixels each of G and R. Through this averaging operation, for example, even a 150-line original can be recognized with an accuracy within a color difference of 5. To read the BSG and R density data, designated coordinates are converted into addresses from the IIT shading correction RAM and read out. Address conversion requires readjustment for registration adjustment, similar to original size detection. In prescan, the IIT operates in sample scan mode. B. read out from the grading correction RAM. The G and Ra degree data are subjected to shading correction by software, averaged, and further subjected to END correction and color masking before being set in the window converter 3052.

Up to 8 colors out of 6.7 million colors can be registered in the 3053 color palette at the same time, and the standard colors are YSM,
14 colors are available: C, G, BSR and their intermediate colors, as well as K and W.

(E) If the UCR & black generation modules Y, M, and C are equal amounts, the result will be gray.Theoretically, the same color can be reproduced by replacing equal amounts of YSM and C with black, but in reality When Mazuko is replaced with black, the color becomes muddy and the reproducibility of vivid colors deteriorates.

Therefore, the UCR & black generation module 3f) 5 generates an appropriate amount of K to prevent such color muddiness, and performs a process of reducing Y and MSC by the same amount (undercolor removal) in accordance with the amount. Specifically, the maximum and minimum values of Y, M, and C are detected, K is generated below the minimum value from the conversion table according to the difference, and a constant value for Y%M and C is generated according to the amount. Undercolor removal is being performed.

In UCR & black generation, as shown in Figure 7(e), for example, when the color is close to gray, the difference between the maximum value and the minimum value becomes small, so the minimum values of Y, M, and C are directly removed and the K However, if the difference between the maximum and minimum values is large, the amount of removal is less than the minimum value of YSM,C, and K
By reducing the amount of raw material, it is possible to prevent ink from being mixed in and the saturation of low-brightness, high-chroma colors to decrease.

In FIG. 7(f) showing a specific circuit configuration example, the maximum value/minimum value detection circuit 3051 detects the maximum and minimum values of Y, M, and C, and the calculation circuit 3053 calculates the difference. Then, K is generated using a conversion table 3054 and an arithmetic circuit 3055. The conversion table 3054 is for adjusting the value of K, and if the difference between the maximum value and the minimum value is small,
Since the output value of the conversion table 3054 becomes zero, the minimum value is directly output from the arithmetic circuit 3055 as the value of K, but if the difference between the maximum value and the minimum value is large, the output value of the conversion table 3054 becomes non-zero. Therefore, calculation circuit 3055
The value subtracted by that amount from the minimum value is output as the value of K. A conversion table 3056 is a table for determining a value to be removed from Y%M%C corresponding to K. Through this conversion table 3056, an arithmetic circuit 3059 converts Y%M. Perform the removal corresponding to K from C. Also, andgame}3057
, 3058 gates the K signal and the signals after removing the undercolor of Y and MSC according to the monochrome mode and 4 full color mode signals, and the selector 305
2, 3050 is Y%M%C by process color signal
%K is selected. In this way, colors are actually reproduced using four g points, Y, M, and C, so Y
, M%The removal of C and the generation ratio of K are set using empirically generated curves, tables, and the like.

(F) Spatial filter module In the device applied to the present invention, the IIT
Since the document is read while scanning the CCD, if the information is used as is, the information will be blurred.Also, since the document is reproduced by halftone dots, the halftone period of the printed matter and the sampling of 16 dots}/mm Moiré occurs between cycles. Moire also occurs between the self-generated halftone dot synchronization and the halftone dot period of the document. The spatial filter module 306 has a function of recovering such blur and a function of removing moiré. A low-pass filter is used to remove halftone dots, and a high-pass filter is used to emphasize edges.

In the spatial filter module 306, as shown in FIG. This information is easier to pick up edges, so for example, Y is selected as one of the colors.In addition, a threshold register 3001, a 4-bit binarization circuit 300
2. For each pixel using the decoder 3005, Y%MSC,
Min and Max-Min to YSM%C, KSBS
Separates into eight hues: G, R, and W (white). Decoder 3
005 is for converting the hue into ml according to the binarized information and outputting i-bit information indicating whether or not the color is a required color from the process color.

The output of FIG. 7 (BO) is input to the circuit of FIG.
By using the halftone removal information, FIF03062 and 5
The X7 digital filter 3064, modulation table 3067, and delay circuit 3065 generate edge emphasis information from the output information in the figure (110). selected accordingly.

In edge enhancement, for example, if you want to reproduce a green character like ■ in Figure 7 (i) as ■, change Y1C to ■, ■.
Emphasis processing is performed as shown in , and M is not emphasized as shown in the solid line. This switching is performed by AND game}3068. To carry out this process, if the image is emphasized as indicated by the dotted line (■), the edge will become muddy due to the color mixture of M as shown in (■).

A delay circuit 3065 uses a PIF03062 and a 5×7 digital filter 3064 to switch such emphasis using an AND gate 3068 for each process color.
This is to ensure synchronization with the When bright green characters are reproduced using normal processing, magenta is mixed into the green characters, causing them to become muddy. Therefore, if we recognize it as green as above, Y=
C is output as usual, but M is suppressed and edges are not emphasized.

(G) The TRC conversion module IOT operates Y according to the on/off signal from the IPS.
%MSC%K executes four copy cycles (in the case of 4 full-color copies) using each process color, making it possible to reproduce full-color originals, but in reality, the colors theoretically determined by signal processing are To reproduce faithfully,
Subtle adjustments are required that take into account the characteristics of IOT. T.R.
The C conversion module 309 is intended to improve such reproducibility, and inputs 8-bit image data at an address as shown in FIG. The address translation table is stored in RAM.
density adjustment according to the area signal, contrast adjustment, negative/positive inversion, color balance adjustment, character mode,
It has editing functions such as watermark composition. The upper 3 bits of this RAM address are bits 0 to 3 of the area signal.
is used. Furthermore, the above functions can be used in combination using the out-of-area mode. This RAM is composed of, for example, 2 kbytes (256 bytes x 8 sides) and holds 8 conversion tables, and up to 8 sides are stored during IIT carriage return for each cycle of Y1MSC, and are used for area designation and Selected according to copy mode.

Of course, if the RAM capacity is increased, there is no need to load it every cycle.

(H) Reduction/enlargement processing module The reduction/enlargement processing module 308 uses the line buffer 3083
The data
Sampling pitch signal and line buffer 3083 with l
Generate read/write addresses for. The line buffer 3083 is configured as a ping-pong buffer consisting of two lines, so that it is possible to read one line and write the next line data to the other at the same time. In the reduction/enlargement processing, the reduction/enlargement processing module 308 performs digital processing in the main scanning direction, but the scanning speed of the IIT is changed in the sub-scanning direction. The scan speed can be changed from 50% to 4 by changing from 2x speed to 1/4x speed.
Can be scaled up to 00%. In digital processing, when reading/writing data to/from the line buffer 3083, data can be reduced by thinning and complementing, and can be expanded by adding and complementing. If the complementary data is in the middle, it is generated by weighting according to the distance from the data on both sides, as shown in FIG. 1 (1). For example, in the case of data Xi', data X 1 % X l+1 on both sides and the distance d+ between these data and the sampling point,
From dz, (Xt Xdi ) + (Xt.+ Xd1
) However, it can be obtained by calculating d+ +d= =1.

In the case of reduction processing, data is complemented and written to the line buffer 3083, and at the same time, the reduced data of the previous line is read out from the buffer and sent out. In the case of enlargement processing, data is written as is, and data of the previous line is read out at the same time, complemented and enlarged, and then sent.

If complementary enlargement is performed at the time of writing, the clock at the time of writing must be increased according to the enlargement ratio, but if it is done as described above, writing/reading can be performed with the same clock.

In addition, using this configuration, it is possible to perform shift image processing in the main scanning direction by reading from the middle or by reading with delayed timing, and by repeatedly reading, it is possible to perform repeated processing by reading from the opposite direction. It is also possible to perform mirror image processing.

(1) Screen generator The screen generator 309 converts the process color gradation toner signal into an on/off binary toner signal and outputs it, and compares the threshold matrix with the gradation-expressed data value. Binarization processing and error diffusion processing are performed. In the IOT, this binary toner signal is input, and it is approximately vertically 8 to correspond to 16 dots/mm.
A half-tone image is reproduced by turning on and off an elliptical laser beam with a diameter of 0 μm and a width of 60 μm.

First, as shown in FIG. 7(n), a method of expressing gradations using a threshold matrix constituting, for example, a 4×4 halftone cell S will be described. In the screen generator, a threshold matrix m is set corresponding to such a halftone cell S, and this is compared with the data value expressed in gradation.

A 4×4 halftone cell with 16 dots/mm is generally referred to as a 100spi1 16-gradation halftone cell, but this results in a coarse image and poor color image reproducibility. Therefore, in the present invention, as a method of increasing the gradation, this 16 dot/mm pixel is divided vertically (in the main scanning direction) into 4 to 6 parts, and the on/off frequency of the laser beam in each pixel is made the same. As shown in Figure (0), a gradation that is four times higher is achieved by increasing it by 1/4, that is, by four times. Therefore, in response to this, a threshold value matrix m' as shown in FIG. 3(0) is set. Furthermore, a submatrix method can also be adopted to increase the number of lines.

The above example uses the same threshold value matrix }IJxm with the only elongated kernel near the center of each halftone cell, but the submatrix method is configured by a set of multiple unit matrices, and the As shown in b), a certain long nucleus of the matrix is
It is something that is done in one or more places. If such a screen pattern design method is adopted, for example, bright areas are set to 141 spi, 64 gradations, and as it gets darker, the number of lines and gradations are changed to 200 spi, 128 gradations. can be changed. Such a pattern can be designed by visually determining the smoothness, fineness, graininess, etc. of gradations.

When a halftone image is reproduced using a dot matrix as described above, the number of gradations and resolution have a contradictory relationship.

In other words, there is a relationship in which increasing the number of gradations causes a decrease in resolution, and increasing the resolution causes a decrease in the number of gradations. Also,
If the matrix of threshold data is made smaller, a quantization error will occur in the image that is actually output. Error diffusion processing is performed by converting the quantization error between the on/off binary signal generated by the screen generator 3092 and the input gradation signal into a density conversion circuit 3093 and a subtraction circuit 309, as shown in FIG.
4, the correction circuit 3095 and the addition circuit 309l
It uses feedback to improve the reproducibility of gradation when viewed from a macroscopic perspective. For example, it performs error diffusion processing that convolves the corresponding position of the previous line and the pixels on both sides of it through a digital filter. There is.

As mentioned above, the screen generator switches threshold data and feedback coefficients for error diffusion processing for each document or region within the document depending on the type of image such as a halftone image or character image, and is capable of producing high-gradation, high-definition images. Improves reproducibility.

(J) Area Image Control Module The area image control module 311 has a structure in which seven rectangular areas and their priorities can be set in the area control circuit. The area control information is set in the switch IJ box corresponding to each area.

The control information includes color conversion, color mode such as monochrome or full color, modulation selection information for photos and text, TRC selection information, screen generator selection information, etc. Color masking module 302, color conversion module 304, U.C.
R module 305, spatial filter 306, TRC module 30? used for control. Note that the switch matrix can be set by software.

(K) M collection control module The editing control module reads a document that is not a rectangle but a pie chart, for example, and enables coloring processing such as filling in a specified area of any shape with a specified color. As shown in (e), the AGDC is connected to the CPU bus.
(Advanced Graphic Digital
l Controller) 3 1 2 1, font buffer 3l26, logo ROM 128, DMA
C (DMA Controller) 3 1
29 are connected. Then, the encoded 4-bit area command is sent from the CPU to AGDC3.
1 2 1 to the brain memory 3l22, and the font is written to the font buffer 3l26. The plane memo IJ 3 1 2 2 consists of 4 sheets. For example, in the case of "0000", the command is 0 and the original manuscript is output. Can be set in bits.

The decoder 3123 decodes this 4-bit information into commands 0 to 15, and the switch matrix sets commands to perform fill pattern, fill logic, or logo processing for commands 0 to 15. It is 3124. The font address controller 3125 generates addresses for the 7-ont buffer 3l26 in response to patterns such as halftone shade and hatching shade based on a 2-bit fill pattern signal.

The switch circuit 3l27 is a switch matrix 3124
Based on the fill logic signal and the contents of the original data X, the original data X, the 7-onto buffer 3126, the color palette, etc. are selected. Fill logic is information for filling only the background (background part of the document) with a color mesh, color conversion for a specific part, masking, trimming, filling, etc.

゜In the IPS of the present invention, as described above, the IIT original reading signal is first subjected to END conversion and then color masking, and processing at full power is more efficient in terms of original size, border erasure, and color conversion. After processing, I remove the undercolor and adjust the ink, and then focus on process colors. However, spatial filters, color modulation, TRC.
By processing process color data, the amount of processing such as scaling is reduced compared to processing full color data, reducing the number of conversion tables used by 1/3, and reducing the number of types by that amount. This increases the flexibility of adjustment, the reproducibility of color, the reproducibility of gradation, and the reproducibility of definition.

(I [[) Hardware Configuration of IPS Next, an example of the hardware configuration of an IPS equipped with each of the above modules will be explained. FIG. 8 is a diagram showing an example of the hardware configuration of the IPS.

In the IPS of the present invention, two substrates (IPS-A, IPS
-B), and the I-th board (IPS-A ), parts for achieving applied and specialized functions such as editing are mounted on the second board (IPS-B). The configuration of the former is shown in Figure 8 (
a) to (C), and the latter configuration is shown in (d) of the same figure.

In particular, if the basic functions can be sufficiently achieved by the first board, applications and specialized functions can be flexibly handled simply by changing the design of the second board. Therefore, if it is desired to further enhance the functionality of the color image forming apparatus, this can be achieved simply by changing the design of the other substrate.

The IPS board has a C P. as shown in FIG. U bus (address bus ADRSBUS, f-') bus DA
TABUS, control bus CTRLBUS are connected, and video clock IIT-VCLK, line synchronization (main scanning direction, horizontal synchronization) signal 11T-LS, page synchronization (
A sub-scanning direction, vertical synchronization) signal 11T-PS is connected.

Since the video data is subjected to pipeline processing after the END conversion section, a data delay occurs in clock units necessary for processing at each processing stage. Therefore,
The line synchronization generation and fail check circuit 328 generates and distributes horizontal synchronization signals in response to delays in each process, and performs a fail check on the video clock and line synchronization signals. Therefore, the line synchronization generation & fail check circuit 328 includes a video clock I
IT-VCLK and line synchronization signal IIT/LS are connected, and the CPU bus (ADRSBUS, DATABUS, CTRLBU) is connected to rewrite internal settings.
S), chip select signal CS is connected.

IIT video data B, G%R is E. R of ND converter
Input to OM3 2 1. The END conversion table is
For example, it may be configured to use RAM and load it from the CPU as appropriate, but since the device is in use and there is almost no need to rewrite it while image data is being processed,
, G, and H, and a ROM-based LUT (look-up table) method is adopted. It has 16 conversion tables and is switched by a 4-bit selection signal ENDSel.

The output of ROM3 2 1 after END conversion is 3 operation LS with 2 sides of 3 x 17} +7 squares for each color.
It is connected to a color masking section consisting of I322. Each path of the CPU is connected to the calculation LSI 322, and the CPU
From U to Max} IJ coefficients can be set.

CPU for image signal processing and rewriting by CPU.
A setup signal SU1 and a chip select signal CS are connected to switch to the U bus, and a 1-bit switching signal MONO is connected to select the matrix.

In addition, a power down signal PD is input to stop the internal video clock when the IIT is not scanning, that is, when not performing image processing.

The signals converted from B, G%R to Y, M, C by the calculation LSI 322 are sent to the second board (IPS
-B) After color conversion processing through the color conversion LSI 353, the image is input to the DOD LSI 323. The color conversion LSI 353 includes a threshold register for setting non-conversion colors, a color palette for setting conversion colors,
It has four color conversion circuits consisting of comparators, etc., and the DoD LSI 323 includes a document edge detection circuit,
It has a frame eraser circuit, etc.

The output of the DOD LSI323 that has undergone frame erasing is UCR.
The data is sent to the LSI 324 for use. This LSI includes a UCR circuit, a black generation circuit, and a necessary color generation circuit, and includes a process color X corresponding to the toner color in the copy cycle.
1 Outputs the necessary color Hue and edge signals. Therefore, this LSI includes a 2-bit process color designation signal CoLR, a color mode signal (4COLR
, MONO) are also input.

The line memory 325 is LSI for UCR 3 2 4
IIFOii for accumulating 4 lines of data in order to input each signal of process color
Consists of ○. Here, process color X and edge E d
For ge, 4 lines are accumulated and a total of 5 lines are sent to the digital filter 326, and for the necessary color Hue, it is delayed by FIFO and sent to the digital filter 326.
The signal is synchronized with the output of the MIX LSI 327 and sent to the MIX LSI 327.

The digital filter 326 is a 2X7 filter LS
There are 21&fl (low bass LP and high pass HP) 5 x 7 filters made up of three I, one performs processing for process color X, and the other performs processing for edge E dg
Processing for e is being performed.

The MIX LSI 327 performs halftone removal and edge emphasis processing on these outputs using a conversion table, and mixes them into process color X. Here, edge EDGE and sharp S are used as signals for switching the conversion table.
harp is input.

The TRC 342 consists of a 2K byte RAM that holds eight conversion tables. The conversion table is arranged so that the conversion table is rewritten using the carriage return period before each scan, and is switched by a 3-bit switching signal TRCSel. The processing output from here is sent to the LS for reduction processing from the transceiver.
Sent to I345. The reduction/enlargement processing section is an 8k byte RA
Two M344's are used to configure a ping pong buffer (line buffer), and an LS343 generates a resembling pitch and a line buffer address.

The output of the reduction/enlargement processing section returns to the EDF LSI 346 through the area memory section of the second board shown in FIG. 3(d). E
The DF LSI 346 is a DF that holds information on the previous line.
It has an IFO and performs error diffusion processing using information from the previous line. The signal X after the error diffusion process is transmitted to the SG LSI 34 constituting the screen generator.
7 and is output to the 10T interface.

With the 10T interface, the signal from the SG LSI 347 input as a 1-bit on/off signal is transferred to the LSI.
349, and sends it to the IOT in parallel in 8 bits.

In the second board shown in FIG. 8, the data actually flowing is 16 dots/mm, so the reduced LSI 35
4, the image is reduced to 1/4, binarized, and stored in the area memory. The expansion decoding LSI 359 has a fill pattern RAM 360, and when reading area information from the area memory and generating a command, it expands it to 16 dots, and performs logo address generation, color palette, and fill pattern generation processing. . The DRAMs 3 5 6 are configured on four sides and store coded 4-bit area information. AGDC355 is a dedicated controller that controls area commands.

An overview of the overall configuration of the image processing system has been described above, and next, generation of a halftone image according to the present invention will be described in detail.

(IV) Half-tone binary data generation circuit FIG. 9 is a diagram showing an example of the configuration of an intermediate 11-level binary data generation circuit.

The circuit that generates the binary data of the halftone image is shown in Figure 9 (
As shown in a), it basically has a matrix of threshold value data 701 and a comparator 702, and by comparing the threshold value data and input image data expressed in gradation with the comparator 702, when the image data is larger than the threshold value data, On the other hand, if it is small, an off signal is sent to the IOT, and this signal turns on/off the laser beam to obtain a gradation image 703 corresponding to the image data. The gradation image 703 shown in FIG. 9(a) has 4 bits,
This is an example in which image data of 16 gradations and r0111'' (gradation 7) is input.

By the way, as in the present invention, 62.5 μm (400 spi
) with a resolution of 8 bits and a density value of 256 gradations.
When reading a color original at T and attempting to reproduce it using the dither method, if the matrix of threshold data is small, a quantization error remains.

Therefore, there is a problem that gradation characteristics cannot be obtained unless the maximum value of the threshold value data is increased.

In other words, if you try to reproduce an image with 256 gradations in the same size as the matrix 701 shown in FIG.
As shown in (b), the threshold data matrix 704 is
A threshold value that increases by 16 in steps will be set. Alternatively, when using the matrix 701 shown in FIG. 3A, a conversion circuit for converting an 8-bit, 256-gradation density signal into a 4-bit, 16-gradation density signal is provided on the input side of the comparator. In this case, if the input image data has a gradation level of 111, for example, it becomes the same as the gradation image 703 shown in FIG.

Therefore, error diffusion processing is employed in order to improve tone reproducibility from a macro perspective by feeding noise on this quantization error.

This can be done by installing a density detection circuit 705 on the output side of the controller 702, as shown in Fig. (quantization error). In the same figure), the subtraction circuit 70
6 is for finding the quantization error, and in the case of the gradation image 703 shown in FIG. The quantization error of 15 is obtained by subtracting the gradation level 111 of the image data. Then, in the addition circuit 707,
This quantization error 15 is added to the next image data. Therefore, when the next image data has a gradation level of 111, the quantization error l5 is added to it, so that the gradation m126 is input to the comparator 702, and the number of ons increases. In other words, quantization errors are sequentially diffused backwards to improve tone reproduction when viewed from a macroscopic perspective.

Based on this idea, theoretical gradation reproduction can be improved just by having one fixed threshold value data. In this case, for example, 25
For 6 gradations, there will be 128 threshold data. However, in reality, dot reproduction becomes irregular, unstable, and noisy.In other words, although the gradation characteristics are improved,
Resolution, sharpness, and graininess deteriorate.

As mentioned above, when creating a halftone image without error diffusion processing, if you use a large-sized threshold matrix and try to create one with good gradation and a short screen pitch, However, there are still many problems in terms of fast cutting at the edges of lines and characters and the number of gradations.

Therefore, when creating a line screen with good edge reproducibility, one pixel is subdivided in the main scanning direction as shown in Figure (C), and the line-wise thresholds connected to this main scanning direction are set. array is adopted. Then, in combination with error diffusion processing, a line screen with good edge reproducibility is created, improving the problems caused by the dithering method as described above, improving the reproducibility of the edge portions of letters and pictures, and reducing graininess. ,
Improve gradation. In the case of dot screens, growth nuclei are generally formed, resulting in poor resolution and problems such as characters being cut off in the middle, but in the case of line screens, there are no breaks in the lines, so The edges of lines, characters, etc. will be reproduced smoothly. Moreover, it is also possible to create a screen that grows dots line by line.

(B) Switching of threshold data FIG. 10 is a diagram showing an example of the configuration of a halftone image generation circuit equipped with a threshold data switching circuit.

In FIG. 10(a), the threshold value data 762 has a fixed threshold value and a triangular wave or halftone threshold value, and the selector 7 switches between these and supplies the threshold value to the converter 764.
63, and an edge detection circuit 761 outputs a switching signal. The edge detection circuit 761 performs edge detection from input image data, and when an edge is detected, selects a fixed threshold value of the threshold value data 762,
If no edge is detected, the selector 763 is controlled to select the triangular wave or halftone threshold of the threshold data 762. The correction circuit 767 consists of a line buffer and a weighting coefficient processing circuit (error filter), and multiplies the quantization error by a predetermined coefficient and sends data near the input image data to the addition circuit 768. By using a fixed threshold for edges and using triangular wave or halftone thresholds for other areas, it is possible to eliminate the noise and unnatural feeling that tends to occur in the transition area between characters and halftones, resulting in high quality characters,
It becomes possible to reproduce halftones.

Further, FIG. 10(b) shows an example in which the threshold value is changed depending on the density gradient of the image.

With conventional ED (Error Diffusion) type screens, low-frequency structures and unsightly patterns occur when generating line screens, and the reproduction of definition is also poor, but the example shown in Figure 10) It is intended to improve the Comparison evening? 70 and averaging circuit? 71 is
Image data d1 input through digital filter 769
On the other hand, the previous image data d2 is also input, that is, the image data diSd2 for two consecutive pixels is input. Comparison evening? 70 controls the selector 763 by comparing which of them is larger;
When the concentration tends to increase, that is, when di>d2, select the threshold data of the pattern "rf2345678", and conversely, when di<d2, select the threshold data of the pattern r8765432.
1'' pattern is selected. Also, the averaging circuit? 71 is for two consecutive pixels (dl+d2)
/2, and uses this as image data for screen generation in the addition circuit 76 for error diffusion processing.
8. In this way, the number of dots is determined based on the averaged value of the input data for every two pixels, and the pattern of the threshold data to be adopted is switched depending on the density gradient (large/small difference) of the image data between these two pixels. With a simple hardware configuration, it is possible to improve the unsightly patterns of low-frequency structures and improve definition reproduction.

(C) Control of screen generator and error diffusion processing FIG. 11 is a diagram showing an example of a circuit configuration for selecting a threshold matrix and an error diffusion coefficient using a select signal.

If images such as text, photographs, and drawings are mixed in the same manuscript,
The threshold matrices and error diffusion coefficients suitable for each are different. Therefore, as shown in FIG. 11, the threshold matrix and error diffusion coefficient are selected using a designated area signal in the document or an image type signal detected by prescanning or the like as a selection signal. In this example, two types of screen generator threshold matrix 775 and two types of coefficients 776 for error conversion processing are prepared, and these are selected by the selector 76 using a 1-bit select signal.
3 and 777 for switching and selection. In this way, you can change the select signal within the same document by e.g.
1”, threshold matrix 775 8 and coefficient 776
If you select ``a'' and select ``OJ'', you can select B of threshold matrix 775 and b of coefficient 776, so that even originals containing a mixture of images such as text, photographs, and drawings can be matched to each image type. It becomes possible to reproduce the

The error diffusion coefficient is a weighting coefficient that multiplies the quantization error between the input image data and the output data detected by the subtraction circuit 766, and is usually applied to several pixels before the input image data by l lines, or even The error data of the previous pixel is multiplied by a coefficient and added. For example, if we concatenate four error data, the weighting coefficient cl,
c2. The sum of C3nC4 becomes l.

FIG. 12 is a diagram showing an example of the configuration of the concentration detection circuit. The output of the comparator 764, which constitutes the screen generator, is a serial 2 signal in which "1" turns on the IOT radar dot and "0" turns it off based on the comparison between the input image data and the threshold value data. It becomes valued data.

Therefore, in order to match this with the input image data and detect the quantization error, as shown in FIG.
It is necessary to count and convert this into concentration. The counter 765a counts this "l", the selector 765b decodes the count value and generates a register select signal, and the registers 765cO to 765c7 store converted concentration values. .

Assuming that the input image data is 8 bits and has 256 gradations, and it corresponds to the output data of 8 turns/offs, the converted density value will be 32 higher in gradation every time the count increases by one. Become. As explained earlier, when attempting to perform error diffusion processing on a pixel-by-pixel basis by dividing a pixel into four line patterns, similarly, 256 8-bit gradations can be expressed using four sets of gain/off data. Therefore, each time the count increases by one, the converted density value increases by 64.

register? The concentration conversion value of any one of 65cO to 765c7 is selected and output by the selector 765b, and the subtraction circuit (not shown, the subtraction circuit 766 shown in FIG. 11)
) is subtracted from the input image data of the comparator 764.

FIG. 13 is a diagram showing the configuration of a correction circuit for data inserted into the pixel of interest.

As shown in FIG. 13(a), the correction pixels added to the target pixel A for error diffusion processing are one line before and before and after that, and each data is
%xII◆If the 2% coefficients are cO, cl, c2, the data y7 to be concatenated is: 3F+t =cQXx, +CIXXn+1 +C2XX
It is expressed as l%02. Correction calculation circuit 778 in the same figure (b)
performs the above calculation, and this y. , is delayed in order to add it to the pixel of interest which is l line delayed.
It is FO779. The shifter 78o has a 1-bit register in the error diffusion processing circuit, and depending on this value, it is possible to switch whether the error data in the circuit represents 1 gradation or 2 gradations with 1 bit. In this case, error data of -256 to 254 or -128 to 127 can be handled while the error data path remains 8 bits.

Note that the present invention is not limited to the above embodiments, and various modifications are possible. For example, in the above embodiment, the binarized data is compressed and converted and output.
The compressed data may be stored in the memory and the data may be used for editing processing. Also,
The content of the editing process may be stored in the memory and also displayed on the CRT screen, so that the content of the collection can be confirmed and other information regarding the editing can be provided.

〔Effect of the invention〕

As is clear from the above description, according to the present invention, high-resolution binary data is compressed and converted into a low-resolution pixel block by block, so it is possible to display an image to be printed on a CRT. You can check in advance what the output image will look like after making layout and other edits. Furthermore, since a block unit of multiple pixels is compressed and converted into the gradation expressed by that block, a high-quality image can be reproduced.

[Brief explanation of drawings]

FIG. 1 is a diagram showing an embodiment of a binary data conversion method of an image processing device according to the present invention, FIG. 2 is a diagram showing an example of the configuration of a circuit that compresses and converts binary data in units of blocks, and FIG. is 2
A diagram showing another embodiment of the present invention for compressing value data into multi-value data, FIG. 4 is a diagram showing a configuration example of a compressed multi-value data generation system equipped with a correction processing circuit, and FIG. FIG. 6 shows an example of a configuration in which a memory is inserted for storage.
The figure shows the outline of the IPS module configuration, and Figure 7 shows the I
Figure 111 to explain each module of PS Ill5jt! I is a diagram showing an example of a configuration of a halftone image generation circuit equipped with a threshold data switching circuit, FIG. 12 is a diagram showing an example of a circuit configuration for selecting a threshold matrix and an error diffusion coefficient using a select signal, and FIG. The figure is a diagram showing an example of the configuration of a concentration detection circuit. ■...IIT,2...IPS13...SG,4.
...I○T, 5...signal conversion means, 6...memory,
7...CRT0 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 7 (a) Figure 7 (d) (e) Figure 7 (f) Figure 7 (k) Figure 7 (i) ■c-11111 (1) (shrink no》\) (#.person) Figure 7 (n) Figure 7 (p) (q) Steam Figure 8 (c) Figure 9 Figure 10 Figure (Q) Monthly 13 Figure CDCIC2

Claims (8)

[Claims] (1) A binary data conversion method for an image processing device that compresses and converts binary image data, in which the number of turned-on pixels in a block composed of multiple pixels is counted, and one pixel image data is calculated from the counted value. Binary data conversion of an image processing device, characterized in that the image processing device comprises a conversion means for generating the image data, and an output means for outputting the image data, and is configured to compress and convert binary input image data into low resolution image data. method. (2) The conversion means has a threshold corresponding to the conversion gradation, generates binarized image data by comparison with the threshold, and converts the count value and the binarized image data into the conversion gradation. 2. The binary data conversion method for an image processing apparatus according to claim 1, wherein the input count value is corrected based on an error with a converted value. (3) The binary data conversion method for an image processing apparatus according to claim 1, wherein the conversion means uses the number of pixels forming the block as the number of output gradations, and outputs the counted value as image data expressed by gradation. (4) The binary data conversion method for an image processing apparatus according to claim 1, wherein the conversion means generates image data by multiplying a ratio of the count value to the number of pixels forming the block by a maximum gradation value. (5) A binary data conversion method for an image processing apparatus according to claim 4, wherein the image data is averaged by surrounding pixels. (6) Binary data of the image processing apparatus according to claim 1, characterized in that the output means includes a display means for displaying the output image data of the conversion means, and the compressed and converted data is used as display data on the display. Conversion method. (7) A binary data conversion method for an image processing apparatus according to claim 1, characterized in that the output means includes means for outputting a halftone image of input binary data. (8) The conversion means has a memory for storing the compressed and converted data, and outputs the data stored in the memory to the output means, and also converts it inversely to the level of the input binary data and outputs it to the output means. 2. The binary data conversion method for an image processing apparatus according to claim 1, wherein the binary data conversion method is made selectable.