JPH03928B2 - - Google Patents

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention is an oversampling type digital-analog converter that achieves a high conversion speed by performing a conversion operation at a very high frequency compared to the signal frequency. This invention relates to converters (hereinafter referred to as D/A converters), and in particular to oversampling D/A converters that are suitable for integration, are compact, and can economically perform high-precision D/A conversion. be.

[Conventional technology]

When decoding an analog signal from a sampled digital signal, it is known that the original signal can be reproduced by setting the sampling frequency ( _S ) twice the signal frequency band ( _BW ) according to Nyquist's theorem. Therefore, the general D/A
The sampling frequency ( _S ) of the converter is selected to be approximately twice the signal frequency band ( _BW ).

On the other hand, an oversampling type D/A converter aims to improve conversion accuracy by setting the sampling frequency ( _S ) to a frequency higher than twice the signal frequency band ( _BW ).

Then, a digital-to-analog conversion circuit (hereinafter referred to as
The conversion accuracy of the D/A conversion circuit (abbreviated as D/A conversion circuit) is determined by resolution and linearity. Generally, the output voltage is generated by dividing the reference voltage using a resistive element or a capacitive element, so it is possible to increase the resolution by increasing the number of elements.
However, if the individual output voltages are not exactly on a straight line, the decoded analog voltage will be distorted. Furthermore, since linearity depends on the accuracy of the elements used, a large number of high-precision elements are required to realize a high-precision D/A conversion circuit.

However, with the low resolution of binary output (1-bit resolution) and ternary output (2-bit resolution), the output voltage can be obtained without using multiple elements, so high linearity is achieved regardless of the relative accuracy of the elements. realizable. For example, in the case of binary output, any two points lie on a straight line, so linearity is basically not a problem. In the case of three-value output, three highly linear voltages can be obtained by charging or discharging one capacitive element with a reference voltage in the positive or negative direction. In other words, since linearity can be ensured in a D/A conversion circuit with a low resolution of 1 to 2 bits, high conversion accuracy can be achieved by reducing errors caused by low resolution. To convert a high-resolution digital signal, for example, about 16 bits, to a low-resolution digital signal, for example, 1 to 2 bits, the lower bits are rounded down or rounded up, and this process is called quantization. In other words, by reducing the quantization error caused by quantization, high conversion accuracy can be achieved even with a low resolution D/A conversion circuit.

This quantization error is the difference between the input value and the quantized value, and is a random value within the amplitude range of ±1/2V _q with respect to the small quantization step size (V _q ). Therefore, the frequency spectrum of quantization noise caused by quantization errors is uniformly distributed within the 1/2 _S band.

FIG. 8 shows the frequency spectrum distribution of quantization noise when a quantization error occurs within the range of ±1. In this figure 8, the horizontal axis is FREQ (KHz), and the vertical axis is
FIG. 3 is a characteristic diagram showing frequency spectrum distribution characteristics of quantization noise expressed in LEVEL (dB). However, _S = 2048KHz, 0dB = sine wave with peak value 1, spectrum width 500Hz.

Since the total sum of quantization noise power is determined by the noise amplitude, the higher the sampling frequency _S is, the more the noise is dispersed over a wider band and the level of each spectrum is lowered. Here, signal frequency band ( _BW ) =
If 16KHz and sampling frequency _S = 2048KHz are used to remove quantization noise above 16KHz using a filter, the quantization noise power remaining within the signal band will be 2.
_BW / _S is reduced to 1/64.

That is, by oversampling the sampling frequency _S determined by Nyquist's theorem by 64 times, the quantization noise power is reduced to 1/64 times, and the S/N ratio is improved by about 18 dB. This S/N ratio improvement effect is equivalent to increasing the resolution of the D/A conversion circuit by 8 times (3 bits).

Next, Δ-Σ type oversampling D/A
A configuration called a converter is shown in FIG.
Then, this Δ-Σ type oversampling D/
Examples of the A converter include those described in the following literature. IEEE JOURNAL OF SOLID STATE CIRCUIT
SOLID-STATE CIRCUITS AUGUST 1981
VOL-SC-16No.4, T.Misawa, JEIwersen,
“Single−Chip per Channel Codec with
Filters Utilizing Δ−Σ Modulation”PP333
~341).

In this FIG. 10, 1 is a signal input terminal, 2
is a signal output terminal, 3 is a quantizer, 4 is a D/A conversion circuit, 5 is an integration circuit, 5-1 is an integrator constituting this integration circuit 5, 6 is an adder, and 7 is a quantizer 3. This is a delay circuit inserted between the connection point of the D/A conversion circuit 4 and the adder 6. This figure 10 is designed so that the quantization noise is distributed more in the high frequency range by the integrating circuit 5, and the frequency spectrum distribution characteristics of the analog output signal appearing at the signal output terminal 2 are shown in figure 9. show. This figure 9 shows the characteristics when the quantizer 3 in figure 10 generates a quantization error in the range of ±1, similar to the characteristic shown in figure 8, _S = 2048KHz, 0dB = peak value 1
This is a sine wave with a spectrum width of 500Hz.

As is clear from comparing Figures 8 and 9, Figure 9 has a lower noise level in the low frequency range.
The noise level is increasing in the high frequency range. Therefore, the effect of improving the S/N ratio is greater than the method of simply increasing the sampling frequency ( _S ).

The integrating circuit 5 in FIG. 10 is configured with one integrator 5-1 (single integral type), but the integrating circuit 5 in FIG. 11 showing a double integral type configuration
is composed of two integrators 5-2, 5-4 and an adder 5-3. The configuration shown in FIG.
Quantization noise is lower in the low frequency range than in the configuration shown in FIG. In addition, in this Figure 11,
The same reference numerals as in FIG. 10 indicate corresponding parts.

In FIGS. 10 and 11, 7 is a delay circuit inserted between the output terminal of the quantizer 3 and the adder 6, and has a delay time of T=1/ _S . Further, the bold line portion indicates a digital signal, and the output of the quantizer 3 is restored to an analog value by the D/A converter circuit 4. Then, the quantization noise voltage generated by the quantizer 3 is
The noise voltage V _TN appearing at the signal output terminal 2 when V _qN and the transfer characteristic of the integrating circuit 5 are H _(Z) is expressed by the z function of equation (1).

V _TN =V _qN /(1+Z ^-1 ·H _(Z) )...(1) However, Z ^-1 = e ^-jwT , W = 2π, T = 1/ _S .

Here, the noise component V _TN is
This is a noise voltage caused by a conversion error of the D/A converter shown in FIG. And the integrating circuit 5 in Fig. 10
The transfer characteristic H _(Z) is H _(Z) = 1/(1-Z ^-1 ), the 11th
The transfer characteristic H _(Z) of the integrating circuit 5 shown in the figure is H _(Z) = (2-
Since Z ^-1 )/(1-Z ^-1 ) ² is substituted into equation (1), the noise component V _TN in FIGS. 10 and 11 can be obtained from equations (2) and (3), respectively.

V _TN = V _qN・(1−Z ⁻¹ ) …(2) V _TN = V _qN・(1−Z ⁻¹ ) ² …(3) The frequency characteristic of (1−Z ⁻¹ ) is expressed by equation (4) is required.

(1-Z ^-1 )=1-e ^-jWT =2sin( _1π / _S )...(4) Then, the quantization noise voltage _VqN is a white noise distributed at a uniform level within the band of _S /2. Since it is noise, it is clear from the frequency characteristic of equation (4) that the lower the frequency component of the noise component V _TN , the lower the level. Also, from the relationship of the noise spectral distribution characteristics shown in Figures 8 and 9, the sampling frequency _S
In addition to the fact that the quantization noise V _qN is distributed over a wide band and the noise level is reduced by increasing the
It can be seen that the low frequency noise level decreases according to the frequency characteristic shown by equation (3).

A D/A converter that improves the S/N ratio by changing the frequency distribution characteristics of noise in this way is called a noise shaping type. Specifically, in the configuration shown in FIG. 10, if _BW = 16 KHz and _S = 2048 KHz, the in-band noise level is attenuated by about 31 dB from equation (2). As mentioned above, when combined with the S/N ratio improvement effect of 18 dB due to the wide band dispersion of quantization noise, the S/N ratio improvement effect of the configuration shown in FIG. 10 is about 49 dB.

On the other hand, in the configurations shown in FIGS. 10 and 11, integrators 5-1, 5-2, and 5-4 are generally composed of digital adders and registers, and the word length of the input signal ( When the number of bits is long, the delay time of the adder is longer than that of the register or quantizer. Therefore, the operating speed of the integrator predominantly determines the upper limit of the sampling frequency _S. In Figure 11, two integrating circuits are used in series, which requires twice the processing time compared to the configuration shown in Figure 10, so the upper limit of the sampling frequency _S is limited to approximately 1/2. . Therefore, even if two integrating circuits are connected in series to improve the S/N ratio, the effect will be halved. Specifically, _BW =
S/N in Figure 11 assuming 16KHz, _S = 1024KHz
When calculating the ratio improvement effect, the improvement effect due to quantization noise dispersing over a wide band is about 15 dB, and the noise
The improvement effect of shaving is approximately 47 dB from equation (3).
The total is 62dB. In the configuration shown in FIG. 10, the S/N ratio improvement effect was 49 dB, so it can be seen that the S/N ratio was improved by only 13 dB even though the circuit scale was increased.

When the resolution of the quantizer is Nq bits and the signal voltage range is ±1, the root mean square value of the quantization error _qN ² is 1/12 (2 ^{2 - Nq} ) ² , which is a sine wave at the peak level. Since the average voltage of is 1/√2, its S/
The N ratio is 10log(6/(2 ^{2 -Nq2} ) [dB].

In other words, the S/N ratio of only the quantizer is 6×(Nq−
1) Calculated using the formula +1.8 [dB]. In the configuration shown in Figure 11, the amount of improvement in the S/N ratio is as described above.
62dB ( _BW = 16KHz, _S = 1024KHz), so when the resolution of the quantizer is 2 bits (the D/A conversion circuit outputs 3 values), the S/N ratio of the quantizer alone is 7.8dB. 69.8dB with an improvement of 62dB added to
It is.

FIG. 12 shows the configuration shown in FIG. 10 when the error voltage generated in the quantizer 3 is ±0.5.
The spectrum distribution of the A conversion circuit output is obtained. ( _S = 2048KHz, 0bB = sine number of peak value 1, spectral width = 62.5Hz).

In this Figure 12, the horizontal axis is FREQ. (KHz), and the vertical axis is
This is a characteristic diagram showing the relationship between the nonlinear error of the D/A conversion circuit expressed in LEVEL (dB) and the output noise frequency spectrum distribution characteristic, where a is the D/A conversion circuit 4.
b shows the case where there is no nonlinear error (0%), and b indicates that the nonlinear error of the D/A conversion circuit 4 is 0.5
% is shown.

In Fig. 12, HD indicates the harmonic distortion component, and b indicates the input signal (=
It can be seen that harmonic distortion of 1062.5Hz) is generated. Here, _BW = 16KHz and most of the harmonic distortion components are included below the signal frequency band _BW .
The S/N ratio is limited by harmonic distortion components. In the case of this FIG. 12b, the S/N
The ratio is limited to approximately 46dB. Since the relative accuracy of resistors and capacitive elements formed on an integrated circuit is about 0.5 to 0.05% if no fine adjustment is made after manufacturing, the upper limit value of the S/N ratio is 46 to 66 dB.

Therefore, even if the resolution of the D/A conversion circuit is increased beyond 2 bits, nonlinear errors become a problem and the S/A
It can be seen that this is meaningless in terms of improving the N ratio.

[Problems to be solved by the invention] As mentioned above, in the conventional D/A converter, the S/N
Even with the configuration shown in FIG. 11, which has a large ratio improvement effect,
The S/N ratio at _BW = 16KHz, _S = 1024KHz is
Low at 69.8dB. In addition, in order to perform high-quality D/A conversion when an audio signal is used as the input signal, it is desirable that the D/A converter has a signal bandwidth of 15 KHz or more and an S/N ratio of 80 to 90 dB or more. It will be done.

Therefore, the conventional circuit has the disadvantage that it cannot be applied to high quality audio signals.

[Means for solving problems]

The oversampling type digital
An analog converter consists of an integrating circuit that receives the difference between an input terminal digital signal and a feedback signal, a quantizer that reduces the resolution of the digital output of this integrating circuit, and a low resolution obtained by this quantizer. Means for converting the output of the quantizer, which is a digital signal, into the feedback signal, and an analog signal obtained by passing the quantizer output through a digital-to-analog conversion circuit and a circuit that processes the quantizer output in the same way as the feedback signal. a first quantization loop for obtaining a loop output signal from the input terminal digital signal at each sampling frequency sufficiently higher than the input signal frequency; It has a total of N quantization loops (N: an integer of 2 or more) having the same configuration as the above first
An n-th quantization loop (n: an integer from 2 to N) which inputs a digital input signal to the input terminal of the quantization loop and inputs the output of the (n-1)th quantization loop to the input terminal. and the above first
From the quantizer output of the n-th quantization loop, a differentiating circuit having a transfer characteristic that is inversely related to the product of the transfer characteristics of the integrating circuit included in each of the (n-1)th quantization loops from The analog output signal is inserted into a path for obtaining a loop output signal, and the signal obtained by adding all the first to Nth loop output signals is used as an analog output signal.

[Effect]

Noise-shaving type D/A converters are connected in multiple stages, and quantization errors generated in the previous stage are requantized by the next stage.

〔Example〕

Hereinafter, embodiments of the present invention will be described in detail based on the drawings.

FIG. 1 is a block diagram showing an embodiment of an oversampling type D/A converter according to the present invention, and shows a case where two loops each include a quantizer.

In the figure, 11 is a signal input terminal, 12 is a signal output terminal, 13 is an integration circuit that receives the difference between the input digital signal and the feedback signal, 14 is a quantizer that reduces the resolution of the digital output of this integration circuit, and 1
5 is a delay circuit which inputs the output of this quantizer 14, 16 is a D/A converter circuit which converts the digital signal output from this delay circuit 15 into an analog signal, and 17 is inputs the output of quantizer 14. 18 is an adder which receives the digital signal from the signal input terminal 11 and the feedback signal from the delay circuit 17, and the output of this adder 18 is sent to the integrating circuit 13.
is configured to be supplied to 19 is a delay circuit that receives the output of the integrating circuit 13; 20 is an adder that receives the output of the delay circuit 19 and the output of the delay circuit 17; 21 is a delay circuit that receives the output of the adder 20 and the output of the delay circuit 24; 22 is an integrator that takes as input the difference between the input digital signal output from this adder 22 and the feedback signal; 23 is a quantizer that reduces the resolution of the digital output of this integrator circuit 22; 24 is a delay circuit which receives the output of this quantizer 23 as an input and supplies the output to the adder 21 as a feedback signal; 25 is a differentiation circuit that differentiates the output of the quantizer 23; and 26 is the output of this differentiation circuit 25. A D/A conversion circuit 27 converts a digital signal into an analog signal.
6 and the output of the D/A conversion circuit 16, and is configured so that the output of the adder 27 can be obtained at the signal output terminal 2. Note that the thin line portion indicates a digital signal, and the thick line portion indicates an analog signal.

The integration circuits 13 and 22 have a larger gain as the frequency of the input signal is lower, and their transfer characteristics are assumed to be H ₁ and H ₂ . Further, the differentiating circuit 25 has a characteristic opposite to that of the integrating circuit, and its transfer characteristic is reduced to 1/1.
Let it be _H3 .

In the embodiment shown in FIG. 1, the integrating circuit 13,
Quantizer 14, delay circuit 17, and adder 18
The integration circuit 22, the quantizer 23, the delay circuit 24, and the adder 21 constitute the second loop.

Next, the operation of the embodiment shown in FIG. 1 will be explained.

First, the difference between the outputs of the first loop integration circuit 13 and the quantizer 14 is determined by the adder 20, and is used as an input signal to the second loop. Then, the output of the quantizer 14 in the first loop and the signal obtained by processing the output of the quantizer 23 in the second loop by the differentiating circuit 25 are converted into analog values by D/A conversion circuits 16 and 26, respectively. After that, an adder 27 adds the signals to obtain an analog output signal. Here, the quantizer 14,
Assuming the 23 quantization errors as V _qN1 and V _qN2 , respectively,
Find the error component included in the analog output signal.

Assuming that the output of the quantizer 14 of the first loop is V _O1 and the output of the integrating circuit 13 is V _H1 , V _O1 and V _H1 are obtained by equations (5) and (6), respectively.

V _O1 =V _FN・H ₁ /1+Z ^-1・H ₁ +Vq _N1 /1+Z ^-1・H ₁ …(5
) V _H1 =V _IN・H ₁ /1+Z ^-1・H ₁ −V _qN1・Z ^-1・H ₁ /1×Z ^-
1・H ₁ …(6) If the input signal of the second loop is V _IN2 , the above
Equation (7) is derived from Equations (5) and (6).

V _IN2 = (V _H1 − V _O1 ) = −V _qN1 …(7) Then, in equation (5) above, the error component of V _O1 is
This shows that the error is equivalent to the error of the conventional circuit determined by equation (1). Also, by finding the difference between V _O1 and V _H1 , the quantization error voltage of the quantizer 14 can be determined.
Equation (7) above shows that only V _qN1 can be detected.

Next, the analog output signal V _AO obtained at the signal output terminal 2 is obtained by equation (8).

V _AO =V _IN・H ₁ /1+Z ^-1・H ₁ +V _qN1 (H ₁ −H ₂ +Z ^-1 H ₂ H ₃ −
Z ^-1 H ₁ H ₂ / (1+Z ^-1・H ₁ ) (1+Z ^-1・H ₂ )H ₃ )+V _qN2
(1/(1+Z ^-1・H ₂ )H ₃ )...(8) And from this equation (8), the term V _qN1 is H ₁ = H ₂ =
It can be seen that if H ₃ , it is completely eliminated and becomes as shown in equation (9).

V _AO =V _IN・H ₁ /(1+Z ^-1・H ₁ )+V _qN2 /(1+Z ^-1・
H ₂ ) H ₃ …(9) The noise component of this equation (9) is V _TN , and the transfer characteristics of H ₁ to H ₃ are the characteristics of the first stage of integrator H ₁ = H ₂ = H ₃ = 1/
(1−Z ⁻¹ ), equation (10) is derived from equation (9).

V _TN = V _qN2・(1−Z ^-1 ) ² ...(10) And this equation (10) shows that the frequency characteristic similar to the above equation (3) of the conventional circuit shows that the noise voltage is distributed. ing. Here, when the resolution of the quantizer 23 is constant, the magnitude of the quantization error voltage Vq _N2 is
is proportional to the maximum input amplitude of the loop. Also, the second
Since the input of the loop is the quantization error voltage of the first loop according to the above equation (7), it is determined by the resolution of the quantizer 14 of the first loop.

Next, the range of the signal applied to the signal input terminal 1 is set to ±1, and the quantizers 14 and 23 have N q1 and N _q1 , respectively.
Assuming that the resolution is Nq ₂ bits, the amplitude ranges of the quantization errors V _qN1 and V _qN2 are expressed by equations (11) and (12), respectively.

−2 ^-(Nq1-1) ≦V _qN1 2 ^-(Nq1-1) …(11) −[2 ^-(Nq ₁ ^-1)・2 ^-(Nq2-1) ]V _qN2 [2 ^{-(Nq1-1 )}・2 ^(Nq2-1) ] ...(12) On the other hand, as mentioned above, regarding the linearity of the D/A conversion circuits 16 and 25, the linearity is ensured without depending on the element precision in the range of 1 to 2. Only for 2-bit resolution. Here, since the resolution of the D/A conversion circuit and the quantizer is the same, the quantizer is also generally 1 to 2 bits, so the above
From equations (11) and (12), in the case of 1 bit, both V _qN1 and V _qN2 have an amplitude range of ±1, and in the case of 2 bits, V _qN1
is ±0.5V, and V _qN2 has an amplitude range of ±0.25V. The relationship between V _qN and quantizer resolution in equation (3) of the conventional circuit is also as shown in equation (11), which is the same as V _qN1 , so the amplitude of V _qN2 in equation (10) is the same as V _qN in equation (3). Comparing the ranges, it can be seen that when the quantizer resolution is 1 bit, the quantizer resolution is the same, but when the quantizer resolution is 2 bits, V _qN2 becomes 1/2 of V _qN . If the quantizer resolution becomes even larger, V _qN2 becomes even smaller.

The case where equation (7) is used as the input signal V _IN2 of the second loop has been described. However, equation (6) can be approximated as V _H1 =V _qN1 in the low frequency range. The quantization noise component is exactly the same as equation (7), and the input signal component does not constitute noise, so the same operation will occur even if only the integrator output V _H1 is input to V _qN2 .

Next, improvement of the S/N ratio will be explained by comparing the embodiment shown in FIG. 1 with the conventional circuit.

Here, in order to compare the S/N characteristics with the conventional circuit shown in FIG. 10 and FIG.
The S/N ratio of the embodiment shown in FIG. 1 is determined in the same manner as in the case of determining the S/N ratio in the figure.

The transfer characteristic H ₁ of the integrating circuit 13 and the transfer characteristic H ₂ of the integrating circuit 22 in the embodiment shown in FIG.
And if the transfer characteristic H ₃ of the differentiation 25th stage is the characteristic of one stage of integrator {H _{1 to 3} = 1/(1−Z ⁻¹ )},
As described above, since the operating speed of the loops is predominantly determined by the integrator, each loop in FIG. 1 can operate in parallel at the same sampling frequency _S as in the configuration in FIG. 10. This point is different from that in which the sampling frequency _S in FIG. 11 is lowered to 1/2 of the sampling frequency _S in FIG. 10.

Therefore, when _BW = 16KHz, _S = 2048KHz, and the quantizer resolution is 2 bits, the amount of improvement due to quantization noise dispersing over a wide band is 18 dB, and the amount of improvement due to noise shaping is given by equation (10).
The improvement amount is 6 dB due to 59 dB and V _qN2 is reduced to 1/2 (from equations (11) and (12)), and the total amount of improvement is 83 dB. 6dB x (2 bits - 1) + S/N ratio
1.8dB+83dB=90.8dB is obtained. 11th above
Since the S/N ratio of the conventional circuit shown in the figure was 69.8 dBB, an S/N ratio as high as 21 dB can be achieved with the circuit according to the present invention.

The above S/N ratio calculation was performed on the assumption that the D/A conversion circuits 16 and 26 shown in FIG. 1 output correct values. However, this D/A conversion circuit 1 in FIG.
Since 6 and 26 are analog circuits, the accuracy of the output voltage deteriorates due to element accuracy.

The embodiment shown in FIG. 1 is an example in which two loops each include a quantizer, but in the present invention, two loops each include a quantizer.
It can also be composed of more than one.

FIG. 2 is a block diagram showing another embodiment of the present invention, in which it is constructed with three loops.

In FIG. 2, the same symbols as in FIG. 1 indicate corresponding parts, 28 is a delay circuit that receives the output of the integrating circuit 22, and 29 is a circuit that adds the output of this delay circuit 28 and the output of the delay circuit 24. Adder, 30
is an adder that adds the output of this adder 29 and the output of the delay circuit 33; 31 is an integrating circuit that receives the output of this adder 31; and 32 is a quantum circuit that reduces the resolution of the digital output from this integrating circuit 31. 33 is a delay circuit which receives the output of this quantizer 32 as an input and supplies the output as a feedback signal to the adder 30; 34 is a differentiation circuit that differentiates the output of the quantizer 32; 35 is this differentiation circuit 34; 36 and 37 are a delay circuit 15 and a D/A conversion circuit, respectively, for converting a digital signal from a digital signal into an analog signal.
A delay circuit 38 is inserted between the conversion circuit 16 and between the differentiating circuit 25 and the D/A conversion circuit 26.
An adder 39 adds the outputs of the adder 38.
This is an adder that adds the output of the D/A conversion circuit 16 and the output of the D/A conversion circuit 16 and sends the resulting signal to the signal output terminal 2.

In the embodiment shown in FIG. 2, the adder 3
A third loop constituted by 0, an integrating circuit 31, a quantizer 32, and a delay circuit 33 is added to the configuration of the embodiment shown in FIG.

Next, the operation of the embodiment shown in FIG. 2 will be explained.

First, the input V _IN3 of the third loop is input to the quantizer 23
This is the anti-phase waveform of the quantization error that occurs. That is, the connection relationship between the second loop and the third loop is exactly the same as the relationship between the first loop and the second loop in FIG.

Therefore, the output V _O2 of the adder 38 is obtained by equation (13) in the same way as equation (9).

V _O2 = {−V _qN2・H ₂ /1+Z ^-1・H ₂ +V _qN3 /(1+Z ^-1・H
₄ ) _H5 } 1/ _H3 ...(13) However, the transfer characteristic of the differentiating circuit 34 is 1/ _H5 · _H3 .

The analog output signal V _AO obtained at the signal output terminal 2 is determined by the sum of the above equation (5) and the above equation (13) V _O2 . Here, each transfer characteristic is H ₁ = H ₂
= H ₃ = H ₄ = H ₅ , this analog output signal
V _AO is calculated using equation (14).

V _AO =V _IN・H ₁ /1+Z ^-1・H ₁ +V _qN3 /(1+Z ^-1・H ₄ )・
H ₅ · H ₃ ... (14) The noise component of this equation (14) is V _TN , and the transfer characteristics of H ₁ to H ₅ are the characteristics of the first stage of integrator 1/(1-Z ^-1 )
Then, the above noise component V _TN can be found using equation (15).

V _TN = V _qN3・(1−Z ⁻¹ ) ³ …(15) In this way, by increasing the loop including the quantizer from two stages to three stages, the noise component V _TN is reduced.
As shown in equations (10) to (15), the quadratic equation has changed to a cubic equation. The number of loops can also be increased to four or more stages using the same technique used to increase the number of loops from two stages to three stages.

Figure 3 is a circuit diagram showing a specific example of the configuration of a D/A conversion circuit.
This is a D/A circuit with bit resolution.

In FIG. 3, V _REC is an input terminal to which a reference voltage is applied, and OUT is an output terminal. and,
40-1, 40-2...40-8 are switch circuits (analog switches), 41-1, 41
-2 and 41-3 are capacitive elements, and 42 is an operational amplifier.

Now, capacitive element 41-1 is C _S , capacitive element 41-
2 is C _I and the capacitive element 41-3 is C _B , the transfer characteristic H _DA from the input terminal V _REF to the output terminal OUT is expressed by equation (16).

H _DA = C _S / {C _I − Z ^-1・(C _I − C _B )} … (16) In this equation (16), the sampling frequency _S
Since Z ^-1 is approximately 1 in a sufficiently low signal frequency band, it can be seen that the gain is C _S / _CB . Then, by controlling the connection order of the switch circuits 40-1 to 40-4, the C _S of the capacitive element 41-1
Charges the V _REF voltage and outputs an analog voltage. At this time, charging can be performed in three ways by switching the charging direction and not charging, so it operates as a 1- to 2-bit D/A conversion circuit.

In this way, in a D/A conversion circuit using one capacitive element, linearity is not a problem as mentioned above, but the gain, that is, the absolute value of the output voltage is C _S /
C Varies depending on the capacity ratio of _B. Therefore, the accuracy of the gains of the D/A conversion circuits 16 and 26 shown in FIG. 1 becomes a problem. Here, the gain ratio of the D/A conversion circuit 26 to the D/A conversion circuit 16 is assumed to be α. (α1).
Then, when the noise component V _TN is determined in the same way as when formula (10) was derived, formula (17) is obtained.

V _TN = V _qN1・(1−α)・(1−Z ⁻¹ )) +V _qN2・α・(1−Z ⁻¹ ) ² …(17) As mentioned above, the capacitance ratio accuracy is 0.5~
If it is 0.05%, α = 0.995 to 0.9995, so the term (1-α) is 0.005 to 0.0005 (-46 to -66 dB)
becomes the size of Since the gain of (1-Z ^-1 ) is -26dB when _S = 2048KHz and _BW = 16KHz,
It can be seen that the term V _qN1 is at a level lower than V _qN2 by more than 20 dB. The amount of deterioration that the term V _qN1 gives to the S/N ratio is very small, about 0.05 dB or less. From this, the D/A converter used in the present invention can obtain a high S/N ratio without using elements with high ratio accuracy.

On the other hand, the transfer characteristics of the integrating circuit need not be completely equal to those of the integrator. The design condition for this integrating circuit is that the gain in the low frequency range, that is, the signal frequency band, is greater than the gain in the high frequency range.

The loop including the quantizer and integration circuit should stably follow the input signal without oscillating.

The inverse characteristic can be achieved using a differentiating circuit.

There are three points.

In addition, the transfer characteristics (H ₁ ,
H ₂ ...) must be equal, but even if the noise level increases in a high frequency band that is higher than the signal band, it will not deteriorate the S/N ratio within the signal band and will not be a problem. It is only necessary that the transfer characteristics within the band be exactly the same. however,
If it is desired to reduce the high frequency noise level outside the signal band, it is desirable that the transfer characteristics be equal across the entire band.

FIG. 4 is a block diagram showing still another embodiment of the present invention, which differs from FIG. 1 in that integrating circuits 42 and 43 are added to the structure shown in FIG. 1.

With this configuration, the integration circuit 42
Since the output of the quantizer 14 is compared with the input signal, if the level of the high frequency component contained in the input signal is low, the low frequency gain of the integrating circuit 42 is used to compare the output of the quantizer 14.
Even if the output value of is small, it is possible to follow the input signal. That is, the quantization error generated in the quantizer 14 is reduced, and a high S/N ratio can be achieved.

The analog output signal _VAO obtained at the signal output terminal 2 of the embodiment shown in FIG. 4 is expressed by equation (18). However, the transfer characteristics of the integrating circuits 42 and 43 are set to H ₆ and H ₇ , and the rest is the same as the embodiment shown in FIG. 1.

V _AO = V _IN (H ₁ H ₇ /1 + Z ^-1 H ₁ H ₆ ) + V _qN1 (H ₇ /1 + Z ^-1 H ₁
H ₆ −H ₂ / (1 + Z ^-1 H ₂ ) H ₃ ) + V _qN2 (1 / (1 + Z ^-1 H ₂ )
_H3 )
...(18) When the term in equation (18) is eliminated, it can be seen that the noise component is only the term V _qN2 and the frequency distribution characteristics become the same, similar to equation (9) in the explanation of Figure 1. . Also, the conditions for the V _qN1 term to disappear in the low frequency band are H ₁ = H ₂ = H ₃ and H ₆ = H ₇ in the low frequency band.
It is sufficient if the following conditions are satisfied. In order to completely eliminate this V _qN1 term, the transfer characteristics of H ₁ to _{H 7} may be selected as shown in equation (19).

Substituting this equation (19) into the above equation (18) leads to equation (20).

V _DO =V _IN +V _qN2 ·(1−Z ⁻¹ ) ² (20) From equation (20), it can be seen that the noise component is the same as equation (10) in the explanation of FIG. 1 above.

However, as described above, V _qN2 is smaller in the embodiment shown in FIG. For example, _BW =
When 16KHz and _S = 2048KHz, the gain of _H6 at 16KHz is about 26dB, so V _qN2 in the embodiment shown in Fig. 4 is smaller than that in the embodiment shown in Fig. 1.
Can be set 26dB lower.

Figure 5 shows the configuration shown in Figure 1, with one integrating circuit.
In the case of a stage integrator (H ₁ = H ₂ = H ₃ = 1/(1
-Z ^-1 ))), in which the same parts as in FIG.

The D/A conversion circuit in FIG. 5 is an application of the circuit example shown in FIG. is commonly used by the two D/A conversion circuits 16 and 26 in FIG. The charging circuit of the D/A conversion circuit 16 includes a capacitive element 41-1 and switch circuits 40-1 to 40-4, and the charging circuit of the D/A converting circuit 26 includes capacitive elements 41-4, 41-5 and switch circuits. Circuit 40-9, 40-10...4
0-14 are configured individually.

Further, the quantizers 14 and 23 each have a resolution of 2 bits, and the quantization voltage of the quantizer 14 is 0, ±V _REF , and the quantization voltage of the quantizer 23 is 0, ±1. /2V _REF .

The differentiating circuit 25 also includes a delay circuit (register) 2.
5-2 and an adder 25-1, and realizes the characteristic of 1/H ₃ =(1 −Z ⁻¹ ). Then, in the output of this differentiating circuit 25, the quantized voltage has five values of 0, ±1/2 V _REF , ±V _REF , so the capacitive element 41
The capacitance values of -4 and 41-5 are set to 1/2 of 120, and the switch control circuit 51 controls charging of the two capacitive elements. Further, charging of the capacitive element 41-1 is controlled by a switch control circuit 50. And the first
Integrating circuits 13 and 24 in the figure are composed of registers and adders, so H ₁ = H ₂ = 1/(1-Z ^-1 )
In the case of the characteristic, the adders 18, 20,
21 and delay circuits (registers) 15, 17, 19,
24, it can be simplified as shown in FIG.

FIG. 6 shows the frequency spectrum distribution characteristics of the analog signal output of FIG. 5. However, _S =
2048 KHz, 0 dB=sine wave with peak value of V _REF , spectrum width=500 Hz, and the same conditions as in FIGS. 8 and 9 described above. When compared with FIG. 6 and FIG. 9, it is clearly seen that the noise level in the low frequency region has decreased significantly.

FIG. 7 shows the S/N characteristics of the embodiment shown in FIG. And this figure 7 shows that _S = 2048KHz, _BW
= 16KHz, the horizontal axis is the input signal amplitude level LEVEL (-DB), and the vertical axis is the S/N ratio S/N (DB).
It is.

As is clear from the S/N characteristics shown in Fig. 7, the S/N is linear with respect to the input signal amplitude level.
It can be seen that the ratio changes. This characteristic is almost the same as that of a general linear 15-bit A/D converter.
Also, the S/N ratio obtained from the above calculation formula is
It can be seen that the S/N ratio was 90.8 dB, which is almost the same as the S/N ratio of the 0 dB input level shown in FIG.

〔Effect of the invention〕

As explained above, according to the present invention, by performing multi-stage quantization processing using multiple quantization loops, the noise level in the low frequency band can be significantly reduced, compared to the sampling frequency _S. This has the advantage that very high S/N characteristics can be obtained in a sufficiently low signal frequency band. In addition, since multiple quantization loops can be processed in parallel, high-speed processing is possible and _a high sampling frequency _S can be achieved.
This has the advantage that the improvement effect is even greater. In addition, the resolution of the quantizer and D/A circuit can achieve high linearity regardless of element precision, and high S/N characteristics can be achieved even with a low resolution of 1 to 2 bits. Since the relative accuracy of circuit A is sufficient to be easily realized on an integrated circuit, there is no need for high-precision elements, so there is no need for post-processing such as fine adjustment after manufacturing, so it has the advantage of being economical to manufacture. Therefore, the practical effect is extremely large.

Furthermore, as is clear from the embodiment shown in FIG. 5, although the scale of the analog circuit is very small, a relatively large number of digital circuits are required in the quantization loop. However, as the miniaturization of integrated circuits progresses, digital circuits have become more highly integrated than analog circuits, so the chip area can be reduced, making it a method suitable for integrated circuits. This is extremely effective in that a high-precision D/A converter can be realized economically.

As described above, the present invention has significant effects compared to conventional D/A converters, and achieves high conversion accuracy by performing conversion operations at a frequency that is much higher than the signal frequency. This is a unique oversampling D/A converter that achieves this.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of an oversampling type digital-to-analog converter according to the present invention, FIG. 2 is a block diagram showing another embodiment of the present invention, and FIG. FIG. 4 is a block diagram showing still another embodiment of the present invention, and FIG. 5 is a specific example of the embodiment shown in FIG. 4. FIGS. 6 and 7 are characteristic diagrams showing output noise frequency spectrum distribution characteristics and S/N characteristics for explaining the present invention, and FIGS.
FIG. 9 is a characteristic diagram showing the frequency spectrum distribution characteristics of quantization noise used to explain the present invention. FIG. 9 is a characteristic diagram showing the output noise frequency spectrum distribution characteristics of a conventional oversampling D/A converter. FIG. FIG. 11 is a block diagram showing an example of a conventional Δ-Σ type oversampling D/A converter. FIG. 12 is a block diagram showing another example of a conventional Δ-Σ type oversampling D/A converter. FIG. 12 is an explanatory diagram showing the relationship between a nonlinear error and an output noise frequency spectrum distribution characteristic for explaining the operation of FIGS. 10 and 11. FIG. 13...Integrator circuit, 14...Quantizer, 15...
...Delay circuit, 16...D/A conversion circuit, 17, 1
9...Delay circuit, 20, 21...Adder, 22...
... Integration circuit, 23 ... Quantizer, 24 ... Delay circuit, 25 ... Differentiation circuit, 26 ... D/A conversion circuit, 27 ... Adder, 28, 33 ... Delay circuit,
30, 38, 39... Adder, 31... Integrating circuit, 32... Quantizer, 34... Differentiating circuit, 35
...D/A conversion circuit, 42, 43... Integration circuit.

Claims (1)

[Claims] 1 An integrating circuit that receives the difference between the input terminal digital signal and the feedback signal, a quantizer that reduces the resolution of the digital output of this integrating circuit, and a low-resolution digital signal obtained by this quantizer. In a quantization loop configured with the output of the quantizer as the feedback signal, the quantizer output is directly used as the feedback signal and the quantizer output is used as the output signal of the quantization loop, or the quantizer output is used as the output signal of the quantization loop. The output is passed through a frequency characteristic conversion circuit such as a filter or an integrator as a feedback signal, and the signal obtained from the quantizer output through a circuit with the same transfer characteristic as the frequency characteristic conversion circuit is used as the output signal of the quantization loop, and the input signal is The quantization loop converts the input terminal digital signal into a low-resolution digital output signal at each sampling frequency sufficiently higher than the signal frequency, and the quantization loop with the same configuration as the above quantization loop is used to convert the input terminal digital signal into a low resolution digital output signal.
(an integer of 2 or more), inputs a digital input signal to the input terminal of the first quantization loop, and integrates the (n-1)th (n is an integer from 2 to N) quantization loop. A difference signal between the circuit output and the quantizer output is input to the input terminal of the n-th quantization loop, and the first
The output signal of the nth quantization loop is input to a differentiating circuit having a transfer characteristic that is inversely related to the product of the transfer characteristics of the integrating circuits included in each of the (n-1)th quantization loops. , the outputs of the differentiating circuits of the second to Nth quantization loops and the outputs of the first quantization loop are all added together, and then one digital-to-analog conversion circuit obtains an analog output signal, or The outputs of the differentiating circuits of the second to Nth quantization loops and the outputs of the first quantization loop are separately converted into analog voltages by digital-to-analog conversion circuits, and then all are added to generate an analog output signal. An oversampling type digital-to-analog converter characterized in that it obtains the following.