JPH0392100A - Sound field processing device - Google Patents

Abstract

PURPOSE:To relieve the load of the software handling a modulation control system by employing a multiplier provided with an interpolation circuit. CONSTITUTION:An interpolation circuit 2 consists of a latch circuit 3 latching a present value, a discrimination circuit 4 comparing the content of the latch circuit 3 with an object value (control data being an input of the interpolation circuit 2) and discriminating the quantity of an object with respect to the present value, and an adder circuit 5 making the present value close to the object (control data) and adding the result to the content of the latch circuit 3 based on the result of discrimination of the discrimination circuit 4. When the control data is rapidly changed, the change is traced gradually. As a result, a voice waveform being one input of a multiplier 1 is changed continuously regardless of a rapid change in the control data. Thus, the load of the software handling the modulation control system is relieved.

Description

[Detailed Description of the Invention] [Industrial Application Field] This invention relates to a sound chamber processing device. [Conventional technology] In general, a sound chamber processing device must perform various types of audio modulation processing. Therefore, the sound chamber processing device consists of an audio signal system that directly handles audio signals, and a modulation control system that controls the modulation elements of the audio signal handled by the audio signal system. [Problems to be Solved by the Invention] However, in conventional sound field processing devices, the burden on the software that handles the modulation control system is extremely heavy.
There were problems such as the overall construction was large-scale and extremely expensive. The purpose of this invention is to provide a sound field processing device that can solve the problems of the conventional devices mentioned above and reduce the burden on software that handles the modulation control system. [Means for Solving the Problems] In order to achieve the above object, the present invention includes various processing means for audio modulation. [Operation] By adopting the above-mentioned means, this invention reduces the burden on the software that handles the modulation control system. [Example] Hereinafter, an example of the present invention shown in the drawings will be described. <First Embodiment> FIG. 1 shows a first embodiment of the present invention focusing on the function as an arithmetic device. 1 is a multiplier, and an input waveform is applied to one input of the multiplier 1. , the control data of the input waveform is input to the other input. Reference numeral 2 denotes an intervolation circuit provided at the other input of the multiplier 1, and the intervolation circuit 2 is configured to gradually follow the change when the control data changes suddenly. It has become. FIG. 2 shows an example of the interboration circuit 2,
3 is a holding circuit that holds the current value, and 4 is a holding circuit that compares the contents of the holding circuit 3 with the target value (i.e., control data that is input to the interboration circuit 2), and calculates the target value (control data) with respect to the current value. A discrimination circuit 5 determines the size of the content of the holding circuit 3 based on the discrimination result of the discrimination circuit 4.
This is an adder circuit that adds a predetermined unit amount to bring the current value closer to the target value (control data) and inputs it again to the holding circuit 3, and the output of the adder circuit 5 becomes the output of the interboration circuit 2. That is, when the determination circuit 4 determines that the target value (control data) is larger than the current value, the addition circuit 5 outputs a new current value obtained by adding a positive unit l to the contents of the holding circuit 3. .Furthermore, when the discrimination circuit 4 discriminates that the target value (control data) is smaller than the current value, the addition circuit 5 outputs a new current value obtained by adding a negative unit amount to the contents of the holding circuit 3. Further, the discrimination circuit 4 determines the current value and target value (control data).
When determining that these are the same, the adder circuit 5 adds zero to the contents of the holding circuit 3 and outputs the result. Next, we will explain the effects of the above. Suppose that, for example, a voice waveform is input to one input of the multiplier 1, f/IIa4 data of the voice waveform is input to the other input, and the control data suddenly increases. In this case, first, the discrimination circuit 4 determines that the target value (
(control data after change) is large. Therefore, the addition circuit 5 adds a plus unit I to the content of the holding circuit 3.
Adds and outputs the new current value. This output is input to the multiplier 1 as the output of the interpolation circuit 2, and is also input to the holding circuit 3, where the current value is rewritten. Next, the discrimination circuit 4
If the target value (control data after change) is still larger than the rewritten new current value (control data) of the holding circuit 3, it is determined. Therefore, the addition circuit 5 adds the content of the holding circuit 3 The unit quantity of is added again to output a new current value. This output is input again to the multiplier 1 as the output of the intervolation circuit 2, and is also input to the holding circuit 3 to rewrite the current value again. Similarly, as long as the target value (control data after change) is larger than the rewritten new current value (control data) of the holding circuit 3, the addition circuit 5 adds a positive unit to the contents of the holding circuit 3. The amounts are added as many times as necessary and then input to the multiplier 1 as the output of the interpolation circuit 2.Next, for example, an audio waveform is input to one input of the multiplier 1, and the other input is input to the multiplier 1. , the control data of the audio waveform has been input, and the control data has suddenly become smaller. In this case, first, the discrimination circuit 4 selects the previous control data (currently target value (
(control data after change) is small. Therefore, the adder circuit 5 adds a negative unit amount to the contents of the holding circuit 3 and outputs a new current value. This output is input to the multiplier 1 as the output of the intervolation circuit 2, and is also input to the holding circuit 3, where the current value is rewritten. Next, the discrimination circuit 4
If the target value (control data after change) is still smaller than the new current value (control data) that has been rewritten in the holding circuit 3, it is determined. Therefore, the adder circuit 5 again adds a negative unit quantity to the contents of the holding circuit 3 and outputs a new current value. This output is input again to the multiplier 1 as the output of the intervolation circuit 2, and is also input to the holding circuit 3, where the current value is rewritten. Similarly, as long as the target value (control data after change) is smaller than the new current value (control data) of the holding circuit 3, the addition circuit 5 adds a negative unit amount to the contents of the holding circuit 3. It is added as many times as necessary and then input to the multiplier 1 as the output of the intervolation circuit 2. As a result, the audio waveform that is one input of the multiplier 1 remains constant despite sudden changes in the control data. First, due to the function of the intervolation circuit 2, the control data changes continuously in accordance with the slowly changing control data. l) When controlling the volume, the control CPU only needs to directly write the target value. 2) The output of the product-sum calculator can be input to the oscillation frequency control input of the low-frequency oscillator. Also, the maximum positive value can be selected for the multiplicand input of the product-sum calculator. Therefore, in combination with the function I), the frequency of the modulation low frequency signal can be changed continuously. 3) A low frequency signal for modulation can be selected as the input of the product-sum calculator. Therefore, in combination with the function l), the amplitude of the modulation low frequency signal can be changed continuously. 4) The output of the interboration circuit 2 can be forced to O without rewriting the target value input itself. Therefore, muting processing, which is important in audio modulation processing, becomes easier. 5) By providing a plurality of holding registers in the holding circuit 3 in the interboration circuit 2, simultaneous changes can be handled by the number of holding registers. 6) As described above, all modulation elements necessary for audio modulation processing can be continuously updated by interborating control data and widening the selection range of inputs and outputs to the product-sum calculator. Can be done. In the first embodiment, the multiplier 1 is used as an example, but any suitable arithmetic unit may be used instead. Further, in the first embodiment, the interboration circuit 2 is illustrated as the circuit shown in FIG. 2, but the present invention is not limited to this. In the audio modulation process, the arithmetic device of the first embodiment has the following functions:
Even if the target value of the control data of the input modulation element has no continuity with the current value, the modulation element can be updated continuously from the current value to the target value. By simply writing target values directly, various audio modulation processes can be performed smoothly and automatically, and as a result, it is extremely suitable for application to digital signal processing devices and other sound field processing devices. ．． <Second Embodiment> Fig. 3 shows a second embodiment of the present invention focusing on the function as a peak hold circuit, in which 1 is an absolute value circuit that processes an input waveform by absolute value, and 2 is a waveform subjected to absolute value processing. 3 is the peak value holding register, 4 is the input register that compares the contents of input register 2 with the contents of peak value holding register 3, and the contents of input register 2 are greater than the contents of peak value holding register 3. A comparison circuit 5 transfers the contents of the input register 2 to the peak value holding register 3 when the contents of the peak value holding register 3 are read from the outside.
The peak value holding register 3 is reset each time d.

When the waveform input to the input register 2 has a sampling period, the comparison circuit 4 performs a comparison process to compare the contents of the input register 2 and the contents of the peak value holding register 3, and performs a comparison process to compare the contents of the input register 2 with the peak value. Holding register 3
, the transfer process of transferring the contents of the input register 2 to the peak value holding register 3 is performed as follows.
This is done at least once in each sampling period. Next, the operation of the above will be explained in the case where a waveform having a sampling period and peak value as shown by the broken line in FIG. 4 is input. First, when the first sampling waveform is input to the input register 2, the comparator circuit 4 compares its peak value with the contents of the peak value holding register 3, but the contents of the peak value holding register 3 are the initial value O Therefore, the peak value of the first sampling is transferred as is to the peak value holding register 3, and as a result, the contents of the peak value holding register 3 become the peak value of the first sampling. Next, when the second sampling waveform is input to the input register 2, the comparator circuit 4 compares its peak value with the contents of the peak value holding register 3, Greater than the wave height value of the sampling point 2
The peak value of the second sampling is transferred to the peak value holding register 3, so that the content of the peak value holding register 3 becomes the peak value of the second sampling. Similarly, as long as the peak value of the input waveform increases with each sampling period, each peak value is sequentially transferred and becomes the contents of the peak value holding register 3. Furthermore, when the 8th sampling waveform is input to the input register 2, the comparator circuit 4 compares its peak value with the contents of the peak value holding register 3. In this case, the peak value of the input waveform is Since the peak value of the 8th sampling is smaller than the peak value of the 7th sampling, which is the content of the value holding register 3, the peak value of the 8th sampling is not transferred to the peak value holding register 3, and as a result, the content of the peak value holding register 3 is The peak value is maintained as it is. Next, when the ninth sampling waveform is input to the input register 2, the comparator circuit 4 compares its peak value with the contents of the peak value holding register 3, and compares the waveform with the contents of the peak value holding register 3. 9 smaller than the wave height value of the sampling point
The peak value of the 7th sampling is not transferred to the peak value holding register 3, so that the contents of the peak value holding register 3 are held as the peak value of the 7th sampling. Similarly, as long as the peak value of the input waveform becomes smaller with each sampling period, each peak value is not transferred at all.
The contents of the peak value holding register 3 are held at the maximum peak value of the 7th sampling up to that point. Therefore, the contents of the peak value holding register 3 are the peak values of the input waveform for each sampling up to that point.
It will always be held at the maximum value. Then, when the contents of the peak value holding register 3 are read out from the outside (for example, a control CPU), the reset circuit 5 is activated at the same time to reset the contents of the peak value holding register 3 to O. Therefore, among the input data from the previous readout to the current readout, the maximum value is always held in the peak value holding register 3, and is read out in response to external readout. 3rd Embodiment> FIG. 5 shows a third embodiment of the present invention which focuses on the function as a peak hold circuit, similar to the second embodiment, and 11 is an absolute value circuit that processes a plurality of input waveforms into absolute values. , 12 is an input register into which the waveform subjected to absolute value processing is input, 13 is a peak value holding register, and 14 is a comparison between the contents of the input register 12 and the contents of the peak value holding register 13, and the contents of the input register 12 are A comparison circuit 15 transfers the contents of the input register 12 to the peak value holding register 13 when the contents are larger than the contents of the peak value holding register 13, and 15 is a peak value holding register when the contents of the peak value holding register 13 are read from the outside. This is a reset circuit that resets 13. When the plurality of waveforms input to the input register 12 each have a sampling period, the comparison circuit 14
Comparison processing that compares the contents of the input register 12 and the contents of the peak value holding register 13, and when the contents of the input register 12 are larger than the contents of the peak value holding register 13, the contents of the input register 12 are transferred to the peak value holding register 13. The transfer processing is performed at least once in each sampling period for each of the plurality of waveforms. Next, the operation of the above will be explained for the case where three types of waveforms having sampling periods and peak values as shown in FIGS. 6A to 6C are input. First, when the peak values of the first sampling of waveforms a to C are input to the input register 12, the comparison circuit 14 first performs the following steps.
The peak value of the first sampling of waveform a is compared with the contents of the peak value holding register 13, and since the content of the peak value holding register 13 is the initial value O, the peak value of the first sampling of waveform a is unchanged. Transfer to peak value holding register 13. The comparison circuit 14 then compares the peak value of the first sampling of the waveform b with the contents of the peak value holding register 13, and compares the peak value of the waveform a which is the contents of the peak value holding register 13.
The peak value of the first sampling of waveform b, which is larger than the peak value of the sampling, is transferred to the peak value holding register 13. The comparator circuit 14 then compares the peak value of the first sampling of the waveform C with the contents of the peak value holding register 13, and determines that the peak value of the first sampling and the first ring of the waveform C is the peak value of the peak value holding register 13. Since the peak value of the first sampling of waveform C is smaller than the peak value of the first sampling of waveform B, which is the content of
As a result, the contents of the peak value holding register 13 become waveform b.
The peak value of the first sampling is maintained. The order of this comparison processing and transfer processing by the comparison circuit 14 is as follows:
Even if the processing is performed not only in the order of waveforms a, b, and c, but also in the order in which they occur, the same result will be obtained when the processing of the first sampling is completed. Next, when the second sampling of the waveform a%C is input to the input register 12, the comparator circuit 14 operates in the same way as the first sampling, and the second sampling of the waveform a to C is input to the input register 12. The high value is sequentially compared with the contents of the peak value holding register 13, and the peak value of the second sampling which is higher than the peak value of the first sampling of waveform b, which is the contents of the peak value holding register 13, is stored in the peak value holding register 13. As a result, the contents of the peak value holding register 13 become the peak value of the second sampling of waveform b. Similarly, input waveform a % C
An arbitrary peak value of
As long as the peak values of the input waveforms a to C become larger, the peak values are sequentially transferred and become the contents of the peak value holding register 13, and as long as the arbitrary peak values of the input waveforms a to C all become smaller with each sampling period. , the peak value is not transferred at all, and the contents of the peak value holding register 13 are held at the maximum peak value up to that point. Therefore, the contents of the peak value holding register 13 are as follows:
As shown by the solid line in Figure d, the peak value of the input waveforms a to C is always held at the maximum value for each sampling up to that point. Then, when the contents of the peak value holding register 13 are read from the outside (for example, a control CPU), the reset circuit 15 is activated at the same time.
Reset the contents of the peak value holding register 13 to O.
Therefore, among the input data from the previous readout to the current readout, the maximum value is always held in the peak value holding register 13, and is read out in response to external readout. Although the absolute value circuits 1 and 11 are provided in the second and third embodiments, these may be omitted depending on the case. In addition, in the second and third embodiments described above, input registers 2 and 12
Although the peak value holding registers 3 and 13 are illustrated, for example, an appropriate input circuit and peak value holding circuit may be used instead. Further, in the second and third embodiments described above, the case where there is one input waveform (FIGS. 3 and 4) and the case where there are three input waveforms (FIGS. 5 and 6) have been explained, but the present invention is not limited to this. The peak hold circuits of the second and third embodiments described above can always reliably hold the peak value even if the duration of each peak value is extremely short in audio modulation processing, and can also Of the input data until the readout, the maximum value is always held in the peak value holding circuit and can be read out in response to external readout. It is extremely suitable for application to 4th Embodiment> FIG. 7 shows a fourth embodiment of the present invention focusing on the function as a sample-and-hold circuit. 2 is a clipping circuit that outputs a predetermined maximum value of the input waveform when the detection circuit 1 is in a detection operation, and 3 is a clipping circuit that outputs a predetermined maximum value of the input waveform when the detection circuit 1 is in a non-detection operation. A reset circuit resets circuit 2, and 4 is an arithmetic circuit. The arithmetic circuit 4 is set in advance so that when the maximum value of the peak value of the input waveform is less than the predetermined boundary, the peak value exceeds the predetermined boundary or coincides with the predetermined boundary. The value of the constant register is added. Next, we will explain the effects of the above. First, the 8th
As shown in Figure a, if there is a triangular wave whose maximum value is located between the O level and the maximum dynamic range, the arithmetic circuit 4 determines whether the positive maximum value of the triangular wave matches the maximum dynamic range or Add the value of a preset constant register so that it exceeds that value. Therefore, the waveform input to the detection circuit 1 via the arithmetic circuit 4 becomes as shown in FIG. 8b. Then, the detection circuit 1 detects that the peak value of the input waveform input via the arithmetic circuit 4 coincides with at least a predetermined boundary, and switches to a detection operation. In response to this, the clip circuit 2 outputs the predetermined maximum value of the input waveform, that is, the positive maximum value of the triangular wave that matches the maximum dynamic range, during the detection operation of the detection circuit 1. During non-detection operation, the reset circuit 3 resets the clip circuit 2 and sets its output to O level. Therefore, the input waveform becomes as shown in FIG. 8C after the clip/reset process. Therefore, from the triangular wave shown in FIG. 8a, a pulse waveform as shown in FIG. Voice input in Figure 8a
Each time the triangle wave shown in
This means that it can be held. Note that in the fourth embodiment, the audio input is sampled and held each time the triangular wave reaches the maximum positive value, but the invention is not limited to this; for example, when the triangular wave reaches the maximum negative value. The audio input may be sampled and held each time the triangular wave reaches its maximum positive value and the maximum negative value, respectively. Also,
In the fourth embodiment, the arithmetic circuit 4 is configured to add the values of the constant register set in advance so that the maximum value of the triangular wave matches or exceeds the maximum dynamic range. The maximum value of the triangular wave can be made to match or exceed the maximum dynamic range by appropriate means, and the maximum value of the triangular wave can be set to the maximum dynamic range from the beginning. If it matches or exceeds the range, the arithmetic circuit 4 can be omitted and the triangular wave can be used as it is as the input waveform of the detection circuit 1. Further, in the fourth embodiment, a triangular wave is used as an example of the input waveform, but the present invention is not limited to this, and any appropriate waveform can be used as the input waveform. 4th above
The sample-and-hold circuit of the embodiment can obtain the sample-and-hold function by using the clip function. Therefore, like a conventional sample-and-hold circuit, it requires a dedicated circuit including a dedicated register, and a dedicated circuit including a dedicated register. There is no need for any control command signal to give a dedicated command, and therefore the sample-and-hold function can be realized simply and easily.As a result, it can be applied to digital signal processing equipment and other sound field processing equipment. This is a very suitable conflict. 5th Practical Example> FIG. 9 shows a fifth embodiment of the present invention focusing on the function as a gate signal generation circuit, in which 1 is a digital integration circuit that integrates an impulse signal, and 2 is an output of the digital integration circuit 1. 3 is a detection circuit that detects when the output of the shift-up circuit 2 exceeds a predetermined range; 4 is the output of the shift-up circuit 2 during the detection operation of the detection circuit 3; A clip circuit 5 outputs a predetermined maximum value of . 5 is a reset circuit that resets the J clip circuit 4 during non-detection operation of the detection circuit 3. Next, we will explain the effects of the above. First, the first
When an impulse signal as shown in Figure 0a is applied,
The digital integration circuit 1 integrates this to obtain an output waveform as shown in Figure 10b. Next, the shift-up circuit 2 adds the necessary DC component L so that a predetermined width portion of the output of the digital integration circuit 1 exceeds a predetermined pot size value, as shown in FIG. 10C. Obtain an output waveform like this. Then, the detection circuit 3 detects that the output of the shift-up circuit 2 exceeds a predetermined range, and switches to a detection operation. In response to this, the clip circuit 4 outputs the predetermined maximum value of the output of the shift-up circuit 2 during the detection operation of the detection circuit 3, while during the non-detection operation of the detection circuit 3,
The reset circuit 5 resets the clip circuit 4 and sets its output to O level. Therefore, a gate signal having the required time width T as shown in FIG. 10d is obtained. Such a gate signal may, for example, cause a reverb or echo sound as shown in FIG. 11b obtained from an original sound as shown in FIG. 11a to pass for a predetermined duration as shown in FIG. 11C. It can be used as a so-called reverb gate. Furthermore, the gate signal can be used to obtain an output waveform from which noise is removed, as shown in FIG. 12b, from the original sound as shown in FIG. It can also be used as a noise gate. In the first place, when an impulse signal as shown in FIG. 10a of the gate signal generation circuit is obtained from an audio input waveform as shown in FIG. If the input signal is input and the detection circuit 3 is instantaneously switched to the detection operation, an impulse signal as shown in FIG. Furthermore, instead of converting the audio input waveform as shown in FIG. 13 into an impulse signal as shown in FIG. 10a and inputting it to the digital integration circuit 1, the audio input waveform as shown in FIG. If , is directly input to the digital integration circuit 1 as it is, almost the same result will be obtained. In the fifth embodiment, examples of the use of the gate signal of the gate signal generation circuit include use as a reverb gate,
Although the use as a noise gate is illustrated, the present invention is not limited to this and can be used for any appropriate purpose. The gate signal generation circuit of the fifth example 81 can obtain a gate signal by using the clip function, and
Unlike conventional gate signal generation circuits, no dedicated software or hardware is required;
The structure is simple and easy to handle, and the absolute value of the input signal can be used as is to realize a gate signal generation circuit.As a result, it can be applied to digital signal processing equipment and other sound field processing equipment. Therefore, it is extremely suitable. <Sixth Embodiment> FIG. 14 shows a sixth embodiment of the present invention focusing on the function as a sine wave generator. 1 is a triangular wave generating circuit, 2 is a holding circuit, and 3 is an output of the triangular wave generating circuit 1. 4 is an initialization circuit that initializes the holding circuit 2 by inputting zero when the triangular wave output from the triangular wave generation circuit 1 is at its maximum value; conversion circuit 4
After initialization, the output of the adder circuit 3 is held and a sine wave is generated. Next, the operation of the above will be explained with reference to FIG. Assume that the triangular wave generating circuit 1 is outputting a triangular wave as shown in FIG. 15a. In this case, first, when the output triangular wave of the triangular wave generating circuit 1 reaches the maximum positive or negative value, the initializing circuit 4 inputs O to the holding circuit 2 to initialize it. Then, the addition circuit 3 starts addition according to a predetermined sampling period. That is,
For example, if the addition is started from the maximum positive value of the triangular wave, the output level of the triangular wave generating circuit 1 at the first sampling is the maximum positive value M, while the output of the holding circuit 2 is the initial value O. The output of the adder circuit 3 becomes M+O''C''M, and this value is held in the holding circuit 2 and output from the holding circuit 2. Next, the output level of the triangular wave generating circuit 1 at the second sampling is M-a, which is smaller than M by a unit amount a, and on the other hand,
Since the output of the holding circuit 2 is M, the output of the adding circuit 3 is (M-a)+M, which is 2M-a, and this value, which is smaller by a than twice M, is held in the holding circuit 2, and Output from circuit 2. Next, the output level of the triangular wave generation circuit 1 at the third sampling is M-2a, which is smaller than M-a by a unit amount a,
On the other hand, since the output of the holding circuit 2 is 2M-a, the output of the addition circuit 3 is (M-2a)+(2M-a), which is 3M-3a.
This value, which is 3a smaller than 3 times M, is held in the holding circuit 2 and output from the holding circuit 2.
Next, the output level of the triangular wave generating circuit 1 at the fourth sampling is M-3a, which is smaller than M-2a by a unit amount a, and on the other hand, the output of the holding circuit 2 is 3M-3a, so the output level of the adding circuit 3 is is〈M-3a) + (3M-
3a) becomes 4M-6a, and this value, which is 6a smaller than four times M, is held in the holding circuit 2 and output from the holding circuit 2. Thereafter, in the same manner, the output of the holding circuit 2 continues to rise at a gradually decreasing rate until the output level of the triangular wave generating circuit 1 reaches O, as shown in FIG. 15b. When the output level of the triangular wave generation circuit 1 becomes O, the output of the holding circuit 2 becomes the maximum positive value N. The output level of the triangular wave generating circuit 1 at the first sampling counting from now is −a, which is smaller than O by the unit amount a, and on the other hand, the output of the holding circuit 2 is the maximum positive value N, so the output level of the adding circuit 3 is -a+N becomes N-a, and this value is held in the holding circuit 2 and output from the holding circuit 2. Next, the output level of the triangular wave generating circuit 1 at the second sampling is -2a, which is smaller than -a by the unit amount a, while the holding circuit 2
Since the output of is N-a, the output of adder circuit 3 is -2a
+ (N-a) becomes N-3a, and this value is the holding circuit 2
is held and output from the holding circuit 2. Next, the output level of the triangular wave generation circuit 1 at the third sampling is -3a, which is smaller than -2a by a unit amount a, and on the other hand, the output level of the holding circuit 2 is N-3a, so the adder circuit 3
The output of -3a+(N-3a) becomes N-6a, and this value is held in the holding circuit 2 and output from the holding circuit 2. Similarly, until the output level of the triangular wave generation circuit 1 reaches the negative maximum value, the output of the holding circuit 2 is as follows.
As shown in Figure 15b, the rate of decline continues to increase gradually. When the output level of the triangular wave generation circuit 1 reaches the negative maximum value 1M, the output of the holding circuit 2 becomes O. That is, the output level of the triangular wave generation circuit 1 at the first sampling is the negative maximum value 1M, while the output of the holding circuit 2 is O, so the output of the addition circuit 3 is -M+O, which is 1M. This value is held in the holding circuit 2 and output from the holding circuit 2. Next, the output level of the triangular wave generation circuit 1 at the second sampling is 1M+a, which is greater than 1M by a unit amount a, and on the other hand, the output of the holding circuit 2 is 1M, so the output of the addition circuit 3 is (- M+a)+(-M) becomes -2M+a, and this value, which is larger by a than twice 1M, is held in the holding circuit 2 and output from the holding circuit 2. Next, the output level of the triangular wave generation circuit 1 at the third sampling is -M+2a greater than 1M+a by a unit amount a.
On the other hand, since the output of the holding circuit 2 is -2M+a, the output of the adding circuit 3 is (-M+2a)+ (-2M
+a) becomes -3M+3a, and this value, which is 3a larger than 3 times 1M, is held in the holding circuit 2 and output from the holding circuit 2. Next, the output level of the triangular wave generation circuit 1 at the fourth sampling is -M+3a, which is larger by a unit amount a than -M+2a, and on the other hand, the output of the holding circuit 2 is -3M+3a, so the output level of the adder circuit 3 is (1) M+3a)+ (-3M
+3a) becomes -4M+6a, and this value, which is 6a larger than 4 times 1M, is held in the holding circuit 2 and output from the holding circuit 2. Thereafter, in the same manner, the output of the holding circuit 2 continues to fall at a gradually decreasing rate until the output level of the triangular wave generating circuit 1 reaches 0, as shown in FIG. 15b. When the output level of the triangular wave generation circuit 1 becomes 0, the output of the holding circuit 2 becomes the maximum negative value -N. Counting from now on, 1
The output level of the triangular wave generation circuit 1 at the sampling point is O
On the other hand, the output of the holding circuit 2 is the negative maximum value 1N, so the output of the adding circuit 3 is a+(1N), which is 1N+a, and this value is the value of the holding circuit 2. is held and output from the holding circuit 2. Next, the output level of the triangular wave generating circuit 1 at the second sampling is 2a, which is greater than a by the unit amount a, and on the other hand, the output of the holding circuit 2 is -N+a, so the output level of the adding circuit 3 is 2a+ (-N+a ) becomes -N+3a, and this value is held in the holding circuit 2 and output from the holding circuit 2. Next, the third sampling triangular wave generation circuit 1
The output level of is 3a, which is greater than 2a by a unit amount a, and on the other hand, the output of holding circuit 2 is -N+3a, so the output of adder circuit 3 is 3a+ (-N+3a), which is -N+6a.
This value is held in the holding circuit 2 and output from the holding circuit 2. Thereafter, in the same manner, the output of the holding circuit 2 continues to rise at a gradually increasing rate, as shown in FIG. 15b, until the output level of the triangular wave generating circuit 1 reaches its maximum positive value. When the output level of triangular wave generation circuit 1 reaches the maximum positive value,
The output of holding circuit 2 becomes O. Therefore, when the triangular wave generating circuit 1 generates a triangular wave as shown in FIG. 15a, the holding circuit 2 generates a sine wave (strictly speaking, a pseudo sine wave) as shown in FIG. 15b. ．． In the sixth embodiment, the initialization circuit 4 is provided separately from the triangular wave generation circuit 1 and the holding circuit 2, but the present invention is not limited to this. The sine wave generator of the sixth embodiment does not require a ROM that records each level value for each sampling period of the sine wave, unlike conventional ones.
There is no need for the CPU to read out the ROM at every sampling period, so it is possible to generate a sine wave extremely easily with a simple configuration, and as a result, it can be applied to digital signal processing devices and other sound field processing devices. Therefore, it is extremely suitable. Seventh Embodiment> FIG. 16 shows a seventh embodiment of the present invention which focuses on the function as a sine wave generator, similar to the sixth embodiment. It is an inverting circuit that folds the output back at its intermediate level, and since it folds back in the positive direction, it is composed of an absolute value circuit. In addition, 3 adds a constant to the output of the inverting circuit 2, and the inverting circuit 2 corresponds to the maximum value and minimum value of the triangular wave generating circuit I.
This is an arithmetic circuit that makes the minimum value of the output more than half of the maximum value. That is, the arithmetic circuit 3 is a constant circuit 4 that outputs a constant A.
and an auxiliary circuit 5 that outputs a number B (-0.5A≦Boo), which is a number equal to or less than 172 of the output A of the constant circuit 4 with a negative sign added.
The output of the inverting circuit (absolute value circuit) 2 is multiplied by the output B of the auxiliary circuit 5, and the level difference between the maximum value and the minimum value of the output of the inverting circuit (absolute value circuit) 2 is calculated by the constant A. A multiplier circuit 6 that increases the output by half or less, and an adder circuit that adds the output of the multiplier circuit 6 and the output A of the constant circuit 4 to increase the minimum value of the output of the inverting circuit (absolute value circuit) 2 to more than half of the maximum value. Furthermore, 8 is a multiplication circuit that multiplies the output of the triangular wave generation circuit 1 and the output of the arithmetic circuit 3.Next, the operation of the above circuit will be explained with reference to FIG. Assume that the triangular wave generating circuit 1 is outputting a triangular wave as shown in FIG. Since the waveform turns back in the positive direction at the level, the waveform becomes as shown in FIG.
Since the output of the absolute value circuit (absolute value circuit) 2 is multiplied by the output B of the auxiliary circuit 5 (for example, B=-0.5A>), the level difference between the maximum and minimum values of the output of the inverting circuit (absolute value circuit) 2 is , becomes exactly half of the constant A. At the same time, since the adder circuit 7 adds the output of the multiplier circuit 6 and the output A of the constant circuit 4, the minimum value of the output of the inverting circuit (absolute value circuit) 2 is the maximum The value becomes exactly half, resulting in a waveform as shown in FIG.
7a) is multiplied by the output of the arithmetic circuit 3, that is, the output of the adder circuit 7 (FIG. 17C).

That is, for example, when the triangular wave is at the origin O, the output level of the triangular wave generating circuit 1 is 0, and on the other hand, the output of the arithmetic circuit 3 is the maximum value A, so the output of the multiplier circuit 8 is O.
XA becomes O. Next, when the output level of the triangular wave generation circuit 1 is 0.2M, which corresponds to the maximum value M of 175,
The output of the arithmetic circuit 3 is from the maximum value A to the maximum value A and the minimum value 0.
．． 5A is 0.9A, which is 1/5 smaller than the difference of 0.5A, so the output of the multiplier circuit 8 is 0.9A. 2Mx0.9Ar0
．． It will be 18 MA. Next, the output level of the triangular wave generating circuit 1 is 2, which is the maximum value M.
When it is 0.4M corresponding to 75, the output of the arithmetic circuit 3 is from the maximum value A, and the difference in ρ between the maximum value A and the minimum value 0.5A is 0.
Since it is 0.8A, which is 2/5 of 5A, the output of the multiplier circuit 8 is 0.4Mx0.8Ar0.32MA. Next, the output level of the triangular wave generation circuit 1 is 3, which is the maximum value M.
/5, the output of the arithmetic circuit 3 is the maximum value A, and the difference between the maximum value A and the minimum value 0.5A is 0.
Since it is 0.7A, which is 3/5 of 5A, the output of the multiplier circuit 8 is 0.6MX0.7A, which is 0.42MA.

Furthermore, the output level of the triangular wave generating circuit 1 is 4, which is the maximum value M.
/5, the output of the arithmetic circuit 3 is determined by the maximum value A, and the difference between the maximum value A and the minimum value 0.5A is 0.5A.
Since it is 0.6A, which is 4/5 of 5A, the output of the multiplier circuit 8 is 0.8MX0.6A, which is 0.48MA. Then, when the output level of the triangular wave generation circuit 1 reaches the maximum value M, the output of the arithmetic circuit 3 becomes the minimum value 0.5A.
The output of the multiplier circuit 8 is MXO. La A becomes 0.5 MA. Therefore, during this period, the output of the multiplier circuit 8 is
As shown in , the rate of increase continues to increase while gradually decreasing. Also, the output level of the triangular wave generation circuit 1 changes from the maximum value M to O.
During this period, the output of the multiplier circuit 8 is as shown in FIG.
It continues to fall while the rate of decline gradually increases. On the other hand, the output level of the triangular wave generation circuit 1 is 1 of the minimum value 1M.
/5, the output of the arithmetic circuit 3 is the maximum value A, so the difference between the maximum value A and the minimum value 0.5A is 0.
．． Since 0.9A is smaller by 1/5 of 5A, the output of the multiplier circuit 8 is -0.2MX0.9A, which is -0.18MA. Next, when the output level of the triangular wave generation circuit 1 is -0.4M, which corresponds to 2/5 of the minimum value 1M, the output of the arithmetic circuit 3 reaches the maximum fit! From A, maximum value A and minimum value 0
, 5A is 0.8A, which is smaller by 2/5 of the difference of 0.5A, so the output of the multiplier circuit 8 is -0.4MXO. At 8A-
It becomes 0.32 MA. Next, when the output level of the triangular wave generation circuit 1 is 0.6M, which corresponds to 3/5 of the minimum value M, the output of the arithmetic circuit 3 is calculated from the maximum value A. 0.7A, which is 3/5 smaller than the difference of 0.5A
Therefore, the output of the multiplication circuit 8 is 10. 6MX0.7A
Therefore, it becomes -0.42MA. Furthermore, when the output level of the triangular wave generation circuit 1 is -0.8M, which corresponds to the minimum value M of 475, the output level of the arithmetic circuit 3 is lower than the maximum value A.
0, which is smaller by 4/5 of the difference 0.5A between and the minimum value 0.5A
．． 6A, the output of the multiplier circuit 8 is -0.8MX0
．． At 6A, it becomes -0.48MA. When the output level of the triangular wave generation circuit 1 reaches the minimum value 1M, the output of the arithmetic circuit 3 becomes the minimum value 0.5A, so the output of the multiplier circuit 8 becomes 1M x 0.5A, which is -0.5MA. Become. Therefore, during this period, the output of the multiplier circuit 8 is
As shown in , the rate of decline continues to decrease gradually. Also, when the output level of the triangular wave generation circuit 1 increases from the minimum value 1M to 0, the above process is reversed, so
Meanwhile, the output of the multiplier circuit 8 continues to rise at a gradually increasing rate, as shown in FIG. 17d. Therefore, when the triangular wave generator circuit 1 generates a triangular wave as shown in FIG. In the seventh embodiment, the inverting circuit 2 is constituted by an absolute value circuit, but the invention is not limited to this. In addition, in the seventh embodiment, the arithmetic circuit 3 is composed of a constant circuit 4 that outputs the constant A, and a number B that is equal to or less than 1/2 of the output A of the constant circuit 4 with a negative sign. (-0.5A≦Boo), the output of the inverting circuit (absolute value circuit) 2 and the output B of the auxiliary circuit 5 are multiplied together, and the output of the inverting circuit (absolute value circuit) 2 is The level difference between the maximum value and the minimum value is expressed as a constant A
A multiplication circuit 6 which adds the output of the multiplication circuit 6 and the output A of the constant circuit 4 to make the minimum value of the output of the inverting circuit (absolute value circuit) 2 less than half of the maximum value. Although the configuration is made up of circuit 7, it is not limited to this. The sine wave generator of the seventh embodiment can generate a sine wave by simply performing inversion, calculation, and multiplication on the output of the triangular wave generation circuit. There is no need for a ROM that records each level value for each sampling period, and there is no need for the CPU to read out the ROM for each sampling period. Therefore, a sine wave can be generated extremely easily with a simple configuration. As a result, it is extremely suitable for application to digital signal processing devices and other sound field processing devices. 8th Embodiment> Fig. 18 shows an eighth embodiment of the present invention, which focuses on the function of the A/D converter as a correction device. A zero input circuit that switches from the audio input and inputs zero level direct current,
3 indicates that when the A/D converter 1 is receiving zero level direct current from the zero input circuit 2, the A/D converter 1
4 is a constant circuit that generates a constant 1K corresponding to the opposite phase of the DC component K detected by the detection circuit 3; 5 is a zero input During normal audio input when circuit 2 does not input zero-level DC, the output of A/D converter 1 and the output of constant circuit 4 are added to calculate the DC component K that should appear at the output of the A/D converter. This is an addition circuit that cancels and eliminates by a constant 1K. Next, we will explain the effects of the above.
First, when there is no normal audio input or when there is no problem even if the audio input to the A/D converter 1 is momentarily cut off, the zero input circuit 2 switches from the normal audio input. Input zero level DC to A/D converter 1. At this time, if the A/D converter 1 itself generates a DC component K having a substantial level, this DC component K will appear at the output of the A/D converter 1. Then, the detection circuit 3 detects the DC component K appearing at the output of the A/D converter 1, and upon receiving this, the constant circuit 4
generates a constant 1K corresponding to the opposite phase of the DC component K detected by the 5 detection circuit 3. After the above operations are completed,
When the zero input circuit 2 switches from zero input to normal audio input, the input audio signal is A/D converted by the A/D converter 1 and then output, but it is included in the output. The DC component K generated by the A/D converter 1 itself is added to the constant 1K generated from the constant circuit 4 by the adding circuit 5, and is canceled out and removed. Therefore, the output of the adder circuit 5 is the output of the A/D converter 1
The DC component K is completely removed from the output of , that is, the output is only A/D conversion data in the pure sense of the input audio signal. As a result, an appropriate audio processing device (not shown) that receives A/D converted data from the A/D converter 1 via the adder circuit 5 is a pure A/D converter that does not include any DC component K generated by the A/D converter 1 itself. /D converted data can be received and required processing can be performed. In the eighth embodiment, the constant circuit 4 is replaced by the detection circuit 3.
Although the detection circuit 3 and the addition circuit 5 are provided independently, the present invention is not limited to this, and the detection circuit 3 or the addition circuit 5 may also be provided. Furthermore, in the eighth embodiment,
Although the detection circuit 3 and the addition circuit 5 are provided independently from an appropriate audio processing device (not shown) that receives A/D conversion data from the A/D converter 1, the present invention is not limited to this. Using its own function, the detection circuit 3
Alternatively, it may be configured to perform the role of the adder circuit 5. Furthermore, in the eighth embodiment, the zero input circuit 2 and the constant circuit 4 are also provided independently from the appropriate audio processing device (not shown) that receives A/D conversion data from the A/D converter 1. However, the present invention is not limited to this, and the role of the zero input circuit 2 or the constant circuit 4 may be performed by using the functions of the audio processing device itself or devices originally used in combination with the audio processing device. good. The A/D converter correction device of the eighth embodiment is an A/D converter correction device according to the eighth embodiment.
The DC component that should appear in the output of the D converter can be canceled out and removed by a constant corresponding to the opposite phase of the DC component detected at zero input. By removing the DC component that appears in the output of the A/D converter without performing any It is extremely suitable for application to digital signal processing devices such as digital filters, as well as other sound chamber processing devices. <Ninth Actual Tumor Example> Figure 20 shows this device focusing on its function as a memory rewriting circuit. A ninth embodiment of the invention is shown, in which 1 is a control CPU (central processing unit), 2 is a program memory, 3 is an arithmetic unit that operates according to the contents of the program memory 2, and 4 holds required values of the arithmetic unit 3. memory for calculation, 5 is C for control.
When the contents of the program memory 2 are rewritten by the PUI, this clear circuit simultaneously clears the contents of the calculation memory 4 according to instructions from the control CPUI. Program memory 2 is RAM (random access memory) and is rewritable, so by rewriting the contents of program memory 2, you can execute multiple different processes without changing the hardware. ing. In addition, the calculation memory 4 is connected to the calculation unit 3.
It is possible to temporarily hold the value in the middle of an operation, or to hold the value for a long time (delay). Further, when the clearing of the calculation memory 4 is completed, the clear circuit 5 is configured to notify the control CPU of the same. Next, we will explain the effects of the above. When rewriting the contents of the program memory 2, the contents of the calculation memory 4 are the values held by the previous program, and become noise irrelevant to the new program. The rewriting of the program memory 2 and the clearing of the calculation memory 4 are performed in the following manner. That is, as shown in FIG. 21, first, the contents of program memory 2 are output (volume) as they are in software A before the update.
Gradually lower. Next, when the output becomes 0, the content of the program memory 2 is directly rewritten from A to B (new software to be updated) using the control CPU, and at the same time, the clear circuit is 5 directly clears the contents of the calculation memory 4. Next, after rewriting the program memory 2 and clearing the calculation memory 4, the output (volume) is gradually increased. Therefore, rewriting the program memory 2 and clearing the calculation memory 4 must be performed in parallel.
Furthermore, in the ninth embodiment, when the contents of the program memo υ2 are rewritten by the IIN official CPU, at the same time, the contents of the calculation memory 4 are instructed to be cleared by the instruction of the control CPU. However, the present invention is not limited to this; for example, even when the contents of the program memory 2 are rewritten by the control CPU, the contents of the calculation memory 4 may be configured so as not to clear necessary portions. Furthermore, even when the contents of the program memory 2 are not rewritten, a necessary portion of the contents of the calculation memory 4 can be cleared.

The memory rewriting circuit of the ninth embodiment described above can rewrite the program memory and clear the calculation memory at the same time, and the rewriting of the program memory is shown in FIG. 22.4. As with the conventional version, you must first rewrite the software A before the update to the software C for clearing the calculation memory, clear the contents of the calculation memory, and then rewrite the software C to the new software B that should be updated. Instead, it only needs to be done once, directly from the old software to the new software to be updated. Therefore, it does not take much time to rewrite the program memory, and the rewriting time can be used to clear the calculation memory. Therefore, it is possible to rewrite the program memory and clear the calculation memory in a short time and efficiently.As a result, it is extremely suitable for application to digital signal processing devices and other sound chamber processing devices. It is something. [Effects of the Invention] Since the present invention is structured as described above, it is possible to reduce the burden on the software that handles the modulation control system, thereby reducing the cost and increasing the popularity of sound chamber processing devices. It has excellent effects such as being extremely effective.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a first embodiment of the present invention, and FIG.
The figure is a block diagram showing an example of an intervolation circuit. 1... Multiplier 2... Interboration circuit 3... Holding circuit 4... Discrimination circuit 5...
Adding circuit FIG. 3 is a block diagram showing a second embodiment of the present invention, and FIG.
The figure is an explanatory diagram showing an example of the input waveform and peak hold waveform of the one shown in FIG. 3, FIG. 5 is a block diagram showing the third embodiment of the present invention, and FIG. FIG. 3 is an explanatory diagram showing an example of a hold waveform. 1... Absolute value circuit 2... Input register 3.
...Peak value holding register 4...Comparison circuit 5...Reset circuit 11
... Absolute value circuit l2 ... Input register 13.
...Peak value holding register 14...Comparison circuit 15...Reset circuit FIG. 7 is a block diagram showing a fourth embodiment of the present invention, and FIG. 8 shows an example of waveforms of each part of the one shown in FIG. This is an explanatory diagram. 1...Detection circuit 2...Clip circuit 3.
...Reset circuit 4...Arithmetic circuit FIG. 9 is a block diagram showing the fifth embodiment of the present invention, FIG. 10 is an explanatory diagram showing an example of waveforms of each part of the circuit in FIG. 9, and FIG. 11 is a gate FIG. 12 is an explanatory diagram showing an example of the use of a signal, FIG. 12 is an explanatory diagram showing another example of the use of a gate signal, and FIG. 13 is an explanatory diagram showing an example of an audio input waveform. 1... Digital integration circuit 2... Shift up circuit 3... Detection circuit 4... Clip circuit 5.
...Reset circuit FIG. 14 is a block diagram showing a sixth embodiment of the present invention, and FIG. 15 is an explanatory diagram showing an example of waveforms of each part of the circuit shown in FIG. 1...Triangular wave generation circuit 2...Holding circuit 3...
Addition circuit 4...Initialization circuit FIG. 16 is a block diagram showing a seventh embodiment of the present invention, and FIG. 17 is a block diagram showing the seventh embodiment of the invention.
It is an explanatory diagram showing an example of the waveform of each part of the figure. 1... Triangular wave generation circuit 2... Inverting circuit (absolute value circuit) 3... Arithmetic circuit 4... Constant circuit 5...
Auxiliary circuit 6 Multiplying circuit 7 Adding circuit 8 Multiplying circuit FIG.
FIG. 19 is a block diagram showing an example of a digital filter. 1... A/D converter 2... Zero input circuit 3.
...Detection circuit 4...Constant circuit 5...Addition circuit FIG. 20 is a block diagram showing the ninth embodiment of the present invention, FIG. 21 is an explanatory diagram showing rewriting of the program memory of the one in FIG. 20, FIG. 22 is an explanatory diagram showing how to rewrite the program memory of a conventional device. 1... Control CPU 2... Program memory 3... Arithmetic unit 4... Arithmetic memory 5... Clear circuit

Claims (1)

[Claims] 1. Sound field processing device equipped with various sound modulation processing means.