JPH0392062A - Facsimile equipment - Google Patents
Facsimile equipmentInfo
- Publication number
- JPH0392062A JPH0392062A JP1230130A JP23013089A JPH0392062A JP H0392062 A JPH0392062 A JP H0392062A JP 1230130 A JP1230130 A JP 1230130A JP 23013089 A JP23013089 A JP 23013089A JP H0392062 A JPH0392062 A JP H0392062A
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- signal
- personal computer
- serial
- outputs
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000006243 chemical reaction Methods 0.000 abstract description 5
- 230000006835 compression Effects 0.000 abstract 1
- 238000007906 compression Methods 0.000 abstract 1
- 230000004044 response Effects 0.000 abstract 1
- 238000010586 diagram Methods 0.000 description 2
- 230000005540 biological transmission Effects 0.000 description 1
- 238000005070 sampling Methods 0.000 description 1
Landscapes
- Facsimiles In General (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明はファクシミリ装置に関し、特にパーソナルコン
ピュータからの画データを送信するファクシミリ装置に
関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a facsimile device, and particularly to a facsimile device that transmits image data from a personal computer.
従来のファクシミリ装置は、パーソナルコンビ二一夕か
ら2 1 M H zのクロックを入力し、そのクロッ
クで画データをサンプリングしたシリアルデータをメモ
リに蓄積している.
〔発明が解決しようとする課題〕
上述した従来のファクシミリ装置は、クロックが高速の
ため応答できるメモリに制限があり、更に画データの書
き込みとリフレッシュを交互に行う必要があるため処理
時間に無理があり、回路規模が大きくなる欠点がある。A conventional facsimile machine inputs a 21 MHz clock from a personal computer, and stores serial data obtained by sampling image data using that clock in a memory. [Problems to be Solved by the Invention] The above-mentioned conventional facsimile machine has a high-speed clock, so there is a limit to the memory that can respond, and furthermore, it is necessary to alternately write and refresh image data, which leads to unreasonable processing time. However, the disadvantage is that the circuit scale becomes large.
本発明のファクシミリ装置は、パーソナルコンピュータ
から入力のディジタル画信号を識別順にシリアルからパ
ラレルに変換する手段と、変換されたパラレル画データ
を蓄積する手段と、蓄積された前記パラレル画データを
読み出し色濃度変換し符号化して送信する手段とを有し
ている.〔実施例〕
次に、本発明について図面を参照して説明する。第1図
は本発明の一実施例のブロック図である。The facsimile apparatus of the present invention includes means for converting digital image signals inputted from a personal computer from serial to parallel in identification order, means for accumulating the converted parallel image data, and reading out the accumulated parallel image data to determine the color density. It has means for converting, encoding, and transmitting. [Example] Next, the present invention will be described with reference to the drawings. FIG. 1 is a block diagram of one embodiment of the present invention.
インタフェース回路1は、パーソナルコンピュータ(P
C)から入力のディジタル画信号(R・G−B)を表示
器CRTに出力すると共にデイジタル画信号をPCから
のクロツクCLK周期でサンプリグされたシリアルの画
データ6が変換回路2に出力する.変換回路2は、カウ
ンタ回路3がPCからのクロックCLKで発生した出力
で8ビット毎にシリアルからパラレルに変換した画デー
タ7を蓄積回路4に出力する.制御回路5は蓄積回路4
から読み出した画データを送信する回線の適した圧縮符
号化を行わせて送信する.〔発明の効果〕
以上説明した様に本発明では、パーソナルコンピュータ
からの画信号を識別順にシリアルからパラレルに変換し
メモリに蓄積することにより、複雑なリフレッシュ回路
やパーソナルコンピュータから入力されるCLK (2
1MHz >に応じたメモリーを使用することなく、
簡単にかつ安価な回路にできる効果がある.The interface circuit 1 is a personal computer (P
C) outputs the input digital image signal (R, G-B) to the display CRT, and serial image data 6 sampled at the clock CLK period from the PC is output to the conversion circuit 2. The conversion circuit 2 outputs to the storage circuit 4 image data 7 which is converted from serial to parallel every 8 bits by the counter circuit 3 using the output generated by the clock CLK from the PC. Control circuit 5 is storage circuit 4
The image data read from the image data is compressed and encoded appropriately for the transmission line, and then transmitted. [Effects of the Invention] As explained above, the present invention converts the image signals from the personal computer from serial to parallel in the order of identification and stores them in the memory, thereby converting the CLK (2
1MHz> without using memory according to
This has the effect of making the circuit simple and inexpensive.
第1図は本発明の一実施例のブロック図である。
1・・・インターフェース回、2・・・変換回路、3・
・・カウンタ回路、4・・・蓄積回路、5・・・装置制
御回路。FIG. 1 is a block diagram of one embodiment of the present invention. 1...Interface times, 2...Conversion circuit, 3.
...Counter circuit, 4...Storage circuit, 5...Device control circuit.
Claims (1)
識別順にシリアルからパラレルに変換する手段と、変換
されたパラレル画データを蓄積する手段と、蓄積された
前記パラレル画データを読み出し色濃度変換し符号化し
て送信する手段とを有すること特徴とするファクシミリ
装置。means for converting digital image signals input from a personal computer from serial to parallel in identification order; means for accumulating the converted parallel image data; and reading out the accumulated parallel image data, converting the color density, encoding and transmitting. A facsimile device characterized in that it has means.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1230130A JPH0392062A (en) | 1989-09-04 | 1989-09-04 | Facsimile equipment |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1230130A JPH0392062A (en) | 1989-09-04 | 1989-09-04 | Facsimile equipment |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH0392062A true JPH0392062A (en) | 1991-04-17 |
Family
ID=16903046
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP1230130A Pending JPH0392062A (en) | 1989-09-04 | 1989-09-04 | Facsimile equipment |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0392062A (en) |
-
1989
- 1989-09-04 JP JP1230130A patent/JPH0392062A/en active Pending
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