JPH039199Y2 - - Google Patents

Description

[Detailed explanation of the idea]

"Industrial Application Field" This invention relates to a waveform storage device for storing signals used as a sound source of an electronic musical instrument, for example. "Prior Art" Conventionally, an electronic musical instrument called a synthesizer uses a voltage-controlled oscillator to generate a signal at a frequency with a desired pitch, and then shapes this signal into a waveform to play the piano,
It uses a method that generates the sounds of various musical instruments such as an organ, flute, violin, and guitar. On the other hand, as semiconductor memories have become available at low cost in recent years, a method has been developed in which a portion of the sounds or voices of various musical instruments is stored in a semiconductor memory, and by reading this memory, various musical instrument signals can be obtained. is considered. The pitch of the reproduced musical instrument signal is changed by changing the read speed of the memory. ``Problem that the invention seeks to solve'' When capturing a desired sound signal into a semiconductor memory, it is necessary to accurately capture the beginning of the desired sound and begin writing it into the memory. Conventionally, for example, when a signal S with a waveform as shown in Fig. 3 is taken into memory, a time point <sub>T1</sub> at which the signal level exceeds a set value <sub>V1</sub> is captured, and from this time point <sub>T1</sub> , an AD-converted digitally encoded signal is generated. The operation to write the data into memory is started. When this signal acquisition method is used, a signal having a voltage of V <sub>1</sub> is suddenly written to the head of the memory.
When this signal is read out and reproduced as sound, a signal with voltage V <sub>1</sub> is reproduced at the head, which has the disadvantage of generating spike noise. To overcome this drawback, the point at which the signal crosses zero, for example T <sub>2</sub>
The configuration may be such that writing to the memory is started from this point. However, the signal S has zero-crossing points at many points, and it is difficult to determine from which zero-crossing point writing should be started. In particular, surrounding noise N exists in front of the target signal S. Since the noise N also has a zero-crossing point, it is difficult to start writing from the zero-crossing point because it is necessary to distinguish between the noise N and the target signal S. "Means for solving the problem" In this invention, writing to the memory is started when a zero-crossing point exists, but until the signal level exceeds a predetermined value, the memory address is written every time a zero-crossing point exists. is returned to the initial address, and the operation of constantly writing the signal from the zero-crossing point to the memory is repeated. After time <sub>T1</sub> when the signal level exceeds a predetermined value <sub>V1</sub> , the operation of returning the memory address to the initial address is prohibited and the signal write operation is continued. Therefore, according to this invention, signals can always be taken into the memory from the zero-crossing point. However, since it is possible to store the signal from the zero-crossing point that existed immediately before the point when the predetermined level was exceeded, it is possible to reliably capture the desired signal. ``Example'' Figure 1 shows an example of this invention. In the figure, 1 indicates an input terminal. The input terminal 1 is connected to a signal source such as a microphone, a guitar microphone, a record pickup, etc., and inputs various sound signals. The signal input to input terminal 1 is AD
applied to the converter 2 and the signal detection means 3. The AD converter 2 constantly performs AD conversion on input signals and provides the AD conversion output to the memory 4.
Memory 4 is a RAM that can be written to and read out at any time.
SRAM etc. can be used. Reference numeral 5 indicates an address counter that provides an address signal to the memory 4. A clock pulse is applied to the address counter 5 from a clock source 7 through a variable frequency divider 6. At the time of writing, the variable frequency divider 6 is set to a constant frequency division ratio, but at the time of reading, the frequency division ratio of the variable frequency divider 6 is changed by an operation from the keyboard 8, for example, and the frequency division ratio of the variable frequency divider 6 is set to a constant frequency division ratio. The speed can be selected at any speed, and the pitch of the sound to be reproduced can be arbitrarily selected to play a song. The sound reproduction system includes, for example, a DA converter 21 and a low frequency amplifier 22.
and a speaker 23. Further, an external storage means 24 such as a floppy disk device is provided for recording the waveform data taken into the memory 4 as required. 9 indicates zero cross detection means. This zero cross detection means 9 includes a time constant circuit 9A to which the signal of the most significant bit of the AD converter 2 is applied, an inverter 9B that inverts the polarity of the output of this time constant circuit 9A.
It is constituted by an exclusive OR circuit 9c which takes the exclusive OR of the output of the inverter 9B and the most significant bit signal of the AD converter 2. The AD converter 2 has a conversion code format of, for example, I'S with a symmetrical offset as shown in the table below.
If complement is used, the most significant bit B
The polarity of the signal can be detected depending on whether 1 is "0" or "1".

[Table] Therefore, from the virtual digital waveform M obtained by AD converting the analog signal S shown in Fig. 2A, to the most significant bit B
1 becomes a rectangular wave Pe as shown in FIG. 2E. Therefore, this rectangular wave Pe is applied to the zero-cross detection means 9, and the zero-cross detection signal Pf shown in FIG. 2F is obtained from the zero-cross detection means 9. This zero cross detection signal Pf is applied to one input terminal of an AND gate 11C constituting the reset prohibition control means 11. The reset prohibition control means 11 includes a flip-flop 11A, an inverter 11B, and an AND gate 1.
1C. Flip-flop 11A has a set input terminal ST, and prior to the start of signal acquisition, a set command signal Pc shown in FIG. 2C is applied to set flip-flop 11A in the set state. With this setting, the output terminal becomes L logic, and this L logic signal is transferred to the inverter 11.
B to the other input terminal of the AND gate 11C. As a result, the AND gate 11C is controlled to be open, and the zero-cross detection signal Pf output from the zero-cross detection means 9 is applied to the reset terminal R of the address counter 5. A signal detection means 3 is provided on the preceding stage side of the reset prohibition control means 11. The signal detecting means 3 can be constituted by, for example, a double-wave rectifier circuit 3A and a voltage comparator 3B. The double-wave rectifier circuit 3A performs double-wave rectification on the analog signal S input to the input terminal 1, and converts it into, for example, a positive pulsating current signal. This positive pulsating current signal is applied to the voltage comparator 3B and compared with the set voltage _VR . When the amplitude of the analog signal exceeds the set voltage V _R , the voltage comparator 3B generates a rectangular wave as shown in Figure 2B.
Output Pe. At the first rise of this rectangular wave Pb, the flip-flop 11A is reset and the output terminal Q rises to H logic as shown in FIG. 2D. By resetting the flip-flop 11A, the output of the inverter 11B becomes an L logic, and the AND gate 11C is controlled to be closed, thereby prohibiting the passage of the zero-cross detection signal Pf. (Operation of Embodiment) Therefore, according to the structure of this embodiment, the address counter 5 starts counting in synchronization with the set command signal Pc shown in FIG. , at time _T1 , the zero cross detection signal Pf is applied to the reset terminal R of the address counter 5 through the AND gate 11C, so the address counter 5 is reset and the address applied to the memory 4 is returned to the initial address. After time _T1 , the address counter 5 starts counting clock pulses again and writes the AD converted value of the signal S into the memory 4. At time _T2 , the zero cross detection signal Pf is again applied to the counter 5, and the address of the memory 4 is returned to the initial address again. After time _T2 , the counter 5 starts counting again and writes the digitally encoded signal of the analog signal S into the memory 4. At time _T3 , the zero cross detection signal Pf is again applied to the counter 5, and the address is returned to the initial address. After the time _T3 the memory 4 starts writing signals again. At time T ₄ the analog signal S exceeds the set voltage V _R . As a result, the signal detection means 3 resets the flip-flop 11A and outputs the AND gate 11C.
is controlled to close. Therefore, after time _T4 , even if the signal S crosses zero, the address counter 5 is not reset and writing continues. As a result, memory 4 stores the time point
Signals after T ₃ are written, and the desired signal can be captured immediately after the zero cross point. "Operations and Effects of the Invention" As explained above, according to this invention, waveform data immediately after the zero-crossing point of the target signal can be taken into the memory 4. Therefore, when the signal taken into the memory 4 is read out and emitted as a sound, the sound starts from a small level part close to the zero level, so no noise is generated at the beginning part of the sound. Therefore, you can get good quality sound.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of this invention, FIG. 2 is a waveform diagram for explaining the operation of this invention, and FIG. 3 is a waveform diagram for explaining the disadvantages of the prior art. 1: Input terminal, 2: AD converter, 3: Signal detection means, 4: Memory, 5: Address counter, 6:
Variable frequency divider, 7: clock source, 8: keyboard, 9: zero cross detection means, 11: reset prohibition control means.

Claims (1)

[Claims for Utility Model Registration] A. An AD converter that converts an analog signal to be stored into a digitally encoded signal; B. Storage means for storing the AD conversion output of this AD converter; C. An address signal for this storage means. D detects the zero-crossing point of the above analog signal,
A zero-crossing point detection means that resets the count value of the address counter to the initial value each time a zero-crossing point is detected; E A signal detection means that detects that the analog signal exceeds a preset level; F This signal detection means A waveform storage device comprising: reset prohibition control means for inhibiting the reset operation of the address counter by the zero cross point detection means when detecting that the level of the analog signal exceeds a set value.