JPH0390936A - Conversion system for hardware interruption level - Google Patents

Conversion system for hardware interruption level

Info

Publication number
JPH0390936A
JPH0390936A JP22711189A JP22711189A JPH0390936A JP H0390936 A JPH0390936 A JP H0390936A JP 22711189 A JP22711189 A JP 22711189A JP 22711189 A JP22711189 A JP 22711189A JP H0390936 A JPH0390936 A JP H0390936A
Authority
JP
Japan
Prior art keywords
interrupt
interruption
hardware
level
levels
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP22711189A
Other languages
Japanese (ja)
Inventor
Seiji Mitsuoka
光岡 誠治
Yasuhiro Watanabe
康広 渡辺
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
NEC Solution Innovators Ltd
Original Assignee
NEC Corp
NEC Solution Innovators Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, NEC Solution Innovators Ltd filed Critical NEC Corp
Priority to JP22711189A priority Critical patent/JPH0390936A/en
Publication of JPH0390936A publication Critical patent/JPH0390936A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To start an OS with hardware having different interruption levels without remodeling the OS by converting the interruption level generated from the hardware into an interruption level for OS via a hardware interruption level conversion process. CONSTITUTION:An interruption process 6 includes an interruption level converting function 7 which performs the conversion of interruption levels by reference to an interruption level conversion table 5 and an interruption holding function 8 which performs a check to carry out the interruption processes in order of higher preference levels after conversion of the interruption levels. Furthermore an interruption simulating function 9 is provided to the process 6 to shift a process to an address which is shown by a table of an interruption handler before a change as if an interruption are applied to a hardware interruption level set in an OS 1 directly from the hardware. In such a constitution, the OS 1 can be started with hardware of different interruption levels without remodeling the OS 1.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明はハードウェア割込の処理方式に関し、特にハー
ドウェア割込レベル変換方式に関する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a hardware interrupt processing method, and particularly to a hardware interrupt level conversion method.

〔従来の技術〕[Conventional technology]

従来、目的とするハードウェアに設定されているハード
ウェア割込レベルとOSが管理しているハードウェア割
込レベルが異なった場合、そのハードウェアではOSは
動作しなかった。
Conventionally, if the hardware interrupt level set for the target hardware differs from the hardware interrupt level managed by the OS, the OS will not operate on that hardware.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

上述した従来のハードウェア割込レベルの異なるハード
ウェアをOSがサポートするには、目的とするハードウ
ェア用にOSを改造しなければならないという欠点があ
る。
In order for an OS to support the above-mentioned conventional hardware with different hardware interrupt levels, there is a drawback that the OS must be modified for the target hardware.

〔課題を解決するための手段〕[Means to solve the problem]

本発明のハードウェア割込レベル変換方式は、ハードウ
ェアから発生した割込のレベルを使用するOSの割込の
レベルに変換する手段と、変換後の割込をO5にエミュ
レートする手段と、前記割込を保留する手段とを有する
The hardware interrupt level conversion method of the present invention includes means for converting the level of an interrupt generated from hardware to the level of an OS interrupt to be used, and means for emulating the converted interrupt into O5. and means for suspending the interrupt.

〔実施例〕〔Example〕

次に、本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.

第1図は本発明の一実施例を示す構成図である。FIG. 1 is a block diagram showing an embodiment of the present invention.

OS1の初期化処理2はOSが動作するハードウェア1
0がどの種別なのかを認識するハードウェア種別認識機
能3と、認識されたハードウェア用の割込レベル変換テ
ーブルデータを変換テーブルデータ11,12.13の
中から選択して割込レベル変換テーブル5にセットし割
込ハンドラのテーブルを変更して割込が発生すると割込
レベル変換機能7へ処理が移動する様にする割込レベル
変換データ読込機能4を含む。
Initialization process 2 of OS1 is performed by hardware 1 on which the OS operates.
The hardware type recognition function 3 recognizes which type 0 is, and the interrupt level conversion table data for the recognized hardware is selected from among the conversion table data 11, 12, and 13. 5 and changes the interrupt handler table so that when an interrupt occurs, the processing moves to the interrupt level conversion function 7.

割込処理6は割込レベル変換テーブル5を参照し割込レ
ベル変換を行う割込レベル変換機能7と、割込レベル変
換後に優先度が高い順に割込処理を行なう様にチエツク
する割込保留機能8と、○S1で設定しているハードウ
ェア割込レベルにあたかも直接ハードウェアから割込ん
だ様に変更する前の割込ハンドラのテーブルが示してい
るアドレスへ処理を移行する割込エミュレート機能9と
を含む。
The interrupt processing 6 includes an interrupt level conversion function 7 that converts the interrupt level by referring to the interrupt level conversion table 5, and an interrupt pending function that checks to perform interrupt processing in descending order of priority after converting the interrupt level. Interrupt emulation that shifts the processing to the address indicated by the interrupt handler table before changing the hardware interrupt level set in Function 8 and ○S1 as if the interrupt was directly from the hardware. Function 9 is included.

第2図はOS初期化処理2の流れ図である。同図におい
てハードウェア種別認識21は現在動作しているハード
ウェアの種別を、例えばROM内の固定番地を読むこと
により認識する。認識された種別を受けとった割込レベ
ル変換テーブルセット22はあらかじめハードウェア種
別によって決められている割込レベル変換テーブルデー
タの中から受けとった種別のハードウェア用のデータを
読み込み割込レベル変換テーブル5にセットする。割込
処理アドレス変更23はあらかじめ固定の割込ハンドラ
テーブルに設定されていて、直接割込レベルのハンドラ
に処理が移行する様になっていたアドレスを変更して割
込レベル変換処理へ移行する様にし、変更前の割込ハン
ドラテーブルはデータ領域に退避しておく。
FIG. 2 is a flowchart of OS initialization processing 2. In the figure, a hardware type recognition unit 21 recognizes the type of currently operating hardware by reading, for example, a fixed address in the ROM. The interrupt level conversion table set 22 that has received the recognized type reads data for the hardware of the received type from among the interrupt level conversion table data predetermined according to the hardware type and converts it into the interrupt level conversion table 5. Set to . Interrupt processing address change 23 is set in advance in a fixed interrupt handler table, and changes the address that would have caused processing to directly transfer to the interrupt level handler to transfer to interrupt level conversion processing. and save the interrupt handler table before the change to the data area.

第3図(a)はハードウェア割込発生時の処理の流れを
示す流れ図である。ハードウェア割込が発生すると前記
の割込ハンドラのアドレス変更により割込レベルの変換
31が移行される。割込レベルの変換31は割込レベル
変換テーブル5を参照し割込レベルの変換を行なう。例
えば第3図(b)に示す割込レベル変換テーブル5を参
照し、割込装置51のキーボードの割込が発生した場合
、ハードウェアの設定割込レベル52ではレベル2に設
定されているので、割込レベル変換34のレベル2のハ
ンドラへ制御が移り、割込レベル変換テーブル5を参照
し、ハードウェアの設定割込レベル2に対してOSの認
識する割込レベル53がOになっている事がわかり割込
レベルOに変換する。
FIG. 3(a) is a flowchart showing the flow of processing when a hardware interrupt occurs. When a hardware interrupt occurs, the interrupt level conversion 31 is shifted by changing the address of the interrupt handler. The interrupt level conversion 31 refers to the interrupt level conversion table 5 and converts the interrupt level. For example, referring to the interrupt level conversion table 5 shown in FIG. 3(b), if an interrupt occurs from the keyboard of the interrupt device 51, the hardware setting interrupt level 52 is set to level 2. , control passes to the level 2 handler of the interrupt level conversion 34, refers to the interrupt level conversion table 5, and determines that the interrupt level 53 recognized by the OS is O for the hardware setting interrupt level 2. It turns out that there is an interrupt and converts it to interrupt level O.

次にステップ32は変換後の割込レベルより高優先のレ
ベルがすでに割込んでいるかをチエツクする。割込んで
いなければ割込エミュレート33へ、割込んでいた場合
は割込保留34へ処理を進める。
Next, in step 32, it is checked whether an interrupt has already occurred at a higher priority level than the converted interrupt level. If the interrupt has not occurred, the process advances to the interrupt emulation 33, and if the interrupt has occurred, the process advances to the interrupt pending 34.

割込エミュレート33は割込レベル分のピッ1〜を持っ
た割込中フラグのうちエミュレートするレベルのフラグ
をオンにし、コピーしておいた変更前の割込ハンドラテ
ーブルを参照し、エミュレートをするレベルのハンドラ
へ制御を移す。すなわちあたかもハードウェアからの割
込により直接制御が移った様にする。これにより割込の
エミュレートが行なわれ、現在どのレベルが割込中なの
かがわかる。
The interrupt emulator 33 turns on the flag of the level to be emulated among the interrupt flags with pins 1 to 1 for the interrupt level, refers to the copied interrupt handler table before the change, and emulates the interrupt handler table. Transfer control to the handler at the rate level. In other words, it is as if control was directly transferred due to an interrupt from hardware. This emulates an interrupt and shows which level is currently being interrupted.

割込保留34は割込レベル分のフラグを持った保留中フ
ラグのうち保留するレベルのフラグをオンにする。これ
により現在どのレベルが保留中なのかがわかる。
The interrupt suspension 34 turns on the flag of the level to be suspended among the pending flags having flags corresponding to the interrupt levels. This will tell you which levels are currently pending.

第4図は前記のエミュレートによりOSの割込処理が終
了した後の処理を示す流れ図である。上記のエミュレー
トにより制御移行した後、割込をエミュレートしていた
レベルの割込中フラグをオフにする。その後で保留フラ
グをチエツクして(ステップ41)、現在保留がある場
合には保留中の最優先レベルのものが割込中の最優先レ
ベルのものより優先レベルが高ければ割込エミュレート
42を行なう。この割込エミュレート42は前述した第
3図の割込エミュレート33と同一処理である。又、優
先レベルが高くなければ何もしないで処理を抜ける。
FIG. 4 is a flowchart showing the processing after the OS interrupt processing is completed by the emulation described above. After the control is transferred by the above emulation, the interrupt flag of the level at which the interrupt was being emulated is turned off. After that, the pending flag is checked (step 41), and if there is currently a pending interrupt, if the highest priority level pending interrupt is higher than the highest priority interrupt interrupt emulation 42. Let's do it. This interrupt emulation 42 is the same process as the interrupt emulation 33 shown in FIG. 3 described above. Also, if the priority level is not high, the process exits without doing anything.

〔発明の効果〕〔Effect of the invention〕

以上説明したように、本発明はハードウェアから発生す
る割込レベルをハードウェア割込レベル変換処理によっ
てOS用に割込レベル変換をすることにより、OSを改
造することなしに割込レベル変換テーブルを変更するだ
けで、割込レベルの異なるハードウェアでOSが動作で
きる効果がある。
As explained above, the present invention converts interrupt levels generated from hardware into interrupt levels for the OS using hardware interrupt level conversion processing, thereby creating an interrupt level conversion table without modifying the OS. By simply changing this, the OS can operate on hardware with different interrupt levels.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の一実施例の構成図、第2図は初期化処
理の動作を示す流れ図、第3図および第4図は割込処理
の動作を示す流れ図である。 1・・・OS,2・・・初期化処理、3・・・ハードウ
ェア種別認識機能、4・・・割込レベル変換データ読込
機能、5・・・割込レベル変換テーブル、6・・・割込
処理、7・・・割込レベル変換機能、8・・・割込保留
機能、9・・・割込エミュレート機能、10・・・ハー
ドウェア。
FIG. 1 is a block diagram of an embodiment of the present invention, FIG. 2 is a flowchart showing the operation of initialization processing, and FIGS. 3 and 4 are flowcharts showing the operation of interrupt processing. 1... OS, 2... Initialization processing, 3... Hardware type recognition function, 4... Interrupt level conversion data reading function, 5... Interrupt level conversion table, 6... Interrupt processing, 7... Interrupt level conversion function, 8... Interrupt pending function, 9... Interrupt emulation function, 10... Hardware.

Claims (2)

【特許請求の範囲】[Claims] (1)ハードウェアから発生した割込のレベルを使用す
るOSの割込のレベルに変換する手段と、変換後の割込
をOSにエミュレートする手段と、前記割込を保留する
手段とを有することを特徴とするハードウェア割込レベ
ル変換方式。
(1) A means for converting the level of an interrupt generated from hardware into an interrupt level of the OS used, a means for emulating the converted interrupt in the OS, and a means for suspending the interrupt. A hardware interrupt level conversion method comprising:
(2)ハードウェアから発生した割込のレベルを使用す
るOSの割込のレベルに変換し、変換後の割込をOSに
エミュレートすることを特徴とする特許請求の範囲第一
項記載のハードウェア割込レベル変換方式。
(2) The method according to claim 1, characterized in that the level of an interrupt generated from hardware is converted to the level of an interrupt of an OS to be used, and the converted interrupt is emulated in the OS. Hardware interrupt level conversion method.
JP22711189A 1989-09-01 1989-09-01 Conversion system for hardware interruption level Pending JPH0390936A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP22711189A JPH0390936A (en) 1989-09-01 1989-09-01 Conversion system for hardware interruption level

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP22711189A JPH0390936A (en) 1989-09-01 1989-09-01 Conversion system for hardware interruption level

Publications (1)

Publication Number Publication Date
JPH0390936A true JPH0390936A (en) 1991-04-16

Family

ID=16855650

Family Applications (1)

Application Number Title Priority Date Filing Date
JP22711189A Pending JPH0390936A (en) 1989-09-01 1989-09-01 Conversion system for hardware interruption level

Country Status (1)

Country Link
JP (1) JPH0390936A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7487403B2 (en) 2004-11-12 2009-02-03 International Business Machines Corporation Method for handling a device failure
US7676558B2 (en) 2004-11-12 2010-03-09 International Business Machines Corporation Configuring shared devices over a fabric

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6435633A (en) * 1987-07-31 1989-02-06 Hitachi Ltd Interruption control system
JPS6453237A (en) * 1987-08-24 1989-03-01 Nec Corp Multi-interruption control method
JPS6478329A (en) * 1987-09-19 1989-03-23 Fujitsu Ltd Interruption controller

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6435633A (en) * 1987-07-31 1989-02-06 Hitachi Ltd Interruption control system
JPS6453237A (en) * 1987-08-24 1989-03-01 Nec Corp Multi-interruption control method
JPS6478329A (en) * 1987-09-19 1989-03-23 Fujitsu Ltd Interruption controller

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7487403B2 (en) 2004-11-12 2009-02-03 International Business Machines Corporation Method for handling a device failure
US7676558B2 (en) 2004-11-12 2010-03-09 International Business Machines Corporation Configuring shared devices over a fabric
US7774656B2 (en) 2004-11-12 2010-08-10 International Business Machines Corporation System and article of manufacture for handling a fabric failure

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