JPH0390345U - - Google Patents
Info
- Publication number
- JPH0390345U JPH0390345U JP15104989U JP15104989U JPH0390345U JP H0390345 U JPH0390345 U JP H0390345U JP 15104989 U JP15104989 U JP 15104989U JP 15104989 U JP15104989 U JP 15104989U JP H0390345 U JPH0390345 U JP H0390345U
- Authority
- JP
- Japan
- Prior art keywords
- signal
- count value
- reference pulse
- output signal
- input terminal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 8
- 238000001514 detection method Methods 0.000 description 4
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000003708 edge detection Methods 0.000 description 1
- 230000007274 generation of a signal involved in cell-cell signaling Effects 0.000 description 1
- 230000000630 rising effect Effects 0.000 description 1
Description
第1図は、本考案の割り込み制御機能を有する
マイクロコンピユータの主要構造部を示すブロツ
ク図、第2図は、本考案の動作タイミング図、第
3図は、本考案の応用例を示すブロツク図、第4
図は、本考案の応用例における位相制御系のブロ
ツク図、第5図は、本考案の応用例における位相
制御系のタイミング図、第6図aは、従来の外部
割り込み要求信号発生回路を示すブロツク図、第
6図bは、従来のマスク期間設定回路を示すブロ
ツク図、第7図は従来技術における動作タイミン
グ図、第8図は、従来技術で用いられるソフトウ
エアの処理を示す図である。
1……割り込み入力端子、2……シユミツト回
路、3……割り込み制御回路、4……割り込み要
求信号、5……内部バス、6……コンペアレジス
タ、7……コンパレータ、8……タイマ、9……
コンパレータ一致信号、10……タイマ初期化(
クリア)信号、11……速度誤差量検出部、12
……位相誤差量検出部、13……ループフイルタ
、14……速度制御系ゲイン、15……位相制御
系ゲイン、16……PWM変換部、17……ドラ
ムモータ、18……FG信号検出用磁気ヘツド、
19……PG信号検出用磁気ヘツド、20……F
G信号増幅器、21……PG信号増幅器、22…
…ヘツドスイツチング信号入力端子、23……立
ち上がり/立ち下がり両エツジ検出部、24……
フリー・ランニング・カウンタ(FRC)、25
……キヤプチヤレジスタ0、26……キヤプチヤ
レジスタ1、27……外部割り込み要求信号、2
8……マスク信号、29……汎用タイマ。
Fig. 1 is a block diagram showing the main structural parts of a microcomputer having an interrupt control function of the invention, Fig. 2 is an operation timing diagram of the invention, and Fig. 3 is a block diagram showing an application example of the invention. , 4th
The figure shows a block diagram of a phase control system in an application example of the present invention, Figure 5 shows a timing diagram of a phase control system in an application example of the invention, and Figure 6a shows a conventional external interrupt request signal generation circuit. FIG. 6b is a block diagram showing a conventional mask period setting circuit, FIG. 7 is an operation timing diagram in the prior art, and FIG. 8 is a diagram showing software processing used in the prior art. . 1... Interrupt input terminal, 2... Schmitt circuit, 3... Interrupt control circuit, 4... Interrupt request signal, 5... Internal bus, 6... Compare register, 7... Comparator, 8... Timer, 9 ……
Comparator match signal, 10...Timer initialization (
Clear) signal, 11...Speed error amount detection section, 12
...Phase error amount detection section, 13 ... Loop filter, 14 ... Speed control system gain, 15 ... Phase control system gain, 16 ... PWM conversion section, 17 ... Drum motor, 18 ... For FG signal detection magnetic head,
19...Magnetic head for PG signal detection, 20...F
G signal amplifier, 21...PG signal amplifier, 22...
...Head switching signal input terminal, 23...Rising/falling edge detection section, 24...
Free Running Counter (FRC), 25
...Capture register 0, 26...Capture register 1, 27...External interrupt request signal, 2
8...Mask signal, 29...General purpose timer.
Claims (1)
タにおいて、一定周期の基準パルスが供給される
入力端子と、所定のカウント値を保持する手段と
、初期化されたカウント値から順次計数動作を行
なう手段と、前記保持手段と計数手段の各々のカ
ウント値を比較する手段と、前記入力端子からの
基準パルスおよび前記比較手段からの一致信号に
より出力信号の出力状態を制御する手段とを有し
、前記制御手段は、前記基準パルスの入力により
、前記計数手段のカウント値を初期化すると共に
、前記出力信号の出力を禁止状態とし、前記一致
信号の入力により、前記出力信号の出力を許可状
態とすることを特徴とするマイクロコンピユータ
。 In a microcomputer having an interrupt control function, an input terminal to which a reference pulse of a constant period is supplied, means for holding a predetermined count value, means for sequentially performing a counting operation from an initialized count value, and the holding means and means for comparing the respective count values of the counting means, and means for controlling the output state of the output signal by a reference pulse from the input terminal and a coincidence signal from the comparing means, and the control means includes: By inputting a reference pulse, the count value of the counting means is initialized and outputting of the output signal is prohibited, and by inputting the coincidence signal, outputting the output signal is permitted. microcomputer.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP15104989U JPH0390345U (en) | 1989-12-28 | 1989-12-28 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP15104989U JPH0390345U (en) | 1989-12-28 | 1989-12-28 |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH0390345U true JPH0390345U (en) | 1991-09-13 |
Family
ID=31697366
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP15104989U Pending JPH0390345U (en) | 1989-12-28 | 1989-12-28 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0390345U (en) |
-
1989
- 1989-12-28 JP JP15104989U patent/JPH0390345U/ja active Pending
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