JPH0388334A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To reduce the occupying area of a through hole pad by connecting at least three wiring layers by way of the same through hole. CONSTITUTION:A field insulating film 3 is formed on the surface of an N-type semiconductor substrate 1. A P-type high-concentration diffused layer 2 is formed. Then, a first interlayer insulating film 4 is formed. A first wiring layer 5, a second interlayer insulating film 6, a second wiring layer 7 and a third interlayer insulating film 8 are sequentially formed, and the pattern of photoresist 9 is formed. A single through hole 10 reaching the P-type high concentration diffusing layer 2 is formed by sequentially removing the films and the layers by anisotropic dry etching. Tungsten 11 is embedded, and a third wiring layer 12 is formed. Of the interconnection layers comprising multilayered interconnection layers and the high-concentration diffusing layer which is formed on the main surface of the semiconductor substrate, at least three wiring layers are electrically connected with a metallic conductor layer embedded in the same through hole. Thus, the integration density of elements can be enhanced to a large extent.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to the structure of a semiconductor device and its manufacturing method;
In particular, the present invention relates to a structure of a semiconductor device having a multilayer wiring layer and a method of manufacturing the same.

[Conventional technology]

The structure and manufacturing method of a conventional semiconductor device will be explained with reference to FIG.

FIG. 3(b) shows a vertical cross-sectional view of a conventional semiconductor device having three wiring layers, in which there is a P-wall high concentration diffusion layer 2 and a field insulating film 3 on the main surface of an N-type semiconductor substrate 1. ,
A first interlayer insulating film 4 having a thickness of 7000 layers is provided on the surface. A 1 μm contact hole is formed in the first interlayer insulating film 4 , and a 1 μm thick first wiring layer 5 is connected to the P-wall high concentration diffusion layer 2 . Further, a 1 μm-sized through hole is opened in the second interlayer insulating film 6 having a film thickness of 1 μm, and the second wiring layer 7 and the first wiring layer 5 are connected to each other through a through hole. is a third interlayer insulating film 8 with a film thickness of 1 μm.
exists, and the second wiring layer 7 is connected by a 1 μm through hole.
is connected to the third wiring layer 12.

Next, a method for manufacturing a semiconductor device having the above-mentioned three wiring layers will be described.

First, as shown in FIG. 3(a), a field insulating film 3 made of a thermal oxide film is formed on the surface of an N-type semiconductor substrate 1 by the LOCO3 method, and then a P-type high-concentration diffusion film is formed by a high-dose ion implantation method. Forming Layer 2 Next, a first interlayer insulating film 4 is formed using a BPSG film using the CVD method, a contact hole is opened on the P-wall high concentration diffusion layer 2, and approximately one layer of Si is deposited using a sputtering method. A first wiring layer 5 made of aluminum containing aluminum is formed. Here, in the first wiring layer 5, a portion where a through hole is formed between the upper wiring layer and the upper wiring layer (hereinafter referred to as a through hole pad) is broadly defined as a 3 μm opening.

Next, after a second interlayer insulating film 6 is formed of polyimide, a 1 μm through hole is opened on the above-mentioned through hole pad, and a second wiring layer 7 is further formed. Here, the second wiring layer 7 is connected to the first wiring layer 5 via a through hole provided in the second interlayer insulation M6 described above. Further, similarly to the first wiring layer 5, a 3 μm opening through-hole pad is also provided in the second wiring layer 7.

Next, after forming a third interlayer insulating film 8 made of polyimide on the second wiring layer 7, a 1 μm through hole is opened on the through hole pad of the second wiring layer 7, and then 12 is a form of precept. Here, the third wiring layer 12 is connected to the second wiring layer 7 through the through hole provided in the third interlayer insulating film 8 described above, and is connected to the multilayer wiring layer of the semiconductor device shown in FIG. 3(b). The structure of is completed.

[Problem to be solved by the invention]

The semiconductor device having the conventional multilayer wiring layer described above has a third
When connecting the wiring layer, the second wiring layer, the first wiring layer, and the P-type high concentration diffusion layer, one contact hole and two through holes are required, and the insulating film must be opened three times in total. become.

It is necessary to provide a margin of about 1 μm for one hole-opening process, taking into account variations in photolithographic alignment, etching, and development.

Therefore, if the opening diameter of the contact hole and through hole is 1 μm, an area of 3 μm is required.

Therefore, when connecting the third wiring layer, the second wiring layer, the first wiring layer, and the P-type high concentration diffusion layer, an area of 3 μm of the three layers is consumed for the connection, which is a major drawback.

[Means to solve the problem]

In the semiconductor device having a multilayer wiring layer of the present invention, at least three wiring layers of the multilayer wiring layer and the wiring layer consisting of a high concentration diffusion layer formed on the main surface of the semiconductor substrate are embedded in the same through hole. electrically connected by a metal conductive layer.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1(d) is a longitudinal cross-sectional view showing a first embodiment of a semiconductor device having multilayer wiring layers according to the present invention.

A P-type high-concentration diffusion layer 2 and a field insulating film 3 are provided on the main surface of the N-type semiconductor substrate 1, and a first interlayer insulating film 4, a first wiring layer 5. Second interlayer insulating film 6. Second wiring layer 7. The same through hole reaching the P-type high concentration diffusion layer 2 is formed in the third interlayer insulating film 8, and tungsten 11, which is a metal conductive layer, is embedded in this through hole. First wiring layer5. Second wiring layer 7. Furthermore, the third wiring layer 12 is electrically connected.

Next, a method for manufacturing a structure of a first embodiment of a semiconductor device having multilayer wiring layers according to the present invention will be explained with reference to FIGS. 1(a) to 1(d).

First, as shown in FIG. 1(a), a field insulating film 3 made of a thermal oxide film is formed on the surface of an N-type semiconductor substrate 1 by the LOCO3 method, and then a P-type high-concentration diffusion film is formed by a high-dose ion implantation method. Next, the first interlayer insulating film 4 is formed of a BPSG film using the CVD method.

Subsequently, as shown in FIG. 1(b), a first wiring layer 5. of aluminum containing about one layer of SL with a film thickness of 1 μm is formed. Second interlayer insulating film 6 made of polyimide with a film thickness of 1 μm
．． Second wiring layer 7 made of aluminum with a film thickness of 1 μm. A third interlayer insulating film 8 made of polyimide and having a thickness of 1 μm is successively formed.

Next, as shown in FIG. 1(c), a pattern of photoresist 9 is formed by photolithography, and a third interlayer insulating film 8 is etched by anisotropic dry etching. Second wiring layer 7. Second interlayer insulation 1t16. First wiring layer5. The first interlayer insulating film 4 is sequentially removed to form a single through hole 10 that reaches the P-wall high concentration diffusion layer 2.

Finally, after peeling off the photoresist 9, tungsten 11 is buried in the through hole 10 by selective growth to form a third wiring layer 12 to obtain the structure shown in FIG. 1(d).

FIG. 2(f) is a longitudinal cross-sectional view showing a second embodiment of a semiconductor device having multilayer wiring layers according to the present invention.

A P-wall high concentration diffusion layer 2 and a field insulating film 3 are provided on the main surface of the N-type semiconductor substrate 1, and a first interlayer insulating film 4, a first wiring layer 5. Second interlayer insulating film 6. Second wiring layer 7. The third interlayer insulating film 8 has a through hole reaching the P wall high concentration diffusion layer 2, and the second interlayer insulating film 6. Second wiring layer 7. Through holes are formed that penetrate the third interlayer insulating film 8 and reach the first wiring layer 5, and by filling these through holes with tungsten 11, the P-wall high concentration diffusion layer 2. First wiring layer 5, second wiring layer 7. Electrical connection of the third wiring layer 12 and the first wiring layer 5. Second wiring layer 7. The third wiring layer 12 is electrically connected.

Next, a method for manufacturing a structure of a second embodiment of a semiconductor device having multilayer interconnection layers according to the present invention will be described with reference to FIGS. 2(a) to 2(f).

First, as shown in FIG. 2(a), a field insulating film 3 made of a thermal oxide film is formed on the surface of an N-type semiconductor substrate 1 by the LOCOS method, and then a P-wall is heavily diffused by a high-dose ion implantation method. Next, the first interlayer insulating film 4 is formed of a BPSG film using the CVD method.

Subsequently, as shown in FIG. 2(b), a first wiring layer 5. about one layer of Si-containing aluminum having a thickness of 1 μm is formed. Second interlayer insulating film 6 made of polyimide with a film thickness of 1 μm
．． Second wiring layer 7 made of aluminum with a film thickness of 1 μm. A third interlayer insulating film 8 made of polyimide and having a thickness of 1 μm is successively formed.

Next, a photoresist pattern is formed, and anisotropic dry etching is performed to etch the third interlayer insulating film 8 and the second wiring layer 7.
．． The second interlayer insulating film 6 is sequentially removed to form a plurality of through holes 10a reaching the first wiring layer 5, and the photoresist pattern is peeled off.

Next, as shown in FIG. 2(c), a photoresist 9a having an opening at a predetermined through hole 10a is formed, and the first wiring layer 5. is etched by anisotropic dry etching.
The first interlayer insulating film 4 is sequentially removed to open a through hole 10 that reaches the P-wall high concentration diffusion layer 2.

Subsequently, as shown in FIG. 2(d), the photoresist a is peeled off and the tungsten 11 is inserted into the through hole 10. A selective acid is introduced into the through hole 10a. At this time, in the through hole 10a, the tungsten 11 protrudes onto the third interlayer insulating film 8 and grows into a protruding shape.

Next, as shown in FIG. 2(e), the photoresist b
The protruding portions of the tungsten 11 are etched away by applying and etching back.

Finally, by forming the third wiring layer 12, as shown in FIG. 2(f), the P-wall high concentration diffusion layer 2, the first wiring layer 5. Second wiring layer 7. Electrical connection of third wiring layer 12 and first wiring layer 5. Second wiring layer 7. Electrical connection of the third wiring layer 12 is obtained.

In this embodiment, when there are through holes of a plurality of different depths, it is possible to easily remove the protruding portions of the selectively grown metal that occur on the shallow through holes.

〔Effect of the invention〕

As explained above, the present invention connects at least three wiring layers using the same through hole, thereby eliminating the through hole pads that were conventionally installed in each wiring layer except the top layer of the three wiring layers. It is only necessary to provide the through-hole pad in the lowest interconnection layer, which reduces the area occupied by the through-hole pad and greatly increases the degree of device integration.

[Brief explanation of drawings]

1(a) to (d) are longitudinal cross-sectional views of the first embodiment of the present invention, FIGS. 2(a) to (f) are longitudinal cross-sectional views of the second embodiment of the present invention, and FIG. Figures (a) and (b) are longitudinal sectional views showing a conventional technique. 1... N-type semiconductor substrate, 2... P-type high concentration diffusion layer,
3... Feed insulating film, 4... First interlayer insulating film, 5
...first wiring layer, 6...second interlayer insulating film, 7...
Second wiring layer, 8...Third interlayer insulating film, 9.9a, 9b
... 7 photoresist, 10.10a... through hole, 11... tungsten, 12... third wiring layer.

Claims (2)

[Claims] (1) In a semiconductor device having a multilayer wiring layer on the surface of a semiconductor substrate, at least three of the wiring layers consisting of the multilayer wiring layer and a high concentration diffusion layer formed on the main surface of the semiconductor substrate , a semiconductor device characterized in that the semiconductor device is electrically connected by a metal conductive layer embedded in the same through hole. (2) The method for manufacturing a semiconductor device according to claim (1), including the step of forming an interlayer insulating film on which the uppermost wiring layer of the at least three wiring layers is formed; a step of embedding the metal conductive layer in the through hole by selective growth of metal;
A method for manufacturing a semiconductor device, comprising the step of forming the uppermost wiring layer.