JPH0388193A - Dynamic semiconductor memory device - Google Patents

Abstract

PURPOSE:To perform the serial access mode operation of a DRAM at high speed by incorporating a serial address counter in a chip. CONSTITUTION:When the inverse of RAS is decreased and a reset signal CSET and a signal, the inverse of CSET go to H and L levels, respectively, the transistor for reset of the serial address counter 13 is de-energized, and a row address is fetched. After the lapse of a time tau, a column address is accepted with the latch signal CLTC of a column address 2, and after all the output A0s, A1s... of the serial address counter are set at 0s, count-up is performed sequentially by the toggle of the signals CLTC and the inverse of CLTC. The output is directly inputted to a column decoder 5 via the column address buffer 2, and a fast serial access function can be realized without limiting the number of bits.

Description

[Detailed description of the invention] [Purpose of the invention] (Industrial application field) The present invention relates to a dynamic semiconductor memory device.

(Prior art) Among MO8 type semiconductor memories, 1 transistor/1. Dynamic RAM (DRAM) consisting of capacitors is the most highly integrated. In addition to the normal access mode, recent DRAMs are equipped with high-speed access modes such as page mode, nibble mode, and static column mode. On the other hand, serial access, which allows one row of data to be accessed serially at high speed, is also in strong demand from the field of image processing or the field of computer systems using cache memory.

The conventional page mode is a mode in which data of a selected line of text can be accessed randomly and at high speed. FIG. 9 shows a timing chart of a read cycle in this page mode, and FIG. 10 shows a timing chart of a write cycle. In both cases, the row address strobe signal (RAS) is activated and the column address strobe signal (CAS) is activated.
) and capture the column address when the CAS drops, read or write operations can be performed randomly in the column direction. Therefore, if this page mode is used, one line of data can be accessed serially at high speed by giving an address serially from the outside. Silual access is possible.

However, serial access using this page mode has a speed limit because it is necessary to import the column address from the outside each time in response to a CAS toggle. The reason for this is specifically explained using FIGS. 9 and 10. The reason is that column address setup time tABC% column address◆hold time tCAN is set at the falling edge of CAS. This is because a timing margin required for strobe of the column address is required.

On the other hand, a nibble mode is a mode installed in a normal DRAM. In Figures 11 and 12, respectively,
FIG. 6 shows a timing chart of read-cycle and write cycle in nibble mode. This nibble mode is similar to the page mode described above in that CAS toggle 4 provides high-speed access of consecutive bits in the column direction. However, in nibble meeting mode, CAS
From the second cycle onward, there is no need to capture column addresses. Nibble mode is generally faster than page mode in this regard, which is a major advantage.

However, the biggest drawback of nibble mode is that there is a limit to the number of bits that can be accessed, and it cannot be applied to serial access. The reason why there is a limit to the number of bits that can be accessed is due to the following circumstances. In nibble mode,
High-speed access is achieved by sending a plurality of pieces of data all at once to the data latch register in the first cycle of CAS, and from there sequentially transferring the data to the output port by toggling CAS. Therefore, the number of registers for data latching is the limit on the number of bits that can be accessed. If the number of registers and the number of data for one row are the same, it would be possible to access one row of data at high speed and serially, but mainly due to chip area constraints, 4-bit nibbles are now common. ing.

(Problem to be Solved by the Invention) As described above, in the conventional DRAM, in order to serially access all data for one row at high speed, page
In nibble mode, there was a problem with high speed, and in nibble mode, there was a limit to the number of bits that could be accessed due to chip area.

An object of the present invention is to solve these problems and provide a DRAM that enables high-speed serial access.

[Structure of the Invention] (Means for Solving the Problems) A DRAM according to the present invention is characterized in that it incorporates a serial address counter that generates serial addresses in the column direction. The serial address counter is counted up by toggling CAS, and its output is input to a column address buffer or column decoder to perform serial access.

(Operation) According to the present invention, each CAS in page mode
There is no need to import column addresses from outside when toggling. Therefore, there is no need for timing margins such as column address setup time tASC or column address hold time tell.
Faster page mode operation can be achieved. Furthermore, by generating a serial address using a serial address counter, a high-speed serial access mode can be realized. Moreover, providing a serial address counter does not increase the chip area compared to providing a data latch register that stores data for one row in nibble mode.

(Example) The present invention will be explained in detail below.

FIG. 1 is a block diagram showing the main structure of a DRAM according to an embodiment. Row address that takes in an external address
Buffer 1. Column address ◆ Buffer 2, clock generators 3 and 4 that drive these address buffers 1 and 2, and a column decoder 5 that decodes the fetched address. A row decoder 6, a memory cell array 7 in which 1-transistor/1-capacitor memory cells driven by these decoder outputs are arranged, a sense amplifier and !10 gate 8, which exchange data with the memory cell array 7, and a !10 gate 8. It has an input buffer 9 for latching output data, an output buffer 10, a substrate bias generation circuit 11, and a refresh counter 12 for self-refreshing the memory cell array.These main structures are the same as those of a conventional DRAM.This embodiment In addition to these, a serial address counter 13 that generates serial addresses in the column direction is built in. This serial address counter 13 is configured to count up in response to the toggle of CAS. and its output is column at, res-buffer 2
It is now entered into

FIG. 2 shows an embodiment in which the configuration of FIG. 1 is slightly modified. In this embodiment, serial address counter 13
The output of the column address buffer 2 is directly input to the output part of the column address buffer 2 rather than the input part, that is, the manual part of the column decoder 5. Except for this point, this embodiment is the same as the embodiment shown in FIG.

FIG. 3(a) shows a specific configuration example of the serial address counter 13 used in the embodiment.

This serial address counter is a shift register type counter whose constituent elements are locked CMOS inverters, and the equivalent circuit is shown in Fig. 3(b), and the symbol shown in Fig. 3(c). It shows the first stage and the first stage. Clocked CMO which is a component of this counter
As clocks for controlling conduction and non-conduction of the S inverter, the column address latch signals CLTC and CLTC are used for the lowest address counter, and the clocks for the other address counters are provided by the column address latch signals CLTC and CLTC of the next lower address counter. Output is input. By cascading such address counters, a serial address counter is constructed which generates an address of a predetermined number of bits, for example, one row.

The serial address counter has reset transistors Ql, Q2 . ..., and has a reset signal C9ET,
It can be initialized by C3ET.

FIG. 4 is a timing diagram showing the operation of the serial J address counter described above. Serial using this◆
To explain the operation of the address counter, first, when RAS falls and becomes active, the reset signal C5ET becomes "H" level and C3ET becomes "L'" level, which causes the reset transistors Ql and Q2 of the serial address counter to ．． ...becomes non-conductive. and R.A.
With the fall of S, the row address is taken in, and after a time τl has elapsed, the column address latch signal C
LTC is 'H Lebel.

By bringing CLTC to the m L 11 level, the column address is accepted. At this time, the serial address counter outputs A Os, A is.

All of A2s*... are set to "Om." After that, the latch signal CLT is set by toggling CAS.
When C becomes “H” level and CLTC becomes “L” level,
AOs-1, Al5-0. A25-0. -..., and then the latch signal CLTC goes to ``H# level''.

When CLTC goes to “L” level, AOs-1°A15=
1. A2s -0,-..., and then sequentially CLT
The count is increased by toggling C and CLTC.

Therefore, by inputting the output of this serial address ◆ counter through a column address ◆ buffer as shown in Figure 1, or directly to a column decoder as shown in Figure 2, page mode can be used. Serial access mode can be realized.

According to this embodiment, serial access can be performed without requiring an external column address strobe, and a serial access function can be realized that is faster than the conventional page mode. Furthermore, the number of bits for serial access is not limited as in nibble mode.

Next, an embodiment in which the present invention is applied to a DRAM with a pointer function will be described. The pointer function here is a so-called cueing function that enables serial access to a column address from an arbitrary address. Such a function is useful, for example, in an image memory to facilitate horizontal dot scrolling.

FIG. 5 shows a serial address counter built into a DRAM of such an embodiment.

The overall structure of the DRAM is the same as that shown in FIG. 1 or 2. Here, only the first row is shown. This serial address counter is a so-called preset type counter,
a main counter 51 that sequentially generates serial addresses;
A slave counter 52 for latching the data of this main counter 51 to control the next stage main counter, and a preset port for presetting these to external addresses.

It has 53.

FIG. 6 shows a clock generation circuit that generates the control clock CTl for this serial address counter. The control clock signal HOLD entering the preset boat 53 is “
The first clock CTO is not generated while the control clock HOLD is at the “H” level, and the CTO
A clock CTI whose frequency is sequentially divided by 172 in synchronization with a latch signal CLTC generated in synchronization with the toggle of AS.

C70, . . . are configured to occur.

Next, the operation of the serial address counter shown in FIG. 5 will be explained with reference to the timing diagram shown in FIG. 7.

After the external control signal RAS falls and the row address is captured, the latch signal CL is activated at time tl from the fall of RAS.
TC becomes 'H' level and the reception of the column address starts. The latch signal CLTC falls to the g L II level again due to the fall of CAS, and the column address is latched. In parallel, CAS
While the control signal HOLD is at "H" level until the data Ate falls, the data input to the preset boat 53
.

The serial address counter is preset to an external address by Alc. In Figure 7, for the case of a 2-bit serial address counter,
This shows a state in which the lowest address AO is preset to the H" level and the next address Al is preset to the "L" level. After this, the latch signal CLTC operates in response to the toggle of CAS, and as a result, the clock CTO becomes H. ” level, and this clock CTO and counter output SOs cause the next clock CTI to go to the “H# level,” and so on. As a result, the serial address counter returns to the preset state (S〇-1, 5L-0) to 5o
-0, 5l-1, then 5o-1, Sl-1, and so on.

The output of this preset type serial ◆address counter is input via the column address buffer or directly to the column decoder as in the previous embodiment, and a serial access mode applying the page mode is activated. Realized.

This embodiment also provides the same effects as the previous embodiment.

By the way, DRAMs generally have a built-in refresh counter for auto-refresh as shown in FIGS. 1 and 2. Therefore, in implementing the present invention, it is conceivable to share a serial address counter and a refresh counter for serial access. In that case, n times of refresh
Since cycles may be performed not consecutively but with a serial access mode in between, a register is required to temporarily hold the refresh address.

Figure 8 shows the DR, A of an embodiment that takes such circumstances into consideration.
This is a schematic configuration of a counter for auto-refresh monthly serial access in M. A refresh address register circuit 82 is provided in parallel with the counter circuit 81, so that data can be exchanged between them. The refresh address is always outputted through the refresh address register circuit 82, and the counter circuit 81 can also be preset to the address latched by the refresh address register circuit 82. This makes it possible to interrupt the refresh cycle in the middle, execute the serial e-access mode, and then continue the interrupted refresh cycle.

By sharing the refresh counter and serial address counter in this way, the DRAM chip area can be used effectively.

[Effects of the Invention] As described above, according to the present invention, a DRAM capable of high-speed serial access mode operation can be obtained by incorporating a serial address counter in a chip.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of a DRAM according to one embodiment of the present invention. FIG. 2 is a block diagram showing the configuration of a DRAM according to another embodiment. A diagram showing the equivalent circuit of the serial address counter built in the example DRAM and a clocked CMOS inverter that is a component thereof. FIG. 4 is a timing diagram for explaining the operation of the serial address counter. Figure 6 is an equivalent circuit diagram showing an example of the configuration of another serial address counter, Figure 6 is an equivalent circuit diagram showing an example of the configuration of its clock generation circuit, Figure 7 is a timing diagram for explaining the operation, Figure 8 shows the serial counter shared with the refresh counter.
A block diagram showing an example of the configuration of an address counter. Figure 9 is a timing diagram showing a read cycle in DRAM page mode. Figure 10 is a timing diagram showing a write cycle. Figure 11 is a timing diagram showing a write cycle in DRAM page mode. FIG. 2 is a timing diagram showing a read cycle, and FIG. 2 is a timing diagram showing a write cycle. DESCRIPTION OF SYMBOLS 1... Row address buffer, 2... Column address buffer, 3, 4... Clock generator, 5... Column decoder, 6... Row decoder, 7... Memory cell array, 8... sense amplifier/I10 gate, 9... input buffer, 1o...
Output buffer, 11...substrate bias generation circuit, 12
...Refresh counter, 13...Serial◆
Address counter.

Claims (4)

[Claims] (1) A dynamic semiconductor memory device characterized by having a built-in serial address counter that generates column-direction serial and addresses. (2) The serial counter is counted up by toggling the external column address strobe signal,
2. The dynamic semiconductor memory device according to claim 1, wherein the output thereof is input to a column address buffer or a column decoder to perform serial access. (3) The dynamic semiconductor memory device according to claim 1 or 2, wherein the serial address counter has a presetting function for external addresses. (4) The serial address counter is refreshed.
4. The dynamic semiconductor memory device according to claim 1, wherein the dynamic semiconductor memory device is shared with a counter.