JPH0388041A - Task switching system - Google Patents

Abstract

PURPOSE:To shorten a task switching time and to prevent system performance from being dropped by saving register information in a corresponding intra- memory register storing area in an intra-memory register storing area only when the register information is not stored in a register storing area and then copying the contents of the information. CONSTITUTION:Plural register storing areas 30-0 to 30-N for storing register information are formed in a processor, and when register information correspond ing to tasks allocated to the processor by a task allocating means 80 is stored in the register storing areas 30-0 to 30-N, the register information is copied/ saved between the areas 30-0 to 30-N and an intra-processor register 20. Only when the register information is not stored, the register information is copied/ saved between the register 20 and intra-memory register storing areas 60 formed in a main storage device 40. Consequently, the task switching time can be shortened and the system performance can be improved.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a task switching method in a computer system.

[Conventional technology]

The task switching method in conventional computer systems is
A register storage area is provided for each task on the main memory, and when a given task is assigned to a processor, register information is copied from the register storage area on the main memory to a register in the processor, and the task is transferred to the processor. After that, when a new task is switched, register information in the processor is saved to a register storage area corresponding to the task to be switched in the main memory.

[Problem to be solved by the invention]

In the conventional task switching method described above, register information is copied and saved to the register storage area of the main memory every time the task is switched, which results in frequent access to the main memory and increases the time it takes to switch tasks. In addition to this problem, there is also the problem that system performance deteriorates because there is a high possibility that access to the main storage device will compete with a device such as a human output control device that accesses the main storage device asynchronously with the processor.

An object of the present invention is to shorten task switching time and to prevent system performance from deteriorating due to access contention.

[Means to solve the problem]

In order to achieve the above object, the present invention includes a main storage device having an in-memory register storage area for storing register information corresponding to a task, and a processor having an in-processor register to which register information corresponding to the task to be executed is copied. In a task switching method in a computer system, a plurality of register storage areas for storing register information are provided in the processor, and processor allocation is a means for selecting a task to which a processor is allocated from waiting tasks. When switching tasks, the task allocation means stores the register information corresponding to the task selected in the register storage area, so that the contents of the register in the processor are copied to the copy source in the register storage area. After the task allocation is saved in the register storage area, the register information corresponding to the task selected by the means is copied to the register in the processor sensor, and the task allocation is saved in the register storage area. Since the register information corresponding to the task is not saved in the register saving area, after the contents of the registers in the processor are saved to the copy source register saving area in the register saving area, the contents of the register saving area are saved. The register information stored in one of the register storage areas is saved to a corresponding in-memory register storage area of the in-memory register storage areas, and the task is further allocated to the register storage area in which the register information is saved. register storage area control means for copying the contents of an in-memory register storage area corresponding to the task selected by the means, and then copying the contents of the register storage area in which the contents of the in-memory register storage area have been copied to the registers in the processor; It was established.

[For production]

The main storage device is provided with an in-memory register storage area for storing register information corresponding to a task, and the processor has multiple register storage areas for storing register information, and an in-processor register to which register information corresponding to the task to be executed is copied. and is provided. The task allocation means selects a task to which a processor is to be allocated from among waiting tasks. The register storage SN area control means performs task allocation by registering the contents of the registers within the processor if the register information corresponding to the task selected by the means is stored in any of the multiple register storage areas provided within the processor. It is saved in a copy source register storage area in the storage area, and then the task allocation stored in the register storage area copies the register information corresponding to the task selected by the means to the register in the processor. Also,
If the register information corresponding to the task selected by the means is not saved in the register save area, the contents of the registers in the processor are saved to the copy source register save area in the register save area, and then the register is saved. A means for saving register information stored in one of the areas to a corresponding in-memory register saving area among the in-memory register saving areas, and further assigning a task to the register saving area where the register information was saved. copies the contents of the in-memory register storage area corresponding to the selected task, and then
Copy the contents of the register save area in memory to the register in the processor.

〔Example〕

Next, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of the present invention, which includes a processor 10 and a main memory 40. As shown in FIG. The processor 10 has an internal register 20 and a processor 10
The processor includes (N+1) in-processor register storage areas 30-0 to 30-N corresponding to interrupt levels #O to #N, and a register storage area control means 70. The main storage device 40 also includes a control table 50, an in-memory register storage area 60 for storing register information of each task in the system, and task allocation means 80.

As shown in FIG.
It has a corresponding area. and interrupt level #j
(j-0~N) Task assignment is done by means 80 in the corresponding area.
The identifier Tj(i+1) of the task currently assigned to interrupt level #j and the identifier Tj(+) of the task assigned immediately before are stored.

For task allocation, the means 80 selects one of the tasks waiting to be allocated in the processor IO based on the task running priority level given to each task, and assigns the selected task to the interrupt level corresponding to the task running priority level. Furthermore, among the identifiers of the currently allocated tasks stored in the control table 50, the identifier stored in the area corresponding to the interrupt level to which the selected task is allocated is updated.

At the time of task switching, the register storage area control means 70 corresponds to the interrupt level of the newly running task (interrupt level #j) among the areas corresponding to each interrupt level in the control table 50. The identifier Tj (
i) and the currently assigned task identifier Tj (
i+1), and since they are inconsistent,
The register storage area 30- in the processor corresponding to the interrupt level #j of the task newly started to run among the register storage areas 30-O to 30-N in the processor sensor
The contents of j are saved in the area corresponding to the identifier Tj (1) of the task assigned immediately before in the in-memory register saving area 60, and the contents of the currently allocated task in the in-memory register saving area 60 are saved. The identifier Tj (i
+1) is restored to the in-processor register save area 30-j corresponding to interrupt level #j among the in-processor register save areas 30-0 to 30-N.

3 and 4 are time charts showing an example of task switching, FIG. 5 is a flowchart showing an example of processing by the register storage area control means 70, and FIG. 6 is a flowchart showing an example of processing by the task allocation means 80. The operation of this embodiment will be explained below with reference to each figure.

First, when the task switching is performed as shown in FIG. 3, that is, in the interval from time tO to t1, task A has a task running priority level corresponding to interrupt level #n.
However, in the interval from time t1 to time t2, task B, which has a task running priority level corresponding to interrupt level #m, runs at time t1.
2 to t3, the operation will be explained using an example in which a task C having a task running priority level corresponding to interrupt level #n runs.

At time tl, task A is switched to task B. When switching from task A to task B,
The task allocation means 80 is as shown in the flowchart of FIG.
In step S81, the interrupt level #m of task B to be newly assigned to the processor 10 is obtained, and in the next step 382, each separate level #m on the control table 50 is obtained.
The currently assigned task identifier Tm(++1) stored in the area corresponding to interrupt level #m among the areas corresponding to 0 to #N is assumed to be the identifier of task B.

When the task allocation means 80 updates the contents of the control table 50, the register storage area control means 70 starts the process shown in the flowchart of FIG. It is saved in the processor register storage area 30-n corresponding to the interrupt level #n for the task among the processor register storage areas 30-0 to 30-N, and then allocated to the processor 10 in step S71. The interrupt level #m of task B is obtained, and in the next step S72 *I <
The identifier Tm(
i) and the currently assigned task identifier Tm(++
1) is obtained, and the two are compared in the subsequent step S73. If both are equal (step S74 is YES)
), the register storage area control means 70 stores the internal processor register 20 in the internal processor register storage area 30-.
After copying the contents of m and starting running task B (step 578), the process ends.

In addition, if the two do not match (if the judgment result in step 374 is No), in step 375, task B, which is to be newly run, in the register storage areas 30-0 to 30-N in the processor is selected. saves the contents of the disk storage area 30-m in the processor corresponding to the interrupt level #m in the area corresponding to the identifier Tm (+) of the task assigned immediately before in the register storage area 60 in the memory;
In the next step 376, the currently allocated task identifier Tm(
++1) is restored to the processor register storage area 30-m corresponding to interrupt level m among the processor register storage areas 30-O to 30-N;
In the next step 377, the identifier Tm(i) of the task assigned immediately before, which is stored in the area corresponding to the interrupt level #m of the control table 50, is set to indicate task B, and then the process in step 37B is performed. Do this.

At time t2, task B is switched to task C. In this case as well, the task allocation described above is
0 causes the control table 50 to be updated. That is,
In step S81, the interrupt level #n of task C newly assigned to the processor 10 is determined, and in the next step 382, the currently assigned interrupt level #n stored in the area corresponding to the interrupt level #n of the control table 50 is determined. The identifier Tn (++1) of the current task is updated to indicate task C.

When the task allocation control table 50 is updated by the means 80, the register storage area control means 70 starts the process shown in the flowchart of FIG. Internal processor register storage area 30- corresponding to interrupt level #m of task B in storage areas 30-0 to 30-N
Then, in step 371, the interrupt level #n of the task C to be newly assigned to the processor 10 is obtained, and in the next step S72, the interrupt level #n of the task C corresponding to the interrupt level #n of the control table 50 is obtained. Identifier Tn of the task assigned immediately before stored in the area
(i) and the currently assigned task identifier Tn (
++1) is obtained, and the two are compared in the subsequent step S73. Here, the identifier Tn of the task assigned immediately before
(i).

The currently assigned task identifiers Tn(++1) indicate task A and task C, respectively, and since the judgment result in step S74 is No, the disk storage area 30-n in the processor is replaced. . The internal processor register storage area 30-n is replaced with the internal processor register storage area #30-n in step 375.
The contents of -n are saved in the area corresponding to the identifier Tn (+) of the task assigned immediately before in the in-memory register saving area 60, and in the next step S76, the contents of the in-memory register saving area 60 are saved. This is done by copying the contents of the area corresponding to the assigned task identifier Tn(++1) to the in-processor register storage area 30-n.

After replacing the in-processor register storage area 30-n, the register storage area control means 70 performs step S7.
In step 878, the identifier Tn (i) of the task assigned immediately before, which is stored in the area corresponding to the interrupt level #n of the control table 50, is set to indicate task C, and then in step 878, The contents of the in-processor register storage area 30-n are copied to the register 20, and task C starts running.

Next, if the task switching is performed as shown in FIG.
However, in the interval from time t1 to time t2, task B, which has a task running priority level corresponding to interrupt level #m, runs at time t1.
2 to t3, the operation will be explained again by taking as an example the case where task A having the task running priority level corresponding to interrupt level #n runs.

Until time t2, the same operation as described above in FIG. 3 is performed, and at time t2, task B is switched to task A. When switching from task B to task A, the task allocation means 80 obtains the interrupt level #n for the task to be next allocated to the prosensor 10 in step S81, and performs control in the next step S82. The currently assigned task identifier Tn(i) stored in the area corresponding to interrupt level #n on the table 50 is set to be the one shown in task A.

II When the update of the JB table 50 is completed, the register storage area control means 70 starts the process shown in the flowchart of FIG.
The contents of 0 are saved in the register storage area 30-O to 3 in the processor.
The interrupt level #m of task B among 0-N is saved to the corresponding in-processor register storage area 30-m, and the interrupt level # of the task to be assigned next to the processor 10 in step S71. n is obtained, and in the next step S72, the identifier Tn (i) of the task assigned immediately before and the identifier Tn of the currently assigned task stored in the area corresponding to the interrupt level #n of the control table 50 are obtained. (++1) and step S
73, the two will be compared.

Here, task identifiers Tn (i), Tn (++1
) both indicate task A, and step 3
74 is YES, the register storage area control means 70 saves the register storage area 30-n in the processor.
Copy the contents as they are to the register 20 in the processor,
Start running task A. Therefore, according to this embodiment, the register storage area in the main memory is not accessed at all, such as when restarting a task that has been interrupted by an external interrupt, or when there is only one task at one interrupt level. Since there is no need to do this, it is possible to speed up task switching.

In the above-described embodiment, one in-processor register storage area is provided corresponding to each side interrupt level, but it is also possible to provide a plurality of in-processor register storage areas in the processor regardless of the interrupt level. , only when the register information corresponding to the task to which a new processor is allocated is not saved in the register storage area within the processor, is it copied or saved to the register storage area in memory on the main storage device. It can also be done.

〔Effect of the invention〕

As explained above, the present invention provides a plurality of register storage areas for storing register information in a processor, and stores register information corresponding to a task allocated to a processor in the register storage area in the processor by means of task allocation. If so, copy register information between the register storage area provided in the processor and the registers in the processor.

Register information is saved, and only if it has not been saved, the register information is copied and saved to the in-memory register save area provided in the main memory, and the register information in the processor is saved. When a processor is assigned to a task whose register information is saved in the storage area, it is possible to switch tasks without accessing the register storage area in memory on the main memory, which reduces task switching time. can be shortened. Furthermore, since access to the main memory device can be reduced, main memory contention with control devices other than the processor can be reduced, and system performance can be improved.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention, FIG. 2 is a diagram showing an example of the contents of the control table 50, FIGS. 3 and 4 are time charts showing task switching operations, and FIG. 5 is a register storage area. A flowchart showing an example of processing by the control means 70, and FIG. 6 is a flowchart showing an example of processing by the task allocation means 80. In the figure, 10...Prosensor, 2o...Register in the processor, 30-0 to 30-N...Register storage area in the processor, 40...Main memory, 5°...
- Control table, 60...Register storage area in memory, 70...Register storage area control means, 8o...Task allocation means.

Claims (1)

[Scope of Claims] A computer system comprising a main memory having an in-memory register storage area for storing register information corresponding to a task, and a processor having an in-processor register to which register information corresponding to a task to be executed is copied. In the task switching method, a plurality of register storage areas for storing register information are provided in the processor, and a task allocation means selects a task to be allocated to a processor from among tasks waiting to be allocated to a processor; , the register information corresponding to the task selected by the task allocation means is stored in the register storage area, so that the contents of the register in the processor are saved to a copy source register storage area in the register storage area. After that, the register information corresponding to the task selected by the task allocation means stored in the register storage area is copied to the register in the processor, and the register information corresponding to the task selected by the task allocation means is copied to the register. Since the contents of the register in the processor are not saved in the storage area, the contents of the register in the processor are saved in one of the register storage areas after being evacuated to the copy source register storage area in the register storage area. The register information is saved to a corresponding in-memory register saving area among the in-memory register saving areas, and further, the in-memory register corresponding to the task selected by the task allocation means is saved in the register saving area where the register information is saved. A task switching method comprising register storage area control means for copying the contents of the storage area and then copying the contents of the register storage area into the register in the processor. .