JPH0387789A - Display circuit for peripheral part of crt display screen - Google Patents

Abstract

PURPOSE:To obtain an easy-to-see screen by displaying a non-display area with plain-color half-tone data by using a horizontal and a vertical synchronizing signal, a blanking signal and a half-tone data memory. CONSTITUTION:A horizontal and a vertical non-display period are detected with the horizontal and vertical synchronizing signals (b) and (c) and the horizontal and vertical blanking periods of the video signal (a) and the total blanking period is detected. Further, the half-tone data memory 15 which outputs the plain-color half-tone data signal is provided. An insert half-tone data signal generating circuit 27 generates an insert half-tone data signal which contains the half-tone data signal only in the total blanking period and becomes a high- level signal in the remaining section and an AND signal between an OR signal between the insert half-tone data signal and each non-display period signal, and the video signal is generated, so that the half-tone data signal is inserted in each non-display period. This AND signal is displayed as a corrected video signal and then the plain-color half-tone data is obtained in the non-display area of the peripheral part. Consequently, characters at the head or tail of a line can clearly be recognized.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a CRT display device that displays characters, etc., and particularly relates to a CRT display device that displays characters, etc., and particularly to a CRT display device that displays plain halftone data on the periphery of a CRT display screen. The present invention relates to a display circuit.

[Prior Art] In a CRT display device used as a terminal for an information processing device, the video signal input from the information processing device is a digital signal, and the images displayed are often characters or figures. CRT display devices that display characters and graphics in this manner are required to display accurate graphics and characters.

FIG. 3 is a diagram showing a display screen of a CRT display device. In the figure, 1 is an outer frame, and the inside of this outer frame 1 is a display screen 2 of a CRT display tube. Display screen 2 is maximum (horizontal SMX vertical PM
), however, pincushion distortion occurs in the peripheral area near the outer frame 1, and due to variations in the dimensional accuracy of the outer frame 1 and the deflection position accuracy of the electron beam, the outer frame 1
- If characters are displayed up to the cup, there are problems such as the observer seeing << 1. Therefore, generally, a strip-shaped non-display area 2a having a certain width is provided near the outer frame 1 to display characters.

Actual data such as figures are stored in the horizontal SoX! formed inside the non-display area 2a. It is displayed within the display area 2b of Pn.

FIGS. 4 and 5 are time charts showing the relationship between the video signal a, the horizontal synchronizing signal S, and the vertical synchronizing signal C so that data such as a character 1 graphic is displayed only in the display area 2b. A horizontal blanking period THII is provided in the video signal a so as to include the horizontal retrace period Ts (pulse width) in the horizontal synchronization signal S, and this horizontal blanking period THB corresponds to the left and right non-display areas 2a. It is set wide by the non-display period TB. Therefore, the electron beam is scanned over the entire display screen 2 including the non-display area 2a, but since the signal level of the video signal a is 0 during the horizontal bunking period THH, nothing is seen in the left and right non-display areas 2a. It becomes a dark state where it is not displayed.

Similarly to the case of the horizontal synchronizing signal S, the relationship between the vertical synchronizing signal C and the video signal a is such that the vertical blanking period Tv8 including the vertical retrace period Tc is the non-display period 'rp corresponding to the upper and lower non-display areas 2a. It is set as wide as possible. Therefore,
The upper and lower non-display areas 2a are in a dark state where nothing is displayed.

[Problems to be Solved by the Invention] However, if a dark non-display area 2a in which nothing is displayed is provided at the periphery of the display screen 2 as shown in FIG. When displaying characters or figures in black on the screen, if the characters are displayed at the beginning or end of a line, 1. The border between the character and the dark non-display area where nothing is displayed looks blurred, making it very difficult to see.Furthermore, for example, when the character [T] is displayed on the top line. , [T] is unclear because the border that touches the non-display area appears blurred.
A problem arises in which the corresponding character cannot be immediately determined.

The present invention was made in view of these circumstances, and
By displaying non-display areas with plain halftone data using horizontal and vertical synchronization signals, blanking signals, and halftone data memory, the beginning or last character of a line can be clearly recognized, and it is easy for the observer to see. It is an object of the present invention to provide a peripheral display circuit for a CRT display screen that can provide a very easy-to-see screen.

[Means for Solving the Problems] In order to solve the above problems, the peripheral display circuit of the CRT display screen of the present invention uses an exclusive OR of the horizontal blanking period of the horizontal synchronizing signal and the horizontal blanking period of the video signal. A horizontal non-display period detection circuit that detects a horizontal non-display period consisting of a period of time, and a vertical non-display period that detects a vertical non-display period consisting of an exclusive OR period of a vertical blanking period in a vertical synchronization signal and a vertical blanking period of a video signal. a non-display period detection circuit;
A total blanking period detection circuit that detects a total blanking period consisting of a logical sum period of each blanking period, a halftone data memory that stores plain halftone data, and a halftone data memory output from the halftone data memory. An insertion halftone data signal generation circuit that outputs a logical sum signal of the data signal and an inverted signal of the total blanking period signal output from the total blanking period detection circuit as an insertion halftone data signal, and the insertion halftone data signal The apparatus includes an AND circuit that outputs an AND signal of the inserted halftone data signal output from the generation circuit, the OR period signal of each detected non-display period, and the video signal as a corrected video signal. .

[Effect]

In the peripheral display circuit of the CRT display screen configured in this way, the horizontal and vertical synchronizing signals and the horizontal and vertical synchronization signals of the video signal are
A horizontal non-display period and a vertical non-display period are detected with the vertical blanking period. Additionally, the total blanking period obtained by adding up each blanking period is detected. Further, a halftone data memory for outputting a plain halftone data signal is provided.

Then, the insertion halftone data signal generation circuit generates an insertion halftone data signal that includes the halftone data signal only during the total blanking period and is a high level signal during the remaining period. Then, by creating an AND signal of the inserted halftone data signal, the logical sum signal of each non-display period signal, and the video signal, the halftone data signal is inserted into each non-display period. Therefore, when this AND signal is displayed on a CRT display tube as a corrected video signal, plain halftone data is displayed in a non-display area at the periphery of the CRT display screen.

[Example] An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a circuit diagram showing a peripheral display circuit of a CRT display screen according to an embodiment. The same parts as in FIGS. 3 to 5 are given the same reference numerals.

11 in the figure is a CRT control section, and this CRT control section 11
sends a horizontal synchronizing signal having a period TH and a vertical synchronizing signal C having a period TV to a drive circuit 13 that energizes each deflection coil wound around the CR7 display tube 12. Also,
In the code buffer 14, the CRT control section stores character codes for one screen to be displayed on the CR7 display tube 12, which are output from a main control section consisting of a main processor (not shown). Further, in the halftone data memory 15, CR
2-bit halftone data to be displayed on the non-display area 2a of the display screen 2 of the 7 display tube 12 is stored. Note that this halftone and video data can be arbitrarily rewritten from the main control section.

When the code buffer 14 receives successive address signals from the CRT control section 11, it sends the character code stored at the corresponding address to the next character generator 16. The character generator 16 stores each dot pattern character as a dot matrix, and when a character code is input from the code buffer 14, it outputs each dot in the horizontal direction of the dot matrix corresponding to the corresponding character code as a parallel dot data signal. The parallel/serial converter 17 converts the input parallel dot data signal into a serial dot data signal, that is, the digital video signal a shown in FIGS. 4 and 3.

The video signal a outputted from the parallel/serial converter 17 is waveform-synthesized by an OR gate 18, and a synthesized video signal d is generated by a pair of AND circuits 19a and 19b having three input terminals.
is input to each input terminal.

Further, the horizontal synchronizing signal output from the CRT control section 11 is sent to the drive circuit 13 and is also input to one end of the exclusive OR circuit 20.

Similarly, a CRT is connected to the other end of this exclusive OR circuit 2'0.
A horizontal blanking signal e output from the control section 11 is input. As shown in FIG. 2, since the horizontal blanking period T)I8 of the horizontal blanking signal e includes the horizontal retrace period TB in the horizontal synchronization signal, the output signal f of the exclusive OR circuit 20 is The level is high (H) only during the horizontal non-display period TE corresponding to the non-display area 2a. Therefore, this exclusive OR gate 20 constitutes a horizontal non-display period detection circuit.

The output signal f of the exclusive OR circuit 20 is output from the AND gate 21
is input to. The other end of this AND gate 21 has a CR
The vertical blanking signal g output from the T control section 11 is inverted in level by an inverter 22 and inputted.

The output signal of the AND gate 21 is input to an OR gate 23 having three input terminals. That is, as shown in FIG. 2, this output signal is generated during the vertical blanking period Tv.
The low (L) level is maintained throughout a period (T va + T v ) obtained by adding a period TD equal to the horizontal retrace period TB shown in FIG.

The vertical synchronizing signal C output from the CRT control section 11 is input to the exclusive OR circuit 24 together with the vertical blanking signal g. Therefore, this exclusive OR circuit 24 constitutes a vertical non-display period detection circuit that outputs an output signal i that is at a high (H) level only during the vertical non-display period T corresponding to the vertical non-display area 2a. Then, the output signal i of the exclusive OR circuit 24 is inputted to the OR gate 23.

Furthermore, the horizontal blanking signal e and the vertical blanking signal g are input to the OR gate 25. Therefore, this OR gate 25 outputs a total blanking period signal j that is at a high (H) level only for the total blanking period indicated by the logical sum period of the horizontal blanking period TFIB and the vertical blanking period TvB. Configure a period detection circuit. The level of this total blanking period signal j is inverted by an inverter 26, and then input to the OR gate 23 as an inverted total blanking period signal.

The output signal m of the OR gate 23 is
, 19b is manually operated.

Further, the total blanking period signal j output from the OR gate 25 is input to the other input terminal of the OR gate 18. Therefore, as shown in FIG. 2, in the composite video signal d output from the OR gate 18, a video data signal is inserted for the display period T5D of data corresponding to the display area 2b of the video signal a, and the remaining total block is Ranking period (
T lIa+T vB) maintains a high (H) level.

The halftone data memory 15 contains halftone data [do dl
] is memorized. Therefore, the main control unit produces the sum of [00], which is the lowest brightness, dark, [l(], which is the highest brightness), and two types of halftones, which are the intermediate brightness, [011, [101]. It is possible to specify four types of values, but in the embodiment, one of the two types of data [013 and [101] that is a halftone is stored as plain halftone data ε. The 2-bit data constituting the halftone data signal is sent to each OR gate 27a, 27b via each output port D., DI.
The inverted total blanking period signal k output from the inverter 26 is input to the other end of 7b.

Here, as shown in FIG. 2, each OR gate 27a, 27b converts the halftone data signal outputted from the halftone data memory 15 and indicated by diagonal lines into the total blanking period (T un+T An insertion halftone data signal generation circuit is configured that generates an insertion halftone data signal nQInl that is included only in period va) and is at a high (H) level during other periods.

Each bit signal no, nl of the 2-bit inserted halftone data signal output from each OR gate 27a, 27b is input to the remaining input terminal of each AND circuit 19a, 19b.

Digital corrected video signal p output from each AND circuit 19a, 19b. , pl are each transistor 28a, 2
8b converts it into an analog signal, and resistors 29a and 29b
The signals are waveform-synthesized into one corrected video signal p by an adder circuit 30 consisting of an operational amplifier, which is then applied to the cathode of the CRT display tube 12 via an output transistor 31 and a video amplifier (not shown).

Next, the operation of the peripheral display circuit of the CRT display screen constructed as described above will be explained using the time chart shown in FIG.

That is, the normal video signal a output from the parallel/serial converter 17 is combined with the total blanking period signal j at the OR gate 18 to form a composite video signal d. Therefore, each blanking period THB+T' of the original video signal a
ve becomes H level.

Further, the output signal i of the exclusive OR circuit 24 is at H level only during each non-display period T corresponding to the vertical non-display area 2a, and the output signal i of the AND gate 21 is at H level only during the non-display period T corresponding to the vertical non-display area 2a, and the output signal i of the AND gate 21 is is at H level only during each non-display period TFL corresponding to the horizontal non-display area 2a. Furthermore, the inverted total blanking signal of the inverter 26 has a blanking period T. All signals other than B+TVB are at H level. Therefore, the output signal m of the OR gate 23 is generated during the vertical retrace period Tc and the vertical blanking period T
Only each horizontal retrace period TB other than VB is at L level.

Furthermore, a forced halftone data signal n is output from each OR gate 27a, 27b. +nl includes a halftone data signal only in each blanking period TIIB+TVB, and is at H level in the other blanking periods.

Therefore, each of these signals d, m, no (or nl)
The corrected video signal por pr
, or each corrected video signal p. .

In the corrected video signal p obtained by waveform synthesis of pl, when compared with the original video signal a in FIG. 3, as shown in the figure,
This means that the halftone data signal indicated by diagonal lines is inserted into the horizontal non-display period T and the vertical non-display period TP.

Further, the data signal during the display period TsD of the composite video signal d is transmitted to both transistors 28a.

28b, and are added by an adder circuit 30 to approximately double the signal level. However, for the halftone data signal in each non-display period T, , T, if the video data is set to [01], one of the AND circuits 19a will not be established in the period T 11 + T F. The signal level of the halftone data signal portion of the corrected video signal p output from the adder circuit 30 is approximately half the signal level of the data signal portion.

Therefore, when this corrected video signal p is displayed on the CRT display tube 12, in the non-display area 2a at the periphery of the display screen 2, plain data is displayed with a halftone luminance that is about half the luminance of the display area 2b. is displayed.

Therefore, even if the edge of the first character or the last character of each line touches the non-display area 2a, the edge of the character will not appear blurred as in the conventional case.

Therefore, even if characters or figures are displayed on the display area 2b, they can be read immediately.

Furthermore, in order to change the brightness of the plain halftone data displayed in the non-display area 2a, the halftone data set in the halftone data memory 15 may be changed to [101]. That is, the AND circuit 19b no longer holds true, and the resistor 2
Since the resistance values of 9a and 29b are different from each other, the adder circuit 3
The output signal level of 0 will be different from the previous signal level. Therefore, the level of the halftone data signal in the corrected video signal p changes, and as a result, the brightness of the plain halftone data displayed in the non-display area 2a changes.

Note that the present invention is not limited to the embodiments described above. In the embodiment, 2-bit halftone data is set in the middle data memory 15, but 3-bit or more halftone data is set, and (or game) 27 a, 27
b, AND circuit 19a.

By increasing the number of transistors 19b1 and transistors 28a and 28b, it is possible to increase the number of gradations of plain halftone data displayed in the non-display area 2a.

[Effects of the Invention] As explained above, according to the peripheral area display circuit of the CRT display screen of the present invention, the peripheral area of the display screen is displayed using the horizontal and vertical brightening signals, each blanking signal, and the halftone data memory. The formed non-display area is displayed with plain halftone data.

Therefore, the leading or final character of a line can be clearly recognized, and the screen can be made very easy for the observer to view.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing a peripheral display circuit of a CRT display screen according to an embodiment of the present invention, FIG. 2 is a time chart showing the operation of the same embodiment circuit, and FIG. 3 is a circuit diagram showing a conventional CRT display screen. 4 and 5 are time charts showing signal waveforms for displaying character data on a conventional CRT display screen. 2...display screen, 2a...non-display area, 2b...
Display area, 11...CRT control unit, 12...CRT
Display tube, 14... Code buffer, 15... Halftone data memory, 19a, 1.9b... AND circuit, 2
0...Exclusive OR circuit (horizontal non-display period detection circuit)
, 24... Exclusive OR circuit (vertical non-display period detection circuit), 25... OR gate (total blanking period detection circuit), 27a, 27b... OR gate (inserted halftone data signal generation circuit), 30...Addition circuit, a...
- Video signal, b...Horizontal synchronization signal, C...Vertical synchronization signal, e...Horizontal blanking signal, g...Vertical blanking signal, p...Corrected video signal.

Claims (1)

[Claims] a horizontal non-display period detection circuit (20) that detects a horizontal non-display period consisting of an exclusive OR period of a horizontal retrace period in a horizontal synchronization signal and a horizontal blanking period of a video signal;
a vertical non-display period detection circuit (24) for detecting a vertical non-display period consisting of an exclusive OR period of a vertical retrace period in a vertical synchronization signal and a vertical blanking period of the video signal;
, a total blanking period detection circuit (25) for detecting a total blanking period consisting of the OR period of each blanking period, a halftone data memory (15) for storing plain halftone data, and a halftone data memory (15) for storing blank halftone data; an insertion halftone data signal that outputs a logical sum signal of the halftone data signal output from the tone data memory and an inverted signal of the total blanking period signal output from the total blanking period detection circuit as an insertion halftone data signal; A generation circuit (27a, 27b),
An AND circuit that outputs an AND signal of the insertion halftone data signal output from the insertion halftone data signal generation circuit, the OR period signal of each of the detected non-display periods, and the video signal as a corrected video signal. (19a, 19b) A peripheral display circuit for a CRT display screen.