JPH0385974A - Moving picture recording control system - Google Patents

Abstract

PURPOSE:To attain reproduction or reverse feed reproduction from an optional position by applying inter-frame coding to every other frame in the forward direction with respect to a reference frame and to every other frame in the reverse direction and recording the result to a picture recording section. CONSTITUTION:A coding section 2 applies in-frame coding to moving picture signals of reference frames 1, 6, 11 and applies inter-frame coding to moving picture signals of frames 3, 5, 8, 10 at an interval of a frame in the forward direction from the reference frames 1, 6 and to moving picture signals of frames 4, 2 at an interval of a frame in the reverse direction from the reference frame 6. Thus, the frame sequence of the coded signals fed to a picture recording section 3 is expressed as 1, 3, 5, 6, 2, 8, 4, 10, 11,.... Since the moving picture signals are subject to compression coding in this way and then recorded, fast feed reproduction and reverse feed reproduction from an optional position are attained.

Description

[Detailed Description of the Invention] [Summary] Regarding a video recording control method that records a video signal by performing intra-frame encoding and inter-frame encoding, the video signal is compressed and encoded and recorded, and fast-forward playback is performed from an arbitrary position. The purpose of the present invention is to provide a frame memory that stores input video signals for a plurality of frames, and a video signal from the frame memory and the input video signal to perform intra-frame encoding or frame encoding. It is equipped with an encoding section that performs inter-encoding and an image recording section that records the encoded signal from the encoding section, and each predetermined number of frames is used as a reference frame, and the moving image signal of the reference frame is used as the encoder. The encoding unit performs intra-frame encoding, and the encoding unit performs inter-frame encoding on the moving image signals of every other frame in the forward and reverse directions from the reference frame, and the video signals are sent to the image recording unit. configured to record.

[Industrial Field of Application] The present invention relates to a moving image recording control method for recording a moving image signal by intra-frame encoding and inter-frame encoding.

Since a moving image signal has a very large amount of information, it is possible to reduce the recording capacity by performing band compression and recording. Various methods have already been proposed for such band compression, similar to band compression in video signal transmission methods. Furthermore, when a moving image signal is recorded, it is desired that its contents be easily searchable.

(Prior art) The NTSC system, which is the standard television system, has 5 scanning lines.
25 lines, frame frequency 30Hz, horizontal frequency 15.7
5 KHz, and the PAL system, which is the standard method in continental Europe such as West Germany and the United Kingdom, has 625 scanning lines.
Frame frequency 25Hz, horizontal frequency 15.625KH
It is z. Furthermore, in recent high-definition television systems, the number of scanning lines has almost doubled, and the bandwidth has also more than doubled.

Such an analog recording system for moving image signals based on the television system is already known as a video tape device or a video disc device. It is also known to convert analog video signals to digital signals and record them, but simply converting analog video signals to digital signals and recording would result in a very large amount of recorded information, so band compression is performed. It is suggested that it be recorded.

Band compression means for video signals include, for example, intra-frame encoding using one-dimensional or two-dimensional correlation of frames, inter-frame encoding using inter-frame correlation, and orthogonal encoding such as Hadamard transform and discrete cosine transform. Transform coding based on transform is known. Also known are methods that perform band compression by combining intraframe coding and interframe coding, and methods that perform band compression by combining transform coding and interframe coding. Such band compression means can reduce the amount of recorded information.

[Problems to be Solved by the Invention] As described above, when a moving image signal is band-compressed and recorded, the amount of recorded information can be significantly reduced by using interframe coding. When performing band compression by interframe encoding in this way, interframe encoding is performed using the first frame as a reference frame, so even when performing playback processing, reading starts from the first frame and interframe decoding is performed. This will result in a transformation. Therefore, there was a drawback that the reproduction process could not be performed from any arbitrary position.

In addition, when performing reverse playback, the playback process is performed by returning to the first frame, and the interframe code is reversed from the reverse playback start position to perform reverse playback. was not possible.

Furthermore, when performing fast-forward playback, the speed is limited by the interframe decoding processing speed, and therefore, there is a drawback that high-speed playback processing for searches and the like is difficult.

An object of the present invention is to compress and encode a moving image signal and record it, thereby making it possible to perform fast forward playback or reverse playback from any position.

[Means for Solving the Problems] The moving image recording control method of the present invention performs intra-frame encoding for every predetermined number of frames, and enables forward and reverse playback at the same speed. This will be explained with reference to FIG.

A frame memory 1 that stores input video signals for a plurality of frames; an encoding unit 2 that switches the video and input video signals from the frame memory 1 and performs intra-frame rod-curving or interframe encoding; and an image recording section 3 for recording the encoded signal from the encoding section 2, each frame of a predetermined number of frames is used as a reference frame, and the video signal of this reference frame is intra-frame encoded in the encoding section 2. ,
Regarding the frames between the reference frames, the encoding unit 2 performs interframe encoding on the moving image signals of every other frame in the forward and reverse directions from the reference frame, and generates an intraframe encoded signal and an interframe code. The signal and the image recording section 3
shall be recorded.

[Effect]

For example, if frames 1, 6, 11, . . . are reference frames, the encoding unit 2 encodes these reference frames 1, 6, .
11 video signals are intraframe encoded, video signals of every other frame 3.5 in the forward direction from the reference frame 1 are interframe encoded, and video signals of every other frame 8.5 in the forward direction from the reference frame 6 are encoded. 10 moving picture signals are interframe coded, and moving picture signals of every other frame 4.2 are interframe coded in the reverse direction from the reference frame 6. Therefore, the frame order of the encoded signals applied to the image recording section 3 is 1, 3, 5, 6, 2, 84, 10, 11, .
...becomes...

Further, the frame memory 1 is for storing moving image signals of frames when the moving image signals of every other frame are interframe encoded in the reverse direction, and the image recording section 3 is for storing moving image signals of frames in the case of interframe encoding of moving image signals of every other frame in the reverse direction. memory.

Configurations using various recording media such as magnetic disks and optical disks can be used.

〔Example〕

Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 2 is a block diagram of an embodiment of the present invention, where 11 is 3
Frame memory (3F) that temporarily stores input image signals for one frame period, 12 a frame memory (7F) that temporarily stores input image signals for 7 frame periods, 13 a subtracter, and 14 a quantizer. 15 is an adder; 16 is a delay circuit (DL) for delaying one pixel or one scanning line; 17.
18 is a frame memory (FM), 19 is a variable length encoder, 20 is an image recording unit, 21 is a frame memory (4F) that temporarily stores a moving image signal for a period of 4 frames, and 22 is a 7
A frame memory (7F) for temporarily storing moving image signals for a frame period, 23 is an adder, 24 is for one pixel or one
Delay circuit (DL) that delays scanning line, 25.26 is frame memory (FM), 27 is variable length decoder, SWI
~SW4 is a switch circuit.

The frame memories 11 and 12 constitute the frame memory 1 in FIG. 1, and the switch circuits SWI and SW2
and subtracter 13, quantizer 14, adder 15, and delay circuit 1
6, a frame memory 17, 18, and a variable length encoder 19 constitute the encoding section 2 in FIG. The switch circuits SWI to SW4 are controlled by a control section (not shown), and when the switch circuit SW2 is switched to A, intra-frame encoding is performed on the moving image signal of the reference frame, B, When switched to C,
Interframe encoding is performed on moving image signals of other frames. Furthermore, when the switch circuit SW3 is switched to A, intra-frame decoding of the encoded signal of the reference frame is performed, and when switched to B and C, inter-frame decoding of the encoded signal of other frames is performed. be exposed.

This example shows a case where one cycle of encoding and decoding is composed of five frames, the video signal of the reference frame is intra-frame encoded, and the video signals of other frames are encoded every other frame in the forward direction. Interframe coding is performed every other frame in the opposite direction, and the coded signal that has been intraframe coded or interframe coded is variable length coded by a variable length encoder 19, and then transferred to a semiconductor integrated circuit. The image is recorded in an image recording section 20 consisting of a circuit memory, a magnetic disk, an optical disk, etc. When this recorded content is read, the variable length decoder 2
7, and the intraframe encoded signal is sent to the delay circuit 2.
4, the interframe coded signal is interframe decoded using the frame memory 25.26, and the frame memory 21.22 is used to obtain the output video signal in the original order.

FIG. 3 is an explanatory diagram of the operation of the embodiment of the present invention, where (a) is the input moving image signal a, (b), and (C) are the switch circuit S.
Switching state of Wl and SW2, (d) is switch circuit SWl
, (e) is the switching output signal e of the switch circuit SW2, (f) is the quantized output signal f, (g) is the switching state of the switch circuit SW3, and (h) is the switching output signal e of the switch circuit SW2.
3 switching output signal h, (i) is the output signal i of the adder 23
, (j) shows the switching state of the switch circuit SW4, and (k) shows the switching output signal of the switch circuit SW4.

Also, 1-1, 12, ... in (a) indicate frame numbers, and (d), (e), (f), (h), (
t) and (k) also indicate frames corresponding to this frame number. This shows the case where the input moving image signal a has one period of 5 frames, and the reference frame 1-1.2
-13-1. ..., the switch circuit SW
1, SW2 are switched and connected to A, respectively, as shown in (b) and (c). Therefore, the input moving image signal a is input to the subtracter 13 as it is, and the delay circuit 16
Switch circuit SW2 delayed by a pixel or one scanning line
The switching output signal e of 1-1 and e is input to the subtracter 13.
The difference between pixels within the same frame or the difference between scanning lines, such as l-1, 2-1 and C2-1°, is calculated by the subtracter 13.
The quantized output signal r is outputted from fl-1, f2-1 . f3-1.・・・
. This is variable-length encoded by the variable-length encoder 19 and added to the image recording section 20.

Reference frame 1-1.1-1.3-1. When the forward direction frame is 1-2.2-2.3-2°..., switch circuit SW1 is B1 switch + circuit Sw2 is C
The moving image signal delayed by three frames from the frame memory 11 becomes the switching output signal d, and the signal from the frame memory 17 one frame before becomes the switching output signal e. For example, at frame 2-2, the moving image signal of frame 1-4 three frames before from the frame memory 11 becomes the switching output signal d of the switch circuit SWI,
Further, the signal of the previous frame 2-1 from the frame memory 17 becomes the switching output signal e of the switch circuit SW2. Therefore,
Frame 1 placed in the opposite direction from reference frame 2-1
-4 moving image signal is interframe encoded, and the quantized output signal f becomes rl-4 as shown in (f).

Next frame 1-3. 2-3.3-3. When..., switch circuit SW l is A, switch circuit SW
2 is switched and connected to B, the input moving image signal a is input to the subtracter 13 via the switch circuit SWI, and the signal from the frame memory 17.18 two frames before becomes the switching output signal e. For example, in the case of frame 2-3, the moving image signal of frame 2-3 becomes the switching output signal d of the switch circuit SWI, and the signal e2-1 of two frames before from the frame memory 17.18 is the switching output of the switch circuit SW2. Becomes a signal snake. Therefore, inter-frame encoding is performed for every other frame 2-3 from the reference frame 2-1 in the forward direction, and the quantized output signal r becomes 12-3 as shown in (f). Become.

Next frame 1-4.2-4.3-4. ..., switch circuit SWI is C1 switch circuit SW2 is B
The moving image signal that is switched and connected to the frame memory 12 and delayed by seven frames becomes the switching output signal d, and the signal from the frame memory 18 two frames before becomes the switching output signal e. For example, at frame 2-4, the moving image signal of frame 1-2 from the frame memory 12 becomes the switching output signal d of the switch circuit SWI, and the frame memory 1
The signal e2-1 from 2 frames ago from 8 is the switch circuit S.
This becomes the switching output signal e of W2. Therefore frames 1-4
Inter-frame encoding of the moving image signals of every other frame 1-2 is performed in the reverse direction from then on.

Next frame 1-5.2-5.3-5. ..., switch circuit SW1 is A, switch circuit SW2 is B
The input moving image signal a becomes the switching output signal d, and the signal from the frame memory 18 two frames before becomes the switching output signal e.

For example, at frame 2-5, the moving image signal of frame 25 becomes the switching output signal d of the switch circuit SWI,
Frame 2-3 two frames before from frame memory 18
The signal e2-3 is the switching output signal e of the switch circuit SW2.
becomes. Therefore, interframe encoding of the moving image signal of every other frame 25 is performed in the forward direction from frames 2-3.

In the same way, intraframe encoding of the reference frame,
Since interframe encoding is performed for every other frame in the forward direction and every other frame in the reverse direction, the quantized output signal f is (
f), for example, r2-1. fl-4,
f2-3. The sequence is fl-2, f2-5, variable length encoded by the variable length encoder 19, further compressed in information amount, and recorded in the image recording unit 20.

When forward playback is performed, the encoded signal read from the image recording unit 20 is decoded into a quantized output signal f by the variable length decoder 27, and a moving image signal subjected to intra-frame decoding or inter-frame decoding is generated. i is output as shown in (i). In that case, the switch circuit SW3 is switched and the switch circuit SW4 is switched as shown in (b), and the adder 23
The switching output signal from the switch circuit SW3 is applied as shown in FIG.

For example, reference frame 1-1 2-1.3-1,...
The encoded signal that has been intra-frame encoded is stored in the image recording unit 20.
When the signal is read from the switch circuit SW3, the switch circuit SW3 is switched to A, and the switch circuit SW4 is switched to C. Therefore, since the delay circuit 24 is connected by the switch circuit SW3, the signal h delayed by one pixel or l scanning line in the same frame.
1-1, h2-1. h3-1. ...is the adder 23
In addition, intra-frame decoding is performed, and decoded output signals i (1-1, 2-1, 3-1,...) are output as shown in (i) and stored in the frame memory 25. Added. Further, the moving image signal delayed by seven frames from the frame memory 22 becomes the switching output signal of the switch circuit SW4.

When the next encoded signal of the reference frame is read out, the switch circuit SW3 is switched to C, the switch circuit SW4 is switched to B, and the adder 23 receives the decoded output signal of the previous frame from the frame memory 25 from the switch circuit. For example, frames 1-
The variable-length decoded signal of frame 2-1 and the intra-frame decoded signal of frame 2-1 are added, and interframe decoding of every other frame is performed in the reverse direction from the reference frame. A decoded output signal i delayed by four frames from the switch circuit SW4 is output as an output moving image signal.

When the next encoded signal is read out, the switch circuit SW3 is switched to B, the switch circuit SW4 is switched to C, and the adder 2
3, the decoded output signal of two frames before from the frame memory 26 is added via the switch circuit SW3, so for example, the variable length decoded signal of frame 2-3 and the intra-frame decoded signal of frame 2-1 signal is added, so every other frame 2-3 in the forward direction from the reference frame
interframe decoding will be performed. Then, the decoded output signal i delayed by seven frames from the frame memory 22 is outputted as an output moving image signal from the switch circuit SW4.

When the next encoded signal is read out, the switch circuit SW3 is switched to B, the switch circuit SW4 is switched to A, and the adder 2
3, the decoded output signal of two frames before from the frame memory 26 is applied via the switch circuit SW3, and for example, the variable length decoded signal of frame 1-2 and the variable length decoded signal of frame 1-2 are applied.
4 interframe decoded signals are added, so interframe decoding of every other frame 1-2 is performed in the reverse direction from frame 1-4. And switch circuit SW4
is output as an output moving image signal.

When the next code signal is read out, the switch circuit SW3 switches to B
1 switch circuit SW4 is switch-connected to C, and adder 23
The decoded output signal of two frames before from the frame memory 26 is applied to the frame memory 26 via the switch circuit SW3.
Variable length decoded signal of frame 2-5 and frame 2-3
Since the interframe decoded signal is added to the interframe decoded signal, interframe decoding is performed for every other frame 2-5 in the forward direction from frame 2-3, and the decoded signal delayed by 7 frames from the frame memory 22 is The output signal i is output from the switch circuit SW4 as an output moving image signal.

By repeating the above-described operations, forward playback is performed, and the output moving image signal follows the order of the input moving image signal a, as shown in (k).

In the case of reverse playback, the order of the interframe decoded signals of every other frame in the forward direction and every other frame in the reverse direction is based on the intraframe decoded signal of the reference frame.
This is opposite to the case of the forward playback described above, and by inverting the sign and adding it to the adder 23, the backward playback can be started from any reference frame.

In the case of forward fast-forward reproduction, it is sufficient to read out only the reference frame and perform intra-frame decoding, and the switch circuit SW3 is connected to A1, and the switch circuit SW4 is connected to C or A.

Similarly, in the case of reverse fast-forward playback, it is sufficient to read out only the reference frame and perform intra-frame decoding.

Furthermore, when recording the intra-frame encoded signal of the reference frame and the inter-frame encoded signal of other frames, it is possible to distinguish them by a frame synchronization signal pattern. In that case, the frame synchronization signal is detected and identified during playback, and the switch circuit SW3. A configuration that controls SW4 would suffice.

Further, the present invention is not limited to the above-described embodiments. For example, one cycle is not limited to five frames, but can be composed of an odd number of frames such as seven frames or nine frames.

In that case, the number of frames delayed by the frame memory to perform interframe encoding of every other frame in the reverse direction increases, and the number of accumulated frames also increases, corresponding to the number of frames in one cycle. , the configurations of the frame memories 11, 12.1718 of the recording section and the frame memories 25, 26.degree. 21.22 of the reproducing section are selected.

It is also possible to omit the variable length encoder 19, and if omitted, the variable length decoder 27 will be omitted. Furthermore, instead of the variable length encoder 19, it is also possible to provide an encoder that performs other transform encoding or the like. It is also possible to share the frame memory of the recording section and the frame memory of the reproduction section.

〔Effect of the invention〕

As explained above, in the present invention, in the encoding unit 2,
A reference frame is intra-frame encoded, and every other frame in the forward direction and every other frame in the reverse direction is inter-frame encoded and recorded in the image recording unit 3, Although the processing for forward playback and reverse playback is almost the same, and even though band compression recording is performed, there is a reference frame within several frames from the desired position. It is possible to start playback from the position , and high-speed playback is possible because forward and reverse fast-forward playback only requires playback processing for the reference frame.

Therefore, there is an advantage that searching for moving images can be facilitated with an economical configuration.

[Brief explanation of drawings]

FIG. 1 is an explanatory diagram of the principle of the present invention, FIG. 2 is a block diagram of an embodiment of the invention, and FIG. 3 is an explanatory diagram of the operation of the embodiment of the invention. 1 is a frame memory, 2 is an encoding section, and 3 is an image recording section.

Claims (1)

[Scope of Claims] A frame memory (1) that stores an input video signal for a plurality of frames, and a video signal from the frame memory (1) and the input video signal that are switched to perform intra-frame encoding or inter-frame encoding. It comprises an encoding section (2) that performs encoding, and an image recording section (3) that records the encoded signal from the encoding section (2), and each predetermined number of frames is used as a reference frame, and the reference frame is set as a reference frame. The encoding unit (2) performs intraframe encoding on the video signal of each frame, and encodes the video signal of every other frame in the forward and reverse directions from the reference frame in the encoding unit (2). A moving image recording control method characterized in that interframe encoding is performed in the video recording section (3).