JPH0385947A - Fsk signal demodulator - Google Patents

Abstract

PURPOSE:To obtain a signal demodulator formed easily with small size by using a period detecting means to count the period of an FSK(frequency shift keying) signal and compensating a noise component mixed in the FSK signal. CONSTITUTION:The period of an FSK signal is counted by a counter circuit 11 via a waveform shaping circuit 10, and when a counted value (t) belongs to the range of t1-td<=t<=t1+td, a deciding logic circuit 12 outputs the signal of logic '1' and a deciding logic circuit 13 outputs the signal of logic '0'. The output signal is fed to a flip-flop circuit 14 and the signal demodulated once by the flip-flop circuit 14 is given to a shift register 15 and a discrimination circuit 16, in which a final demodulation signal is generated by the statistic processing including the past data. Thus, the number of components is considerably reduced and miniaturization is attained.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention uses the FSK (Frequency Shift Keying) method, which encodes information by assigning predetermined frequencies to two types of information called marks and spaces. The present invention relates to a demodulator for demodulating a modulated signal into a signal represented by original marks and spaces.

[Prior art] For example, as shown in FIG.
"Digital data (mark) of frequency fl, logical value"
0” digital data (space) at frequency f2 (
However, it is a type of frequency modulation method expressed by FM waves (f1≠f2).

Conventionally, a signal modulated by this FSK modulation (hereinafter referred to as FSK modulation)
In order to demodulate a high-frequency FSK signal into the original signal represented by marks and spaces, a wireless receiver uses a hetero gain to convert the high-frequency FSK signal into two types of low-frequency signals with different frequencies. It has been common practice to convert the frequency into FSK signals and perform mark and space differential demodulation on these signals.

For example, in the conventional example demodulator shown in FIG. , 2 that are continuously connected to the rectifier circuits 3 and 2 are added together by a voltage addition circuit 5, and the output signal S3 of the voltage addition circuit 5 is compared with a preset reference voltage by a comparator 6. Then, marks and spaces are distinguished from each other based on their magnitude relationship with the reference voltage.

In addition, as shown in FIG. 6, a phase comparison circuit 7 that compares the phase of the FSK signal 5l)l and the signal from the voltage controlled oscillation circuit, a low-pass filter 8, and an oscillation proportional to the output voltage of the low-pass filter Demodulation is achieved by configuring a phase-locked loop that is equipped with a voltage-controlled oscillation circuit 9 whose frequency changes and performs feedback so that the frequency of the human-powered FSK signal and the oscillation frequency of the voltage-controlled oscillation circuit are always kept the same. Signal S
Demodulators that generate O are known.

[Problems to be Solved by the Invention] However, since such conventional FSK signal demodulators use analog circuit technology, they require inductance for the resonant circuit and operational amplifier for the analog filter. The phase-locked loop method shown in Figure 6 has drawbacks such as a complicated circuit configuration, an increase in the number of parts, and manufacturing difficulties unique to analog circuits. The disadvantage is that the demodulation performance of the included FSK signal is extremely low.

The present invention has been made in view of these problems, and an object of the present invention is to provide an FSK signal demodulator that is easy to manufacture and extremely compact by applying digital circuit technology.

[Means for Solving the Problems] In order to achieve such an object, the present invention modulates the time series signals of marks and spaces into two types of signals having different frequencies, and converts the FSK signal into the original time series signal. F to demodulate the signal
In the SK signal demodulator, the period of the FSK signal is counted,
If the count value is within a predetermined range centered on a preset reference count value, it will output "1", and if it is a value within a predetermined range centered on another reference count value, it will output "1". A period detection means that outputs "0" and re-outputs "1" or 0 that was output in the previous cycle if the count value is outside the two set ranges, and A determining means is provided which generates a signal corresponding to a mark or a space according to the number of "1"s and "0"s in the time-series signal in synchronization with each output of the signal from the period detecting means.

Furthermore, the demodulation principle of the present invention will be explained in detail based on FIG.

As shown in FIG. 4, it is assumed that an FSK signal consisting of an FM wave in which frequency f1 is assigned to the mark "l" and frequency f2 is assigned to the space "0" is demodulated.

First, F
Count the period of the SK signal. If the count value t is
As shown in FIG. 1, the reciprocal value tl of the frequency f1 (i.e., t
A predetermined range tl-td≦t centered on l=1/fl)
If ≦tl +td, a signal of “1” corresponding to the mark is output, and on the other hand, the count value t falls within a predetermined range t2 centered on the reciprocal value t2 of the frequency f2 (i.e., t2 = 1/f2). -td≦t≦t2 If +td, a “0” signal corresponding to the space is output. Furthermore, if the count value t does not belong to any of the above ranges, the same signal that was output in the previous cycle is output again.

The time-series signal of "1" and "0" outputted in this way has the form of a demodulated signal, but in the present invention, by further compensating for noise components mixed into the FSK signal during the transmission path etc. The aim is to improve demodulation accuracy.

That is, as shown by way of example in FIG. Regarding the output signal during a certain period T in the past including the signal,
Count the number of “l” and “O”, and if the number of “1#” is large, generate “1” corresponding to the mark, and “0”
If there are many spaces, "O" corresponding to a space is generated, and this finally generated "1" or "O" signal is used as a demodulated signal.

As an example, in FIG. 2, the number of "1" and "0" is detected for each of the past eight signals at the time points τ11τ2, τ3, etc. when the period detection means outputs the signal corresponding to the count value,
A specific example is shown in which the final demodulated signal is determined from the detection results.

Furthermore, if display means is provided to display the output signal of the period detection means, it is suitable for easily and correctly tuning the FSK signal.

Further, the counting results of the period detecting means are statistically classified and stored, and the reference counting values tl and t2 are set to the FS based on the statistical results.
A configuration that follows the K signal is suitable for providing an automatic tuning function.

[Function] Since the present invention having such a configuration can be realized only by digital circuit technology, the number of components such as capacitance elements, reactance elements, and resistors as in conventional FSK demodulators can be significantly reduced. This makes it possible to reduce the size, which is highly economical and allows for miniaturization. Furthermore, from a circuit perspective, it is suitable for integrated circuits using semiconductor manufacturing technology, so it can be miniaturized by being integrated into a communication IC, microprocessor, etc., or realized by a custom IC.

[Example,] An embodiment of the present invention will be described below with reference to the drawings.

First, the configuration will be explained based on FIG. 3. 10 is a waveform shaping circuit that clips the input FSK signal SIN to a predetermined amplitude and performs waveform shaping, and 11 counts the period of the output signal of the waveform shaping circuit 10. This is a counting circuit, and a digital counter with an appropriate number of bits is applied. This circuit also supplies the flip-flop circuit 14 and the shift register 15 with a clock signal indicating the timing of the end of counting.

12.13 is a judgment logic circuit consisting of a digital comparator, etc., and the judgment logic circuit 12 is configured so that the count value t output from the counting circuit 11 is tt-, td and t as explained in FIG.
When belonging to the range l +td, a signal with a logic value of "1" is output, and otherwise, a signal with a logic value of "0" is output. On the other hand, the judgment logic circuit 13 outputs a signal of logical value "1" when the count value t outputted from the counting circuit 11 falls within the range of t2-td and t2 +td explained in FIG. At this time, the logic value “0” is output.

Reference numeral 14 denotes a flip-flop circuit (RS flip-flop in this embodiment) which operates synchronously every time the counting in the counting circuit 11 ends, and the output signal of the judgment logic circuit 12 is connected to the set terminal, and the output signal of the judgment logic circuit 13 is connected to the set terminal. A signal is supplied to the reset terminal, and as a result of counting, the judgment logic circuit 12,1
．． 3. When a judgment is made, the previous judgment result is stored.

15 inputs the output signal from the flip-flop circuit 14 in synchronization with counting, and at the same time holds the past human input signal by bit-shifting it.

16 is a discrimination circuit, which counts the number of logic values "1" and "0" of all the bit data held in the shift register 15 in synchronization with the input of a new signal to the shift register 15; If the number of “1” is large, the logical value “1” representing the mark
" is output as the demodulated signal SO, and if the number of '0's is large, the logic value "0" representing a space is outputted as the demodulated signal SO. The shift register 15 receives the signal from the flip-flop circuit 14 at a predetermined period. Since the data is shifted by i bits in synchronization with the input signal and the oldest bit data is discarded, the past information for 8 or 16 cycles including the input signal is always held, and the discrimination circuit 16 uses this information. The bit data to be changed bit by bit is determined as follows.

Reference numeral 17 denotes a display circuit, and an internal light emitting element emits light according to the output level of the determination logic circuits 12 and 13.

Next, the operation of the demodulator having such a configuration will be explained.

After the FSK signal SIN is waveform-shaped by the waveform shaping circuit 10, the FSK signal SIN is waveform-shaped by the counting circuit 11. The periods are counted and the count value t is supplied to the decision logic circuit 12.13.

Then, when the count value t belongs to the range of tl-td≦t5tl+td, the discrimination logic circuit 12 outputs the logical value "
At the same time, the determination logic circuit 13 outputs a signal with a logic value of "0". When the count value t is in the range of t2 - td ≦t≦t2 + td, the judgment logic circuit 12 outputs a signal with a logic value of "0". “
At the same time, the judgment logic circuit 13 outputs a signal with a logic value of "1".If the count value does not belong to any setting range, both judgment logic circuits 12 and 13 output a signal with a logic value of "1". Both output signals with a logic value of “0”.

The output signal generated in this way is sent to the flip-flop circuit 1.
4 is applied to the set and reset terminals, the flip-flop circuit 14 outputs a signal with a logical value of "0" in both of the judgment logic circuits 12.1.3. The output signal will be output again.

The signal output from the flip-flop circuit 14 is input to an 8-bit or 16-bit shift register 15, and a discrimination circuit 16 detects the number of "1" and "0" in all output bit information of the shift register 15. If the number of '1's is large, the logical value '1' corresponding to the mark is sent to the demodulated signal S.
If the number of "0"s is large, a logical value "0" corresponding to the space is output as the demodulated signal SO.

Note that although the determination circuit 16 in this embodiment determines the demodulated signal SO by majority vote, other determination criteria may be applied.

As described above, according to this embodiment, the signal once demodulated by the flip-flop circuit 14 is further transferred to the shift register 15.
Since the final demodulated signal is generated by statistical processing including past data in the determination circuit 16, the FS
Highly accurate demodulation can be performed by removing noise components contained in the K signal SIN. Further, the tuning state can be detected by observing the blinking display on the display circuit 17.

Further, a circuit may be configured for each functional block of this embodiment, or a configuration may be adopted in which each function is replaced with processing of a computer program using an arithmetic device such as a microprocessor.

Furthermore, although not shown, the outputs of the judgment logic circuits 12 and 13 are classified and processed by a statistician, and the processing results are sent to the judgment logic circuit 1.
By returning to step 2.13 and automatically adjusting the count values tl and t2 of the determination criteria, a demodulator having an automatic adjustment function may be realized.

[Effects of the Invention] As explained above, according to the present invention, the FSK demodulator, which conventionally applied analog circuit technology, is constructed by applying digital technology, so that adjustment becomes easy, and The large number of capacitors, resistors, and actance elements characteristic of conventional analog technology can be reduced, making it possible to downsize the device, and is also highly economical.

Further, since digital technology is applied, it is possible to realize a highly functional and compact device by integrating it into an integrated circuit device containing a microcomputer or the like.

Furthermore, from the performance tests of the examples, it was confirmed that the demodulation method of the present invention can achieve demodulation performance equivalent to that of the conventional analog method.

Furthermore, to ensure more accurate demodulation, it is necessary to tune the frequency of the input FSK signal, but conventional demodulators require tuning from an expensive cathode ray oscilloscope (CRT) or multiple light emitting diodes and AD converters. This synchronization was performed using a complicated voltage peak value detection device, but by performing synchronization adjustment according to the output of the display circuit of the present invention, it can be easily done without using a complicated device like the conventional one. Synchronous adjustments can be made.

Overall, the present invention can provide a compact FSK signal demodulator that is highly functional and economical while maintaining conventional performance.

[Brief explanation of drawings]

(Figure 2) is a principle explanatory diagram for explaining the present invention in detail; Figure 3 is a block diagram showing the configuration of an embodiment of the present invention; Figure 4 is a diagram of the modulation and demodulation signals of the FSK system. An explanatory diagram showing the relationship; FIGS. 5 and 6 are conventional configuration explanatory diagrams showing the configuration of a conventional demodulator. Reference numerals in the figures: 10; waveform shaping circuit 11; counting circuit 12; judgment logic circuit 13; Judgment logic circuit 14; flip-flop circuit 15; shift register 16; discrimination circuit

Claims (4)

[Claims] (1) In an FSK signal demodulator that demodulates an FSK signal obtained by modulating mark and space time series signals into two types of signals with different frequencies into the original time series signal, counting the period of the FSK signal, If the count value is within a predetermined range centered around a certain reference count value set in advance, "1" is output, and even if the value is within a predetermined range centered around another reference count value. In this case, it outputs “0” and the above 2.
a cycle detection means that re-outputs the "1" or "0" output in the previous cycle if the count value is outside the set range of the set; 1. An FSK signal demodulator comprising: a determining means for determining whether a demodulated signal is a mark or a space based on the number of "1"s and "1s" of the signal outputted in the FSK signal demodulator. (2) The FSK signal demodulator according to claim (1), further comprising display means for displaying the tuning state by displaying the output signal outputted by the period detection means in accordance with the count value. FSK signal demodulator. (3) In the FSK signal demodulator according to claim (1), statistically processing the count value outputted by the period detection means,
An FSK signal demodulator, characterized in that it is provided with feedback means for performing feedback control so that the reference count value follows the frequency of the FSK signal in accordance with the statistical processing result. (4) The FSK signal demodulator according to any one of claims (1), (2), and (3), characterized in that processing of some or all of the means is performed by electronic calculation means. FSK signal demodulator.