JPH0385770A - Mon-volatile semiconductor memory - Google Patents

Abstract

PURPOSE:To increase operation speed, enable all memory cells to be erased collectively, uniformly, and positively, and reduce voltage used for writing by connecting a floating gate transistor and an enhancement type transistor in parallel for each memory cell. CONSTITUTION:Each floating gate 16 is placed so that it is shifted to the right and left (in the direction of extension of a control gate 17) or in zigzag. Namely, the floating gate 16 and the control gate 17 are overlapped in the upper direction at one part of the channel region of a memory cell 39, thus constituting a floating gate transistor 39a, and only the control gate 17 exists at the upper part of other parts of the channel region, thus constituting an enhancement type transistor 39b. Namely, the above two kinds of transistors are connected in parallel in some memory cells.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to a nonvolatile semiconductor memory having a nonvolatile memory cell in which data can be electrically erased and written.

(Prior Art) A ROM in which the stored contents of a memory cell can be electrically erased and rewritten is known as an EEPROM (Electrically Erasable Programmable ROM). This EEPROM is an ultraviolet quenching EFRO.
Due to the ease of use in which data can be erased using electrical signals while mounted on a board, there is a sudden increase in demand for use in various control applications, memory cards, and the like.

In particular, recently there has been a desire for a larger capacity EEPROM used for replacing data on floppy disks.

Figures 5 (a) to (C) are conventional NANs suitable for increasing capacity.
It shows the configuration of a memory cell array of a D-type EEPROM, and FIG. 5(a) is a pattern plan view thereof, and FIG.
5(b) is a sectional view taken along line AA' in FIG. 5(a), and FIG. 5(C) is a sectional view taken along line BB' in FIG. 5(a). In FIG. 5(a), 10 surrounded by branch lines indicates one N A N D bolting block. This N A N D Zt
As can be seen from Figure 5(b) of i-book block 10,
The other NAND basic blocks lined up in the left-right direction in FIG. 2B are field oxide films 12, 12 . It is divided by... The longitudinal section of the NAND basic block 10 is the fifth
It is clear from Figure (C). That is, especially in FIG. 5(C), 11 is a p-type silicon semiconductor substrate, and 13 is an n+
A common source region common to each basic block 10 made of a diffusion layer; 14 is a NAND basic block also made of an n+ diffusion layer; a drain region of 0; 15, 15 . . . . is a source na train region of each memory cell provided in NAND basic block] 0, each consisting of an n+ diffusion layer, 16
．． 16. ... are floating gates made of the first polysilicon layer, ]7゜17, ... are control gates made of the second polysilicon layer, respectively, and 18 is the floating gate made of the second polysilicon layer. polysilicon layer and a second
The first select gate 19 is configured by electrically connecting the polysilicon layer of the first layer and the polysilicon layer of the second layer. 20 is a pig line, 21 is a contact portion connecting the drain region] 4 and the data line 20, and 22 is a contact portion provided between the floating gate 16 and the substrate] 1. For example, I't' is a gate oxide film of about 100 layers, and 2'3 is a 70-layer gate oxide film provided between the gate 16 and the control case 117.
A gate insulating film with a thickness of about 300 Ωtl/l & 24 is an insulating oxide film 25 and 26 for the first and second select gates 1, 8, 19 and the substrate 1, respectively.
] is a keto oxide film with a thickness of, for example, about 40.8 mm. In particular, as can be seen from FIG. 5(c), each NANDJl! In this block 10, ten transistors (memory cells and select gate transistors) 31 to 40, which will be described in detail later, are formed. The I transistors 31-40 are turned on and off by gates 17-19 on each channel. However, whether the transistors 32 to 3 are on or off is regulated depending on whether they hold floating ketones, electrons, or holes.

Each of the floating gates 16 stores data "1" or "0" by retaining electrons or holes.

In addition, the above control game) 17, 17... is each N
For example, eight gates are provided in the AND basic block 10, and each gate is provided continuously so as to cover a plurality of floating gates 1616 placed directly on its side. That is, as can be seen particularly from FIGS. 5(a) and 5(b), the floating gates 16, 16 .・
... (width in the vertical direction in FIG. 5(a)) is the control gate 17.17. The width of the floating gates 16, 16. ... length (5th
The length in the left-right direction in Figure (a) is shorter than the width of each NAND basic block. Then, the memory cell array has the above-mentioned NAND, and M blocks 10 are arranged in the fifth block.
In Figure (a), they are arranged in a matrix in the upper, lower, and left ear directions.

Each of the above NAND block Japan blocks',';' 1dl
illll1 sweetfish is shown in FIG. In Figure 6, two NAND basic blocks 10 and 10 are shown on the left and right. As can be seen from the figure, the equivalent circuit of each basic block ] 0 is the source 13 and the data 20 (DLL, DL
2), a select gate transistor 31,
It is assumed that eight memory cells 32 to 39 and a select gate transistor 40 are connected in series.

Transistor 31.40 has select gate signal 5G
ISG2 is manually operated, and word lines WLI to WL8 are connected to memory cells '32 to three control gates]7.

The erasing and writing operations of data stored in each of the eight memory cells 32 to 39 each consisting of a floating gate 1-1 transistor will be described below.

Of data? As shown in FIG. 8(a), the draining is performed by applying a high voltage, for example, 15V, to the control gate 17 and bringing both the source 15 and drain 15 to the ground potential of OV. .

By applying a high voltage to the control gate 17, the control gate 17 and the floating gate 16 are electrostatically coupled, thereby increasing the potential of the floating gate 16 and increasing the potential of the floating gate 16 through the gate oxide film 22. Electrons are injected from the drain 15 into the floating gate]6. This is called the disappearing state,
The stored data at this time is assumed to be at the "1" level. At this time, the threshold voltage of the memory cell is about 2 to 3 V, as shown in the characteristic diagram of FIG.

The data is written as shown in Figure 8(b).
This is done by bringing the control gate 17 to OV, leaving the source 15 in an open state, and applying a high voltage to the drain 15. At this time, electrons are emitted from the floating gate 16 to the drain 15, and the threshold voltage of the memory cell becomes approximately -5■ as shown in the characteristic diagram of FIG. The stored data at this time is defined as "0" level.

Next, we will explain the NAND story in Figures 6 and 5 of the Second Era by placing the original Japanese Zoroku 10 in Table 1.

To erase data, set the data lines DL'l and DL2 to 0VSS.
GI to 5VSSG2 to 15V1 word lines WLI to WL8
This is done by setting all the voltages to 15V. In this state, all the drains and sources of the memory cells 32 to 39 become OV, and all the memory cells 32 to 39
data will be deleted all at once.

Data is written to the select gate transistor 31
The process is selectively performed sequentially starting from the memory cell 32 (cell 1) closest to the memory cell 32 (cell 1). First, to write to cell 32, set SGI to OV1 data line DLI to 20VSDL2 to lQV, SG
Set 2 to 2υV.

Next, the word line WLI is set to OV, and the other word lines WL2 to
By setting all WL8 to 20V, memory cell 32 is selected and writing is performed. The threshold voltage of a memory cell that has been erased in advance is approximately 3V, but memory cells 33 to 33 to which a high voltage is applied in the written state
The threshold voltages of the three cells (cells 2 to 8) are approximately 5V when considering the substrate effect. Therefore, at the drain of the memory cell 32, (gate voltage of memory cell 33>-</r4
A voltage of 15V (threshold voltage of the removed memory cell) - (20V5V) is applied, and a gate oxide film (
Electrons are emitted from the floating gate to the drain through the reference numeral 22) in FIG. In other words, data is written into the memory cell 32.

Writing to the next memory cell 33 is performed by setting the word lines WLI and WL2 to 0V and setting all the remaining word lines WL3 to WL8 to 20V. Similarly, writing up to memory cell 39 is performed sequentially with voltages determined as shown in Table 1.

If writing is not to be performed on the selected memory cell, that is, if the "]" level data is to be left as it is, OV may be applied to the data line DLI instead of 20V. In this case, no voltage is applied between the floating gate and the drain, and no writing is performed.

In this way, data writing to the eight memory cells is performed in order from the source side memory cell 32. The reason for this is that if writing is not performed in this order, when writing to a certain cell, if a high voltage (20V) is applied to the word line in other cells that have already been written, j( This is because the data enters an erased state where a voltage of OV is applied to the drain, and the other cells mentioned above will perform the ritual.By performing the process in the order described above, such a state can be avoided and the data will not be erased. be able to.

Also, writing to block 10 on the data line DLI side,
The amount of loss includes write n and lf for other data lines DL2.
Approximately 10 V, which is an intermediate voltage between This is to prevent erroneous writing and erroneous checking of the memory cells connected to this data line DL2.

In addition, one NANDJA book block Bob block, when writing is being done, that block and vertical (Figure 5 (
In other NAND basic blocks connected in the vertical direction (a), SG2 is set to OV1, and the quad lines WLI to WL8 are set to OV to prevent erroneous writing and writing.

The data read operation from the NAND basic block is performed as follows. For example, in the '66 diagram, when selecting one memory cell 32 in the NANDM main block connected to the data line DLl to read out a
As shown in the table, IV for DLI, 5 for SGI and SG2.
■, OV to the selected word line WLI, other word lines W
5V is applied to each of L'' to WL8. Also, the unselected data line DL2 is in a floating state and is approximately O due to l.
It becomes V. When the data stored in the selected memory cell 32 is at the "1" level (threshold voltage is +3V), the control gate voltage is oV, so the cell is in an off state. Therefore, in the selected NAND basic block 10, no current flows between the data line DL,1 and the ground potential. Therefore, this "1" level data is sensed by a sense amplifier (not shown) connected to this data line DLI. On the other hand, the stored data of the selected memory cell 32 is “0”.
" level (threshold voltage - 5V), it is in the on state even if the control gate voltage is OV. At this time, the control gate voltage of the other memory cells 33 to 39 is
Since the memory cells 33 to '39 are in the ON state regardless of the stored data, a current flows between the data line DLI and the ground potential in this hydraulic block ]O. Therefore, at this time, the sense amplifier is “0”.
″ level data is sensed.

(Problems to be Solved by the Invention) In the conventional memory using the NAND basic block as described above, memory cells can be arranged at the pitch of the word line (control gate 17), and the memory cells can be arranged at the pitch of the word line (control gate 17). The contact portion 21 is connected to a plurality of memory cells (for example, eight).
Since it is only necessary to provide one side of the memory cell array, the number of memory cell arrays per unit area can be increased by 11 mm, and the structure is suitable for miniaturization of large-capacity memories. however,
Conventional memory has the following problems.

One of them is as follows. In other words, the NAND4 basic block is a NAND4 basic block in which multiple memory cells are connected in series.
It has an ND type cell configuration. Therefore, when reading data from a selected memory cell, it is necessary to turn on other erased unselected memory cells.
It is necessary to turn it on with a gate voltage of 5V, and its threshold voltage needs to be approximately 3V or less. Similarly, the threshold voltage of the erased selected memory cell is approximately 1V.
It is also necessary that the value is at least OV (at least OV or higher). However, in large-capacity memories such as 1M bits or 4M bits, it is difficult to uniformly erase all memory cells, and variations inevitably occur. Due to this variation, if even one of the erased memory cells has a threshold voltage outside the range of OV and 3V, that memory becomes defective. However, it is extremely difficult to design and manufacture a memory that can reliably and uniformly erase all memory cells.

In addition, in order to increase the read speed, it is necessary to
It is necessary to increase the current flowing through the basic blocks. However, in this case as well, if the threshold voltage of a memory cell to which 5V is applied to the gate in a non-selective state is 3V, the on-current cannot be made sufficiently large. For example, 1 μm
In a NAND basic block designed according to rules, only a few microamperes of cell power can be obtained when reading data, making it unsuitable for high-speed processing.

Two of the problems with conventional memory are the need to make it more durable. ``Data writing 111'', for example, when writing data to the memory cell 32, the memory cell 33
The threshold voltage of ~39 is approximately 5V, and the memory cell 3
In order to effectively write to 2, a high voltage of 20V is required. Therefore, it is necessary to take sufficient measures to withstand high voltages in the peripheral circuits, and there is also a problem in terms of reliability due to the voltage stress applied to the memory cells.

The present invention has been made in view of the above.Objectives (5) are: high operating speed, uniform erasure of all memory cells at once, and a low voltage required for writing. The purpose is to provide non-fouling semiconductor memory.

[Structure of the invention]

(Means for Solving Problems) The non-destructive flat conductor memory of the present invention has a plurality of basic blocks in which a number of stages of depressive memory cells are connected in series. In the non-volatile semiconductor memory in which one of the plurality of memory cells is selected to write and read data, the memory cell is 1'.

A pair of source/drain regions are formed on the surface of the conductor substrate with a channel region in between, a floating gate formed above the channel region that can capture an electric current, and a floating gate of the floating gate. and a control gate formed above, and the floating gate is provided at a position shifted along a second direction substantially perpendicular to a first direction along the channel direction of the channel region. 8. A floating gate transistor in which the floating gate and the control gate are located above the channel region, and 1. A floating gate transistor in which only the control gate is located above the channel region. an enhancement type transistor connected in parallel with the floating gate transistor, some of the floating gates sliding toward one end in the second direction,
The others are configured to be shifted toward the other end in the second direction.

(Function) Each memory cell has floating gate transistors connected in parallel. floating·
The threshold voltage of the enhancement mode transistor is lower than the threshold voltage of the gate transistor in the erased state, ie with the floating gate having captured the torpedo 6:f. Therefore, the threshold voltage of each memory cell is determined by the enhancement mode transistor in the erased state quantity. Also, the write state Qllj is determined by a floating gate transistor.

Therefore, even in the disappearance state g47, the cell current of the memory cell takes on a large value because the threshold of the enhancement mode transistor is lowered.

As a result, even if an unselected memory cell in the basic block is in an erased state, the magnitude of the current flowing through the memory cell can be increased, and the operation speed can be increased.

Also, is the threshold voltage in the erased state the threshold of an enhancement mode transistor? [IE, that is, uniformity of all memory cells/IIl-)=is achieved because of a predetermined constant threshold voltage.

Furthermore, since the threshold voltage of the memory cell in the erased state is low, the memory cell can be turned on with a low voltage. Therefore, when writing data to a selected memory cell, even if an unselected memory cell is in the erased state, it can be turned on with a voltage instead, and data can be written to the selected memory cell.

Further, in the present invention, the floating gate of each memory cell in each basic block is arranged in the channel direction (the first
almost perpendicular to the direction); shifted along two directions. Furthermore, floating and
The gates are offset toward one end along the second direction, and the floating gates in others are offset toward the other end along the second direction. Therefore, even if the floating gate is shifted in any direction along the second direction due to mask slippage, the current flowing through a certain basic block will not be particularly reduced. In other words, even if the floating gate moves in a certain direction due to mask slippage, even if the cell current decreases in a certain memory cell (enhancement type transistor), the cell current will decrease in other memory cells (enhancement type transistor). 1st person,
This is because the overall cell current does not decrease significantly. Therefore, even if there is a mask shift, the cell current is prevented from decreasing, and the operation speed is prevented from decreasing.

(Example) FIGS. 1(a) and 1(b) show the present invention in a NAND type EE
This figure shows a memory cell array when applied to a PROM, and FIG. 5(a) is a pattern side view thereof, and FIG. Figure 1(a)
, (b), the same components as in FIGS. 5(a) to (c) are given the same reference numerals as in FIGS. 5(a) to (C). The positions shown in Figures (a) and (b) are obtained by applying voltage in the same way as in Table 1 (however, the voltage value during writing is low and the voltage value during erasing is low). /
r'I write, write, and read operations are performed.

The embodiments shown in FIGS. 1(a) and (b) are the same as those shown in FIGS.
) is different from the memory cell array in which each floating gate 16 is, as can be seen from FIG.
They are arranged in a so-called QW shape, shifted left and right (in the J direction (extension of the control gate 17)).

That is, the position of the floating gate 16 is shifted for each word line and each data line. With such a staggered arrangement of each floating gate 16,
Each floating gate 16 is connected to each memory cell (32 to 32).
39), but only part of it will be covered. As a result, if we look at the channel region of a certain memory cell (three), there will be an upward floating state in that part.
The gate 16 and the control gate 17 are overlapped to form a floating gate transistor, and in the other part of the channel top, only the control gate 17 is present above (1 is an enhancement type transistor (1)). 3Qb).That is, in a certain memory cell, the above two types of transistors are connected in parallel.Therefore, as shown in FIG. 1(a).

(b) Each NANDI book blotter block: lJ (dI
il+] path is represented as shown in FIG.

Next, the operation in each of the eight memory cells 32 to 39, which are tightened by connecting a floating gate transistor and an enhancement type transistor in parallel as shown in FIG. I will explain. Characteristic (b) in Figure 4 is the characteristic of the memory cell in the 7'l'l state. In the erased state, the threshold voltage of the floating gate transistor, for example transistor 32a in FIG. 3, has the characteristic (a) in FIG.
As shown in the figure, the voltage is about 5V, which is crystalline. However, the threshold voltage of the enhancement type transistor 32b connected to the north row of the transistor 32B is 1V, as seen from the characteristic (b). Therefore, the characteristics of the memory cell 52 are as follows:
The characteristic of 2b becomes dominant, and the threshold value becomes 1V. Similarly, the characteristics of the other memory cells 33-39 are dominated by the characteristics of the enhancement mode transistors 33b-39b.

Characteristic (c) in FIG. 4 is the characteristic of the memory cell in the write state. The threshold voltage at this time is approximately -5V. That is, in this write state, the threshold voltage of the enhancement mode transistor (e.g., 32b) is the same as that in the /l'1 table state, or the threshold voltage of the floating gate I transistor (e.g., 32a) is the same as that in the /l'1 table state. The threshold voltage will be approximately 5V. Therefore, the characteristics as a memory cell are dominated by a floating gate transistor, and the voltage is about -5V.

When such a memory cell in which two transistors are connected in parallel is used, the threshold voltage at the time of extinguishing is determined by the enhancement type transistor. Set the enhancement mode transistor so that its threshold voltage is 1V,
And it is easy to manufacture. In addition, the threshold voltage of a floating gate transistor can be set to any value as long as it is IV or higher (at least Ov or higher), so if you perform sufficient erasing while taking into account the variations in threshold voltage, you can obtain a large amount of cell current and obtain stable characteristics. .

Furthermore, erasing, writing, and reading operations as a NAND basic block are the same as those in Table 1 above. However, in conventional memory, i't'i −A Il! Since the threshold voltage for j must be within the range of IV to 3V, it is not possible to apply a very high voltage, and the voltage applied to the word line is
It is necessary to apply a relatively low voltage of 5V to slowly erase the data and carefully shift it to the desired threshold voltage. On the other hand, in the case of the memory of the above embodiment, the threshold voltage at the time of extinguishing is determined by the enhancement type transistor, so the threshold voltage of the floating gate transistor is determined at the time of erasing. There is no need to consider it. Therefore, it is possible to apply a voltage higher than that of the conventional voltage, for example, about 17 V, to the word line to sufficiently suppress the dissipation.

In addition, regarding data writing, in the case of conventional memory, the threshold value of the memory cell that has been removed increases to about 5V, so in order to apply a voltage of 15V to the drain of the selected memory cell, It was necessary to apply a high voltage of 20V to the control gate of unselected memory cells. However, in the case of the above embodiment, the threshold voltage at the time of extinguishing is as low as 1■, and even if the substrate effect is taken into account, it is only 2.
Since it is about 15V at the drain of the selected memory cell, a voltage of about 17V is applied to the control gate of the unselected memory cell, which is 9/-1 lower than the conventional method. do it.

Further, according to the above embodiment of the present invention, the position of the floating gate 16 is set at the first position for each word line and each data line.
In figure (a), since it is shifted by J-1" to the right of A, a margin can be obtained for the misalignment of the mask during manufacturing 1'. ,
The position of the floating cage 16 will be explained in comparison with a case where the floating cage 16 is not even staggered left and right as shown in FIG. FIG. 9 shows all of the floating gates 16,
Compared to the case shown in Figure 5(a), it is uniformly shifted to the left in the figure. However, in the cell shown in FIG. 9, there is little margin for mask misalignment during the manufacturing process. For example, in FIG. 9, assume that a mask misalignment occurs during the formation of the floating gate 6 during the manufacturing process, and the floating gate 6 shifts to the right.

For horizontal reading p of the NAND structure, as shown in Table 1, the selected word line is set to OV1, and the other word lines are set to, for example, 5V. At this time, if 0'' is written in the memory cell of the selected word line, the threshold value is 15V, so the memory cell is turned on and current flows through the NAND-configured cell group.

Furthermore, if "1" is written, the threshold is 1 or 3 V, so it is in an off state and no current flows. This on-current is the minimum, that is, the speed is the worst when only the selected cell is a pig "0" and the other 7
One cell has data "1". That is, the third
If WLl is selected in equibiconcave F8 in the figure, enhancement type transistors 33b to 39b
It is determined by the characteristics of This is because the transistor 32a in the on state has a sufficiently negative threshold value, and a sufficient current flows through the transistor 32a compared to the transistors 33b to 39b. Therefore, if the mask shift occurs and the floating gate 16 shifts to the right, the enhancement mode transistors 32b to 39b
As shown in FIG. 2(a), the current values become smaller in all cases. Under such manufacturing conditions, this memory becomes slow and, in some cases, defective.

On the other hand, according to the embodiment of the present invention, there is a large margin against the mask shift as described above. In other words, the floating cell shown in FIG. 1, as in the previous series,
If we add 4 to the case where it shifts to the right, the =9-valence circuit becomes the second
This is shown in Figure (b). Regarding one data line,
The current values of the enhancement mode transistors alternate between low and high current values along the word line, and in the end, of the 8 NAND cells, 4 have large currents and 4 have small currents. Therefore, the total current is an average current value.

In other words, even if the mask shifts, the current value will not become too small.

Note that in the above embodiment, the floating gates are supported in an intersecting direction of 11 for each word line, but it is not necessary to do so.

For example, as shown in Figure 1A, floating
The direction of the word lines WLI to WL4 and the word lines WL5 to WL8 may be changed by two directions without passing the gates. By shifting them all together in this way, it is expected that manufacturing assistance will be facilitated.

Further, the number of floating gates to be shifted does not necessarily have to be the same in each direction.

〔Effect of the invention〕

According to the present invention, the operating speed is fast, all memory cells can be uniformly erased at once, the voltage used for programming 11.1f can be made low, and the high operating speed can be maintained using the floating gate mask. This is possible even if there is a gap.

[Brief explanation of drawings]

FIG. 1 is a plan view and a sectional view taken along the line AA' of an embodiment of the present invention, FIG. 1A is a plan view of a different embodiment of the present invention, and FIG. 2 is an equivalent circuit showing an increase and decrease in cell current when a mask is misaligned. Explanatory diagram,
Fig. 3 is an equivalent circuit diagram at the position shown in Fig. 1, Fig. 4 is its operating characteristic diagram, Fig. 5 is a plan view of the conventional example, and a sectional view taken along the line A-A'.
BB' line sectional view, Figure 6 is the equivalent circuit diagram of Figure 5, Figure 7 is the equivalent circuit diagram of Figure 5.
The figure shows its operating characteristics, FIG. 8 is an explanatory diagram showing erasing and writing to a memory cell, and FIG. 9 is a plan view of a memory showing an example of a floating gate arrangement used to explain mask displacement in the present invention. . 11... Semiconductor substrate, 15... Source train ff
I area, 16... Floating gate, 17... Control gate, 32 to 39. Memory cell, 32
a to 39a... Floating gate transistor, 32b to 39b... Enhancement type transistor.

Claims (1)

[Scope of Claims] It has a plurality of basic blocks in which a plurality of nonvolatile memory cells are connected in series, and in the basic block, data is written by selecting one of the plurality of memory cells in the block. , a nonvolatile semiconductor memory for reading, wherein the memory cell includes a pair of source/drain regions formed on a surface portion of a semiconductor substrate with a channel region sandwiched therebetween;
The memory cell has a charge trapping floating gate formed above the channel region and a control gate formed above the floating gate, and the memory cell has a charge trapping floating gate formed above the channel region. The floating gate and the control gate are located above the channel region, and the floating gate and the control gate are provided at positions shifted along a second direction substantially perpendicular to a first direction along the channel direction. - comprises a gate transistor and an enhancement type transistor in which only the control gate is located above the channel region and is connected in parallel with the floating gate transistor, A non-volatile semiconductor memory characterized in that some of them are shifted toward one end in the second direction, and others are shifted toward the other end of the second direction.