JPH0384650A - Data transfer system - Google Patents

Abstract

PURPOSE:To shorten the time required for transfer of continuous addresses by setting a start address to an address generating circuit with an I/O command and writing or reading only the transfer data into or out of a memory. CONSTITUTION:A store address is set to an address generating circuit 2 with an I/O command and then the transfer block number is set to a transfer block number circuit 6 with an I/O command. Hereafter the address is neglected and only the transfer data is written into a memory 1. At the side of the mem ory 1, a control circuit 5 adds 1 to the address of the circuit 2 every time the data is inputted to a FIFO (first-in first-out) 4-1 and sends a write pulse to the memory 1. As a result, the data is once stored in the FIFO 4-1 and the time required for transfer of data is shortened since the writing speed of the FIFO 4-1 is higher than that of the memory 1.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a data transfer system, and particularly to input/output, as will be described later.
The present invention relates to a high-speed data transfer method that achieves high-speed data transfer by using the ``out''.

[Conventional technology]

In conventional data transfer, the data transfer side outputs an address, then outputs the data, Read/Write signal, and receives an ACK signal from the memory.
Once the transfer is complete, the next transfer involves repeating the same process as above starting from the output of the address.

Regarding this, for example, see the Institute of Electronics, Information and Communication Engineers, ``
It is possible to refer to the description in Section 2, Volume 22, Electronic Information and Communication Handbook' 881 (published by Ohmsha, 1988).

[Problem to be solved by the invention]

The above process takes time, and the above ACK
The signals are generated by a memory control circuit, which is memory dependent and therefore quite slow in processing, which also slows down data transfer time.

This becomes a big problem, especially when transferring a large amount of data such as image data.

However, image data has the characteristic that it is data of consecutive addresses.

The present invention has been made in view of the above circumstances, and its purpose is to solve the above-mentioned problems in the conventional technology and to significantly reduce the transfer time of data at consecutive addresses such as image data. The objective is to provide a high-speed data transfer method that allows for high-speed data transfer.

[Means to solve the problem]

The above object of the present invention is to provide an apparatus that writes data to or reads data from a memory by understanding an address generation circuit that controls memory addresses, a transfer block number circuit that counts the number of transfer blocks, and input/output addresses. an input/output control circuit that generates clocks for the address generation circuit and the transfer block number circuit;
A FIFO, which is a data input/output buffer, was installed, and at first,
The start address is set in the address generation circuit using the I/O command, and the number of transfer blocks is set in the I/O command in the same way.
This is achieved by a data transfer method characterized in that after setting the number of transfer blocks in the transfer block number circuit using the O command, only transfer data is written to or read from the memory.

[Operation] In the data transfer method according to the present invention, in view of the fact that image data has the characteristic that it is data with consecutive addresses, the start address for writing data to or reading data from memory is and,
After setting the number of transfer data blocks in advance and specifying only the data transfer start position, the address is automatically increased by one in synchronization with the data transfer, making it possible to omit address specification. It is something. This results in
This simplifies and speeds up processing.

〔Example〕

Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention. In the figure, l is a memory, 2 is an address generation circuit that controls memory addresses, and 3-1 and 3-2 are used to understand I/O addresses and use the address generation circuit 2 described above or the transfer block number circuit 6 described later. The I/O control circuit 4-1.4-2 generates a clock, and 4-2 is a data input/output buffer FIFO (First F1rst-out).
), 5 is a control circuit that controls the entire memory control,
6 indicates a transfer block number circuit that counts the number of transfer blocks.

The operation of this embodiment will be explained below. In the example explained below, as a condition, the side transferring the data also
It is assumed that the configuration is the same as that described above, and only the operation during data writing will be described. In the case of data read, the operation is the opposite.

First, the storage address is set in the address generation circuit 2 using an I/O command, and then the number of transfer blocks is set in the same way as the I/O command.
Set the transfer block number circuit 6 with the O command. After this, it is sufficient to ignore the address and write only the transfer data to the memory l. On the memory side, data is FIFO
4-1, the control circuit 5 causes the address generation circuit 2 to
+l address and sends a write pulse to the memory. At this time, the data is temporarily stored in FIFO 4-1, but the write speed of FIFO 4-1 is limited to the memory l.
Since it is significantly faster than , data transfer time is significantly reduced.

FIG. 2 shows an operation timing chart.

This will be explained in comparison with the conventional data transfer case shown in FIG.

Conventionally, as shown in Figure 3, the data transfer side first outputs the address, then the data, and then the R6ad/
Reading or writing is executed in response to the Write signal, and one transfer ends when an ACK signal is received from the memory. In this case, it usually takes 100 to 200 nsec from execution of read or write to count of ACK signals (time indicated by tl in the figure). In the conventional technique described above, this process is simply repeated.

On the other hand, in the case of the method of the present invention shown in FIG.
After setting the address, it is sufficient to simply write the transfer data to the memory without considering the address. During this time, on the memory side, each time data enters FIFO4-1,
The control circuit 5 sets the address of the address generation circuit 2 to +l.
and sends a light pulse to the memory. Data is FIF○
4-1, and sequentially stored in the memory 1.

In this case, from the read or write execution, the ACK
The time required for counting the number of signals (time indicated by t in the figure) is shortened to several tens of n5ec or less.

Note that the above explanation assumes that the CPU does not intervene in the data write operation to the memory, but in this case, the time for address specification processing by the CPU is not required, so the processing time is also reduced by that amount. There is a synergistic effect. However, the present invention is not limited to this, and is also possible when the CPU intervenes and performs addressing. In this case, there is an effect of shortening the transfer time only because the return of the ACK signal becomes faster.

It should be noted that the above-mentioned embodiment is shown as an example of the present invention, and it goes without saying that the present invention should not be limited thereto.

〔Effect of the invention〕

As described in detail above, according to the present invention, in a device that writes data to a memory or reads data from a memory, an address generation circuit that controls a memory address, a transfer block number circuit that counts the number of transfer blocks, Initially, a human output control circuit that understood input/output addresses and generated clocks for the address generation circuit and transfer block number circuit, and a first-in-first-out (FIF○) buffer for data input/output were provided.

The start address is set in the address generation circuit using the I/O command, and the number of transfer blocks is set in the I/O command in the same way.
After setting the number of transfer blocks in the transfer block number circuit using the O command, only the transfer data is written to or read from the memory, which enables high-speed data transfer that can significantly reduce the transfer time of data at consecutive addresses. This has the remarkable effect of realizing the system.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention, and FIG.
The figure is an operation timing chart of the embodiment, and FIG. 3 is an operation timing chart of conventional data transfer. 1: Memo 1c 2 Near address generation circuit, 3-1.3-2
:I/○ control circuit, 4-1.4-2: FI F○, 5
: control circuit, 6: transfer block number circuit. Figure G

Claims (1)

[Claims] (1) In a device that writes data to or reads data from memory, there is an address generation circuit that controls memory addresses, a transfer block number circuit that counts the number of transfer blocks, and an address generation circuit that understands input and output addresses. and an input/output control circuit that generates a clock for the transfer block number circuit, and a FIFO (First-in-First
-out), the start address is initially set in the address generation circuit with an I/O command, and the number of transfer blocks is similarly set in the transfer block number circuit with an I/O command, then the transfer A data transfer method characterized in that only data is written to or read from memory.