JPH0383409A - Pulse signal recognition circuit - Google Patents

Abstract

PURPOSE:To execute correct recognition even when there is a noise, or a pulse missing during pulse signalling by installing a level deciding means which decides the level of signal with a clock which possesses a frequency plural times the frequency of the pulse signal which becomes an object of recognition and a recognizing means to recognize the pulse signal based on the decided result of this level deciding means. CONSTITUTION:The period of time when the input signal level is 'H' is counted by a counter 4, and the period of time when the input signal level is 'L' is counted by a counter 6. These count values are each detected by count number detectors 5, 7, and when the count value becomes a prescribed value (m), the values are notified by prescribed signals to a pulse detector 8. The pulse detector 8 recognizes the signal of the 'H' level when the signal is inputted from the count number detector 5, and the signal of the 'L' level when the signal is inputted from the count number detector 7. By lack of signal or noise, a part of the 'H' level is generated in the output signal of an OR gate 2 and the output signal of an NAND gate 3, but the count number detectors 5, 7 do not output the signals, and these parts are ignored.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a pulse signal recognition circuit that recognizes a pulse signal such as an identification signal superimposed on a video signal and transmitted in an FM video time division transmission system using a satellite, for example.

(Prior art) In the FM video time division transmission method using satellites,
An identification signal for identifying the video to be transmitted is superimposed on the video signal and transmitted. This identification signal uses a pulse signal of a predetermined frequency f, which is set to "1" when the signal is present and "0" when the signal is absent.

On the receiving side, the identification signal transmitted superimposed on the video signal is extracted using a narrow band filter and level detected. The signal level of the obtained identification signal is determined by a comparator, and the rlJ and rOJ patterns are recognized.

Conventionally, a pulse signal recognition circuit that recognizes such a pulse signal uses a clock having the same frequency as the frequency f of the pulse signal to be recognized, and determines the signal level at the center of the pulse, for example, as shown in Figure 3. By doing this, it became possible to recognize pulse signals.

However, with this pulse signal recognition circuit, the signal level is judged only at one point in the pulse, so noise may appear at the level judgment point in the pulse signal.
If a pulse is missing, it will be erroneously recognized.

Note that, for example, in the FM video time-division transmission system, the above-mentioned noise occurs even when the C/N ratio is at a level where the video is sufficiently recognizable.

(Problems to be Solved by the Invention) As described above, in the conventional pulse signal recognition circuit, the signal level is determined only at one point in the pulse.
There was a problem in that it could easily be misrecognized due to the influence of noise and the like.

The present invention was made in consideration of these circumstances, and its purpose is to enable accurate recognition even when noise is included in the pulse signal or pulses are missing. The object of the present invention is to provide a pulse signal recognition circuit that can perform the following steps.

[Structure of the Invention] (Means for Solving the Problems) The present invention includes a level determining means for determining the level of a signal using a clock having a frequency that is multiple times the frequency of a pulse signal to be recognized, Based on the determination result by the means, for example, when the detection level of the level determining means changes, if the level after the change is not determined a predetermined number of times in succession by the level determining means, it is recognized that there has been no change in the level. By doing so, the pulse signal is recognized.

(Function) By taking such a measure, the signal level is determined using a clock having a frequency that is multiple times the frequency of the pulse signal to be recognized, and the pulse signal is determined based on the result of this determination. Recognized.

Therefore, identification is performed based on signal levels determined at multiple locations within one pulse, resulting in more accurate recognition. Also, for example, when the detection level changes, if the level after the change is not determined a predetermined number of times in succession, it is recognized that there has been no change in level, thereby ignoring level changes in a minute period during one pulse. be able to.

(Embodiment) Hereinafter, a pulse signal recognition circuit according to an embodiment of the present invention will be described with reference to the drawings. Here, a pulse signal recognition circuit that recognizes a pulse signal of a predetermined frequency f, which is set to "1" when there is a signal and "0" when there is no signal, will be exemplified.

FIG. 1 is a block diagram showing the configuration of the pulse signal recognition circuit. In the figure, 1 is a shift register, into which a pulse signal to be recognized is input. In addition, the shift register 1 has a clock (hereinafter referred to as
(referred to as a recognition clock) is input. The output Q*-+ and the output Q of this shift register 1. are both input to the OR gate 2 and the NAND gate 3. That is, the shift register 1 generates a pulse signal whose phase is shifted by one clock from the recognition clock.

The OR gate 2 takes the OR of the output Qm-i and the output Q of the shift register 1 and outputs the result to the counter 4. The counter 4 is an m-ary counter, and counts the number of recognition clocks input separately when the output of the OR gate 2 is at the rHJ level.

5 is a count number detector. This count number detector 5
detects the count number of the counter 4, and outputs a predetermined signal when the counter 4 counts a predetermined value m. Note that the counter 4 resets the count value when the output signal of the OR gate 2 reaches the rLJ level during the counting operation. Then, when the output signal of the OR gate 2 becomes rHJ level again, counting starts from the initial state.

On the other hand, the NAND gate 3 outputs the output Q of the shift register 1.
@-1 and output Q. The NAND result is obtained and outputted to the counter 6. Counter 6 is an m-ary counter, and N
When the output of the AND gate 3 is at the rHJ level, the number of clocks of the separately input recognition clock is counted.

7 is a count number detector. This count number detector 7
detects the count number of the counter 6, and outputs a predetermined signal when the counter 6 counts a predetermined value m. Note that the counter 6 is connected to the NAND gate 3 during the counting operation.
When the output signal reaches the rLJ level, the count value is reset. Then, the output signal of NAND gate 3 is r
When the HJ level is reached, the signals output from the count number detector 5 and the count number detector 7, which start counting from the initial state, are input to the pulse recognizer 8. The pulse recognizer 8 recognizes the input pulse signal according to the signals output from the count number detector 5 and the count number detector 7, and generates and outputs a pulse signal from which noise during transmission is removed. This pulse signal is decoded by the decoder 9 and output as identification data.

Next, the operation of the pulse signal recognition circuit configured as above will be explained with reference to the time chart shown in FIG.

First, it is assumed that the output Q, -3 of the shift register 1 is a signal shown as 81 in FIG. 2, for example, and the output Q is a signal shown as 82 in FIG. 2, for example.

Then, the output of the OR gate 2 becomes the signal shown at 83 in the i2 diagram. During the period when the output signal of the OR gate 2 is at the rHJ level, the counter 4 counts the number of recognition clocks shown at 85 in FIG. That is, the counter 4 counts the rHJ level period in the input pulse signal.

For example, suppose that there are omissions (one pulse of the recognition clock) as shown at 21 and 22 in FIG. However, when the OR gate 2 is input manually, the phase of the recognition clock is shifted by one pulse, so the output of the OR gate 2 remains at the rHJ level. Therefore, counter 4
does not stop the counting operation due to the omissions 21 and 22, and ignores the omission 2122. Note that since the OR is performed on signals whose phases are shifted by one pulse of the recognition clock, the rHJ level period of the output signal of OR gate 2 is longer than the rHJ level period of the input pulse signal by one pulse of the recognition clock. becomes.

On the other hand, the output of the NAND gate 3 is the output Q*-t of the shift register 1 and the output Q, as shown by S4 in FIG.
level is rHJ when either of them is at rLJ level.
The signal becomes . During the period when the output signal of the NAND gate 3 is at the rHJ level, the counter 6 counts the number of recognition clocks indicated by S5 in FIG. 2. That is, the counter 6 counts the rLJ level period in the input pulse signal.

For example, suppose that noise (corresponding to one pulse of the recognition clock) as shown at 23 and 24 in FIG. 2 occurs.

However, when input to the NAND gate 3, the phase of the recognition clock is shifted by one pulse, so the NAND
The output of gate 3 remains at rHJ level. Therefore,
The counter 6 does not stop its counting operation due to the noise 23.24, but ignores the noise 23.24.

Note that since NAND is performed on signals whose phase is shifted by one pulse of the recognition clock, the rHJ level period of the output signal of the NAND gate 3 is longer than the rLJ level period of the input pulse signal by one pulse of the recognition clock. becomes.

Thus, the input signal level at the counter 4 is rHJ
The counter 6 counts the period when the input signal level is rLJ. The count values of these counters 4 and 6 are detected by a count number detector 5.7, and when the count value of the counter 4.6 reaches a predetermined value m, a pulse recognizer 8 is detected by a predetermined signal.
will be notified. The pulse recognizer 8 then recognizes the pulse as follows. That is, when a signal is input from the count number detector 5, a signal of rHJ level,
Further, when a signal is input from the count number detector 7, it is recognized as a signal at the rLJ level. Here, the predetermined value m is determined by the counter 4 at an rHJ level period that is one pulse of the recognition clock longer than the rHJ level period of the human pulse signal and the rLJ level period of the input pulse signal.
Since 6 is the value to be counted, if the frequency of the recognition pulse is 5 times the frequency of the input signal, it is 6.

In addition, due to omissions 21.22 and noise 23.24! i
The rHJ level parts as shown by 21a, 22a, 23a, and 24a in the s2 diagram are the output signal of OR gate 2 and N
This occurs in the output signal of the AND gate 3, and the value counted by the counters 4 and 6 is "2" here. Therefore, the count detector 5.7 does not output a signal,
These are ignored.

As described above, according to the pulse signal recognition circuit of this embodiment, any omission or noise whose width is one pulse of the recognition clock or less can be completely ignored, and the pulse signal can be recognized more accurately. Most of the omissions and noise can be ignored by optimally setting the frequency of the recognition clock in consideration of the frequency of the pulse signal to be recognized and the omissions and noise that occur.

Note that the present invention is not limited to the above embodiments. For example, the pulse signal may be recognized by processing data obtained by performing level detection according to the recognition clock using software. Further, in the above embodiment, the configuration is such that omissions and noise of one cycle or less of the recognition clock are ignored, but it is also possible to configure such that omissions and noise longer than this are ignored. Furthermore, although the above embodiments illustrate a pulse recognition circuit that recognizes binary pulse signals, it may be a pulse recognition circuit that recognizes multivalued pulse signals. In addition, various modifications can be made without departing from the gist of the present invention.

〔Effect of the invention〕

According to the present invention, for example, the level determining means is provided for determining the level of a signal using a clock having a frequency that is multiple times the frequency of the pulse signal to be recognized, and based on the determination result by the level determining means, for example, the level When the detection level of the determining means changes, if the level after the change is not determined by the level determining means a predetermined number of times in succession, the pulse signal is recognized by recognizing that there has been no change in the level. As a result, the pulse signal recognition circuit can perform accurate recognition even when noise is included in the pulse signal or pulses are missing.

[Brief explanation of drawings]

1 and 2 are diagrams explaining a pulse signal recognition circuit according to an embodiment of the present invention. FIG. 1 is a block diagram showing the configuration, and FIG. 2 is a signal waveform at each part in FIG. 1. The time chart shown in FIG. 3 is the meat that explains the prior art. 1...Shift register, 2...OR gate, 3...
・NAND gate, 4, 6...Counter, 5.7...
- Count number detector, 8, pulse recognizer, 9...decoder.

Claims (2)

[Claims] (1) Level determination means for determining the level of a signal using a clock having a frequency that is multiple times the frequency of the pulse signal to be recognized; and recognition means for recognizing the pulse signal based on the determination result by this level determination means. A pulse signal recognition circuit comprising: (2) The recognition means recognizes that there has been no change in level when the level detected by the level determination means changes and the level after the change is not determined a predetermined number of times in succession by the level determination means. Claims characterized (
1) The pulse signal recognition circuit described above.