JPH0382214A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To expand margin of a clock signal and to attain high speed processing of a high speed logic integrated circuit device or the like by constituting all gate circuits relating to a clock transfer path in a variable delay circuit with a differential gate circuit having at least a couple of complementary input terminals and of complementary output terminals. CONSTITUTION:A complementary clock signal fed from a clock generating circuit of a high speed logic integrated circuit device is transferred to 3 delay circuits connected substantially in series via an input gate circuit RGI of a variable delay circuit. Each delay circuit consists of a driving gate circuit (DG1-DG3) having 2 sets of complementary output terminals, a couple of capacitance gate circuits (CG1, CG2-CG5, CG6) and a selection gate circuit (SG1-SG3) having 2 sets of complementary input terminals respectively. Thus, a clock signal is transferred without giving effect on its duty cycle. Thus, the margin of the clock signal is expanded and the processing speed of the high speed logic integrated circuit device or the like is improved.

Description

Detailed Description of the Invention (Field of Industrial Application) The present invention relates to a semiconductor integrated circuit device, and relates to a technique that is particularly effective when applied to, for example, a high-speed logic integrated circuit device including a variable delay circuit. be.

[Conventional technology]

E CL (Esitter Coupled L
2. Description of the Related Art There is a high-speed logic integrated circuit device which has a basic configuration of a logic circuit or the like and operates synchronously according to a predetermined clock signal.

Further, there is a variable delay circuit provided in such a high-speed logic integrated circuit device for adjusting the skinny etc. of a clock signal.

Regarding delay circuits, for example, Japanese Patent Application Laid-Open No. 60-16751
It is described in Publication No. 9, etc.

[Problem to be solved by the invention]

FIG. 6 illustrates a circuit block diagram of a variable delay circuit of a high-speed logic integrated circuit device developed by the inventors of the present invention prior to the present invention. In the same figure, the variable delay circuit is
Complementary clock signal MCP (Here, for example, non-inverted clock signal MCP and inverted clock signal MCP are collectively expressed as complementary clock signal MCP. Hereinafter, complementary signals, complementary input/output terminals, etc. will be expressed in the same way.)
, and includes three delay circuits that receive and are substantially serially coupled. These delay circuits include drive gate circuits D08 to DGIO having two non-inverting output terminals, and two capacitive gate circuits CG? connected to one non-inverting output terminal of each drive gate circuit. and C60 to CGII and CG1
2, and a pair of NOR gate circuits N0Gl and N0G2 to N0G5 and N whose output terminals are logically connected.
0G6, each selection circuit non-inverts one or the other of the corresponding drive gate circuits D08-DG10 according to complementary ashes control signals SCI-SC3 held by the corresponding flip-flop circuits FF8-FFl0. Selectively transmit the output signal. The output signal of the i & final stage selection circuit passes through drive gate circuits DGII-DG13 and is then distributed to each circuit of the high-speed logic integrated circuit device as a complementary clock signal CPI-P6.

As a result, the variable delay circuit shown in FIG. 6 is free.

By selectively setting or re-centing the 17071 circuits FF8 to FFl0, the complementary clock signal ¥-
It is possible to change the effective delay time of CP and adjust its skinny.

However, the inventors of the present invention have discovered that the variable delay circuit as described above has the following problems. That is, the gate circuits constituting each delay circuit of the variable delay circuit in FIG. 6 are so-called single-ended gate circuits that receive only an inverted input signal and output only a non-inverted output signal, and are set at a predetermined reference potential V8B. Let be its logical threshold level. Therefore, for example, by setting the flip-flop circuit FF8 to a reset state and setting the inversion selection control signal SCI to a high level, the capacitor gate circuit CG? When the clock signal delayed by C60 and C60 is transmitted, the level of internal node nc is equal to
As shown in yJ, since the bipolar transistor (hereinafter simply referred to as a transistor) constituting the output lid follower circuit of the drive gate circuit DG8 is turned on, its rise is accelerated; At the time of falling, which is the OFF state, there is a gradual change determined by the resistance constituting the output follower circuit and the load capacitance coupled to the internal node nC. Therefore, at the input terminal of the variable delay circuit, approximately 5
The duty of complementary clock signal MCP which is assumed to be 0% is:
It is compressed at the output terminal of the NOR gate circuit N0G2, that is, the internal node nd, and is transmitted as it is to the subsequent delay circuit. As a result, the margin of the clock signal is gradually reduced, which correspondingly limits the speeding up of high-speed logic integrated circuit devices.

An object of the present invention is to provide a delay circuit and a variable delay circuit that do not affect the duty of a transmitted clock signal or the like. Another object of the present invention is to increase the clock frequency of a high-speed logic integrated circuit device, etc. including a variable delay circuit, and to promote speeding up of the device.

The above and other objects and novel features of this invention include:
It will become clear from the description of this specification and the accompanying drawings.

[Means to solve the problem]

A brief overview of typical inventions disclosed in this application is as follows.

That is, in a variable delay circuit or the like of a high-speed logic integrated circuit device, all gate circuits related to a clock transmission path are constituted by differential gate circuits having at least one pair of complementary input terminals and complementary output terminals.

[For production]

According to the above-mentioned means, a clock signal etc. can be transmitted without affecting its duty.

As a result, it is possible to correspondingly expand the margin of clock signals, etc., and promote speeding up of high-speed logic integrated circuit devices, etc.

〔Example〕

FIG. 1 shows a circuit block diagram of an embodiment of a variable delay circuit to which the present invention is applied.

Further, FIGS. 2 and 3 each show a circuit diagram of an embodiment of a drive gate circuit DGI and a selection gate circuit Set included in the variable delay circuit of FIG. 1. Based on these figures, an overview of the configuration and operation of the variable delay circuit of this embodiment as well as its characteristics will be explained. Note that the variable delay circuit of this embodiment is included in a high-speed logic product circuit device such as a computer, although it is not particularly limited, and is used, for example, for skinny adjustment of the complementary clock signal MCP. 1st
Each of the circuit elements shown in the figures through FIG. 3 is formed on a single semiconductor substrate such as, but not limited to, single crystal silicon, together with other circuit elements constituting a high-speed logic integrated circuit device. In addition, in FIGS. 2 and 3, the bipolar transistors illustrated are not particularly limited, but
All are NPN type transistors. Further, in FIG. 4, the non-inverted signal (fi) of each complementary signal is shown by a solid line, and the inverted signal is shown by a dotted line.

In FIG. 1, a complementary clock signal MC is supplied from a clock generation circuit (not shown) of a high-speed logic integrated circuit device.
Although not particularly limited, P passes through the input gate circuit RGI of the variable delay circuit, and then is transmitted to three delay circuits that are substantially connected in series. These delay circuits include, but are not particularly limited to, drive gate circuits DG1 to DG3 having two sets of complementary output terminals, a pair of capacitive gate circuits cGl and CG2 to CG5 and CG6, and two sets of complementary input terminals. gate circuits 5GI-3G3, respectively.

One complementary output terminal of the drive gate circuits DGI-DG3 is, although not particularly limited, the corresponding selection gate circuit 5GI.
-5G3 is coupled to one complementary output terminal 8 of (lfl
One complementary output terminal is connected to a corresponding pair of capacitive gate circuits C.
After being coupled to complementary input terminals of GI and CG2 to CG5 and CG6, it is coupled to the other complementary input terminal B of the selection gate circuits 5GI-SG3.

The control input terminal C of the selection gate circuit 5GI-3G3 is
Non-inverted output signals of the corresponding 79717071 circuits FFI-FF3, that is, selection control signals S01-SC3 are supplied. Although not particularly limited to the non-inverting input terminals of these flip-flop circuits FFL-FF3, corresponding selection control signals DCI-DC3 are supplied from an AiT stage circuit (not shown) of the high-speed logic integrated circuit device, and the control inputs thereof A non-inverted clock No. 13 CP5 is commonly supplied to the terminal T. Flip-flop circuits FFI to FF3 take in and hold the corresponding selection control signals DCI-DC3 in accordance with the non-inverted clock fd signal CP5.

On the other hand, the complementary output terminals of the selection gate circuits SGI and SG2 are coupled to the complementary input terminals of the next stage delay circuit, that is, the drive gate circuit DG2 or DG3, and the selection gate circuit S
Complementary output terminals of G3 are commonly coupled to complementary input terminals of clock distribution drive gate circuits D04 to DG6.

The output No. 78 of these drive gate circuits DC4 to DG6 is distributed to each circuit of the high-speed logic integrated circuit device as a complementary clock signal -Ω-PI-CP6, and the -
The part is not particularly limited, but the number of flip-flops is 1i%.
FF4~FF? The signal is also supplied to a clock frequency divider circuit consisting of a drive gate circuit DG7. Drive gate circuit DG7
The output signal is supplied as the output No. 18 of the clock frequency dividing circuit, that is, the complementary clock signal DCP1, to a subsequent stage circuit (not shown) of the high-speed logic integrated circuit device.

Here, the drive gate circuits DG1-DG7 have a basic configuration of a pair of differential transistors TI-T2, as represented by the drive gate circuit DGI in FIG.

The bases of transistors Tl and T2 are respectively coupled to a non-inverting input terminal I and an inverting input terminal I of each drive gate circuit. Further, between the commonly coupled emitters of these transistors and the power supply voltage of the circuit, there is a constant current transistor T3 and a resistor R3, which receive a predetermined constant voltage Vcsl at their bases. A source is provided. Here, the power supply voltage of the circuit is not particularly limited, but is set to be a negative power supply voltage such as -5.2V.

Collector of transistor TI, i.e., inverted internal node n
2 is coupled to the ground potential of the circuit via a load resistor R1 and to the bases of transistors T6 and T7. Similarly, the collector or non-inverting internal node n1 of transistor T2 is coupled to the circuit ground potential via a load resistor R2 and to the bases of transistors T4 and T5. Between the emitters of the transistors T4 to T7 and the circuit power supply voltage, there are transistors T8 to T8 whose bases receive a predetermined constant current of 111Vcs2.
A constant li consisting of Tll and corresponding resistors R4 to R7
Each story has its own story. The emitter of transistor T5 is coupled to the non-inverting output terminal 01 of each drive gate circuit, and the emitter of transistor T4 is coupled to the second non-inverting output terminal 02. Similarly, transistor T
6 is coupled to the first inverting output terminal O1 of each drive gate circuit, and the emitter of the transistor T7 is coupled to the second inverting output terminal O2. As a result, transistors Tl and T2 are connected to transistor T3 and resistor R.
The transistors T4 to T7, together with the corresponding constant current sources, constitute a current switch circuit for the non-inverting input signal I and the inverting input signal I. Configure each.

From these facts, the non-inverting internal node nl of each drive gate circuit has the level of the non-inverting input signal I equal to the inverting input signal ■
When the voltage is raised higher than the level of , it is set to a high level like the ground potential of the circuit, and under the opposite conditions, it is set to a predetermined low level determined by the current value of the constant voltage source consisting of the transistor T3 and the resistor R3 and the resistance value of the resistor R2. It is said that -force,
The inverting internal node n2 of each drive gate circuit is set to a high level, such as the ground potential of the circuit, when the level of the non-inverting input No. 16 I is made lower than the level of the inverting input No. 18 No. 1, and under the opposite condition, the above-mentioned It is set to a predetermined low level determined by the current value and the resistance value of the resistor R1.

The level of the non-inverted internal node nl is the level of the transistor T
After being lowered by the base-emitter voltage of 4 and r5, it is sent out from the non-inverting output terminals 01 and 02 of each drive gate circuit. Similarly, the level of the inverted internal node n2 is lowered by the base-eminter voltage of the transistors T6 and T7, and then sent out from the inverted output terminals O1 and 02 of each drive gate circuit.

Next, the selection gate circuits 5G1-3G3 are connected to two pairs of M
The basic configuration includes dynamic transistors T12 and T13 and T14 and T15. The bases of transistors T12 and T13 are coupled to the first non-inverting input terminal A and the inverting input terminal A of each selection gate circuit, respectively, and the bases of transistors T14
The bases of T15 and T15 are respectively coupled to the second non-inverting input terminal B and the inverting input terminal B of each selection gate circuit. The commonly coupled emitters of differential transistors T12 and T13 are coupled to the collector of transistor T16;
The commonly-coupled emitters of the differential transistors T14 and T15 are coupled to the collector of the transistor T17 which is in a differential configuration with the transistor T16. The base of the transistor T16 is connected to the control input terminal C of each selection gate circuit.
A predetermined reference potential Vaa is supplied to the base of the transistor T17. A constant current source consisting of a transistor T18 and a resistor 810 is provided between the commonly coupled terminals of the transistors T16 and T17 and the power supply voltage of the circuit.

The collector of transistor T12, ie, the inverted internal node n4, is coupled to the circuit ground potential via a load resistor R8, as well as to the collector of said transistor T14 and further coupled to the base of transistor T20. Similarly, the collector of the transistor T13, that is, the non-inverting internal node n3, is coupled to the ground potential of the circuit via the load resistor R9, and the transistor T1
5, and further coupled to the base of transistor T19. Transistors T19 and 'r20
A transistor R21 and a resistor R11 or a transistor are respectively provided between the vine and the power supply voltage of the circuit. The emitter of transistor T19 is coupled to the non-inverting output terminal of each selection gate circuit, and the emitter of transistor T2
The zero emitter is coupled to the inverting output terminal.

As a result, the differential transistors T16 and T17 act as a current switch circuit for the control input signal C, which sets the reference potential BB to the logic threshold level. Furthermore, when the transistor T16 is turned on, or in other words, when the level of the selection control signal C is made higher than the reference potential VB13, the differential transistors T12 and TI3 are connected to the non-inverting input T8 A and the inverting input signal A. acts as a current switch circuit for the differential transistor T1
4.T15 acts as a current switch circuit for the non-inverting input signal B and the inverting input T8B when the transistor T17 is turned on, in other words, when the level of the ashes control signal C is lower than the reference potential VBB. do. Transistors T19 and T20, together with corresponding constant current sources, each constitute an output emitter follower circuit.

For these reasons, the non-inverting internal node n3 of each selection gate circuit is activated when the control input signal C is set to high level and the level to the non-inverting input signal is made higher than the level of the inverting input signal A, or when the control input 78 When the signal C is set to a low level and the level of the non-inverting input signal B (i On the other hand, when the control input signal C is set to high level and the level of the non-inverted input signal A is made lower than the level of the inverted input signal A, the inverted internal node n4 of each selection gate circuit is connected to the inverted internal node n4. is set to a low level and the level of the non-inverted input signal B is set to the inverted input signal B.
When the level is lower than the level of , it is set to a high level like the ground potential of the circuit, and under the opposite conditions, it is set to a predetermined low level. The level of the non-inverted internal node n3 is
After the voltage at the base of transistor T19 is lowered, it is sent out from the non-inverting output terminal of each drive gate circuit. Similarly, the level of the above-mentioned inverting internal n4 is sent out from the inverting output terminal of each drive gate circuit after being lowered by the base-emitter voltage of the transistor T20. As a result, the selection gate circuits SGI to SG3 receive the control signal SCI supplied to their control input terminals C.
~ When SC3 is set to high level, the complementary signal supplied to the first complementary input terminal A, that is, the undelayed first complementary output (3) of the corresponding drive gate circuit DGI-DG3.
When the ashes control fδ signal SCt to SC3 is set to low level, the complementary signal supplied to the second complementary input terminal B, that is, the corresponding wJA dynamic gate circuit @DGI-D
It transmits the delayed complementary output signal of G3.

The input gate circuit RGI has the same circuit configuration as the drive gate circuits DGI-DG7 described above, except that only one set of output limiter follower circuits is provided, and transmits the complementary clock signal MCP. -Meanwhile, -capacitance gate circuit CGI
-CG6 has the same circuit configuration as the drive gate circuits DGI to DG7, except that an output emitter follower circuit is not provided, although it is not particularly limited, and the second non-contact circuit of the corresponding drive gate circuits DGI to DG3. The fall of an inverted or inverted output signal is made gradual in accordance with its input capacitance.

In other words, in the variable EJ delay circuit of this embodiment, all the data circuits related to the transmission path of the clock signal are constituted by differential gate circuits with complementary input terminals and output terminals. Therefore, the selection filJ
The control signal SC1 is set to low level, and the selection gate circuit SG
The second complementary output 73 of the drive gate circuit DGI by I
Focusing on the case where a signal is transmitted, first, only the falling edge of the non-inverted and inverted signal 907534 at the second complementary output terminal of the drive gate circuit DGI, that is, the complementary internal node Ub, is transmitted to the capacitor gate circuit CGI and CG20 input. The rate will be gradual depending on the capacity. Then, the levels of the non-inverted and inverted clock signals at the complementary output terminal of the selection gate circuit SGI, that is, the complementary internal node nb, are inverted following the level inversion of the non-inverted and inverted signals at the complementary internal node na. Therefore, the duty of the non-inverted and inverted clock signals at the complementary internal node nb is the duty of the complementary clock signal MCP, that is, approximately 5
0% will remain unchanged.

As described above, the high-speed logic integrated circuit fabrication of this embodiment is as follows:
A variable delay circuit is provided in which three delay circuits are substantially connected in series. Each delay circuit has a selection control 1δ No. 5C held by the corresponding lid follower circuit FFI to FF3.
In accordance with I-3C3, the complementary [Ttsuk 1a M CP, the output signal of the previous stage delay circuit, or the respective delayed signals are selectively transmitted. Thereby, the delay time of the variable delay circuit is selectively set, and the skew of the complementary clock signal is adjusted. In this embodiment, all gate circuits related to the clock transmission path of the variable delay circuit are differential gate circuits having at least one pair of complementary input terminals and complementary output terminals, including FF4 to FF7 constituting the Cronk distribution circuit. Consisted of. Therefore, the complementary clock signal MCP is transmitted through the variable delay circuit without being affected by its duty, and becomes complementary clock signals P1 to CP6, etc. As a result, the margin of the clock signal is correspondingly expanded, and the speed of the high-speed logic integrated circuit device is promoted.

As shown in the above embodiment, by applying the present invention to a high-speed logic integrated circuit device including a variable delay circuit,
The following effects can be obtained.

That is, (1) In a variable delay circuit or the like of a high-speed logic integrated circuit device, all data 1-circuits related to the clock transmission path are configured by a differential gate circuit connecting at least one pair of complementary input terminals and complementary output terminals. By doing so, it is possible to transmit the clock fd etc. without affecting its duty.

(2j) According to the above item (1), it is possible to expand the margin of the clock signal, etc., and stabilize the operation of the variable delay circuit.

+3) According to the above-mentioned +11 and (2) terms, it is possible to shorten the period of a clock signal, etc., and to promote an increase in the cycle time of a high-speed logic integrated circuit device, etc. including a variable delay circuit.

Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that this invention is not limited to the above Examples and can be modified in various ways without departing from the gist thereof. For example, in FIG. 1, the number of delay circuits forming the variable delay circuit is arbitrary. Furthermore, the number of capacitive gate circuits provided in each delay circuit is arbitrary for each delay circuit, and these capacitive gate circuits may be replaced with ordinary capacitive means, such as driving gates for distributing clock signals. The circuit can be expanded or reduced, and the lid follower circuit FF4 to FF? The Cronk frequency divider circuit consisting of the drive gate circuit DG7 and the drive gate circuit DG7 is not essential.

The variable delay circuit may be one that transmits a complementary signal other than the complementary clock signal. In FIG. 2, each drive gate circuit can be provided with three or more output follower circuits, It is also possible to replace the drive gate circuit with a plurality of drive gate circuits including only one output main interfollower circuit. A plurality of transistors provided corresponding to each output lid follower circuit are multi-emitter type transistors.
can be replaced with 2 transistors. In Figures 2 and 3, the constant current source provided as a load means for each output emitter follower circuit may be a simple resistor, and each gate circuit is basically a logic gate circuit other than an ECL circuit. Furthermore, the block configuration of the variable delay circuit shown in FIG. 1 and the specific circuit configuration and selection of the drive gate circuit and selection gate circuit shown in FIGS. Various embodiments such as combinations of control signals etc. can be adopted.

The above explanation has mainly focused on the case where the invention made by the present inventor is applied to a variable delay circuit of a high-speed logic integrated circuit device, which is the field of application in which the invention was made.
The present invention is not limited thereto, and can be applied to, for example, a normal delay circuit with a fixed delay time or various digital integrated circuit devices equipped with a delay circuit. Can be widely used in equipment.

〔Effect of the invention〕

A brief explanation of the effects obtained by typical inventions disclosed in this application is as follows. That is, in a variable delay circuit or the like of a high-speed logic integrated circuit device, all gate circuits related to a clock transmission path are constructed by differential gate circuits having at least one pair of complementary input terminals and complementary output terminals. As a result, clock signals and the like can be transmitted without affecting their duty, so that the margin of clock signals and the like can be correspondingly expanded, and speeding up of high-speed logic integrated circuit devices and the like can be promoted.

[Brief explanation of drawings]

FIG. 1 is a circuit block diagram showing an embodiment of a variable delay circuit of a high-speed logic integrated circuit device to which the present invention is applied, and FIG. 2 is an example of a drive gate circuit included in the variable delay circuit of FIG. 3 is a circuit diagram showing an embodiment of the selection gate circuit included in the variable delay circuit of FIG. 1; FIG. 4 is a circuit diagram of an embodiment of the variable delay circuit of FIG. 1. 55 is a signal waveform diagram showing an example of a variable delay circuit of a high-speed logic integrated circuit device developed by the inventors prior to this invention; FIG. 6 is a signal waveform diagram showing the variable delay of FIG. FIG. 2 is a circuit block diagram showing an example of a circuit. RGI~RG2...Input gate circuit, DGI~DG1
3... Drive gate circuit, CGI to CG12... Capacitance gate circuit, SGI to SG3... Selection gate circuit, N
0GI~N0G6...Nor gate circuit, FFl-FF
l0...Flip-flop circuit. T'1-T22...NPN type bipolar transistor, R1-R12...Resistor. Figure 2 Figure 2

Claims (1)

[Claims] 1. A first differential gate circuit having complementary input terminals and complementary output terminals and transmitting complementary signals; and a first differential gate circuit coupled to non-inverting and inverting output terminals of the first differential gate circuit; 1. A semiconductor integrated circuit device comprising: a delay circuit including a capacitance means, and a second differential gate circuit receiving a complementary output signal of the first differential gate circuit. 2. The second differential gate circuit has two sets of complementary input terminals and is a selection gate that selectively transmits a complementary signal supplied to one or the other of the complementary input terminals according to a predetermined selection control signal. Claim 1: A circuit, wherein a plurality of the delay circuits are substantially connected in series to constitute a variable delay circuit.
The semiconductor integrated circuit device described in . 3. The semiconductor integrated circuit device according to claim 1 or 2, wherein the semiconductor integrated circuit device is a high-speed logic integrated circuit device, and the complementary signal is a clock signal.