JPH03798B2 - - Google Patents
Info
- Publication number
- JPH03798B2 JPH03798B2 JP57189847A JP18984782A JPH03798B2 JP H03798 B2 JPH03798 B2 JP H03798B2 JP 57189847 A JP57189847 A JP 57189847A JP 18984782 A JP18984782 A JP 18984782A JP H03798 B2 JPH03798 B2 JP H03798B2
- Authority
- JP
- Japan
- Prior art keywords
- wiring board
- chip
- board
- rigid
- mounting
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000000853 adhesive Substances 0.000 claims description 3
- 230000001070 adhesive effect Effects 0.000 claims description 3
- 239000000758 substrate Substances 0.000 description 15
- 239000000919 ceramic Substances 0.000 description 5
- 238000000034 method Methods 0.000 description 5
- 239000000463 material Substances 0.000 description 2
- 238000005476 soldering Methods 0.000 description 2
- 230000035882 stress Effects 0.000 description 2
- 239000004593 Epoxy Substances 0.000 description 1
- ISWSIDIOOBJBQZ-UHFFFAOYSA-N Phenol Chemical compound OC1=CC=CC=C1 ISWSIDIOOBJBQZ-UHFFFAOYSA-N 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 238000001816 cooling Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 230000008646 thermal stress Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
Landscapes
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
- Combinations Of Printed Boards (AREA)
- Wire Bonding (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
Description
【発明の詳細な説明】
本発明はチツプ部品搭載用基板に係るものであ
つて、その目的とするところは電子部品の高密度
実装に適した基板を提供することにある。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a board for mounting chip components, and its object is to provide a board suitable for high-density mounting of electronic components.
電子部品を使用した機器の小型化、高速演算処
理化が進むにつれてLSI等の電子部品の高密度実
装化が切望されている。LSI等の高密度実装方法
としてはLSIチツプの基板への直付けLSIチツプ
をセラミツク等のチツプキヤリヤに載せこのチツ
プキヤリヤを基板へリードレスで接続する等の方
法がある。 BACKGROUND ART As devices using electronic components become smaller and require higher-speed processing, there is a strong need for higher-density packaging of electronic components such as LSIs. High-density mounting methods for LSI and the like include methods such as directly attaching an LSI chip to a board, placing the LSI chip on a chip carrier such as ceramic, and connecting this chip carrier to the board in a leadless manner.
従来、この目的のための基板としてセラミツク
基板が用いられてきたが、セラミツク基板は誘電
率が大きい、大きな基板が再現性よくできない、
加工が難しい等の欠点がある。 Conventionally, ceramic substrates have been used as substrates for this purpose, but ceramic substrates have a high dielectric constant, and large substrates cannot be manufactured with good reproducibility.
It has drawbacks such as difficulty in processing.
一方、紙基材フエノール積層板やガラス基材エ
ポキシ積層板等のリジツドな有機基板は、セラミ
ツク基板よりも誘電率が小さく、加工性にも優れ
ているが、シリコンやセラミツクとの熱膨張係数
の差が大きいために冷熱サイクルを受けた際に基
板とチツプとの接合部に応力が集中し接合部が疲
労破壊を起こすため実際上使用できないという問
題がある。 On the other hand, rigid organic substrates such as paper-based phenol laminates and glass-based epoxy laminates have a lower dielectric constant and better workability than ceramic substrates, but their thermal expansion coefficients differ from those of silicon and ceramics. Due to the large difference, stress is concentrated at the joint between the substrate and the chip when subjected to cooling and heating cycles, causing fatigue failure at the joint, making it practically unusable.
これらの欠点を解決するため鋭意検討した結果
チツプ部品搭載のための回路を形成したフレキシ
ブル印刷配線板とリジツドな配線板とが、より小
さな配線板の全部または大部分がより大きな配線
と重なるように重なり合わされ、重なり部分にお
いて多角形を構成できるように選ばれた数点を含
む３点以上でかつチツプ部品搭載面下で両配線板
間に非接着面が存在し、チツプ部品搭載面下でフ
レキシブル印刷配線板がたるまないような条件下
で固定され、固定点の一部ないしは全部によつて
両配線板上の回路が電気的に接続されていること
を特徴とするチツプ部品搭載用基板を使用すれば
上記欠点を解決できることをみい出した。 As a result of intensive studies to solve these shortcomings, we decided to combine the flexible printed wiring board and rigid wiring board that form the circuit for mounting chip components so that all or most of the smaller wiring board overlaps with the larger wiring. A non-adhesive surface exists between both wiring boards under the chip component mounting surface at three or more points, including several points selected to overlap and form a polygon in the overlapping portion, and a flexible surface exists under the chip component mounting surface. Uses a substrate for mounting chip components, which is fixed under conditions such that the printed wiring board does not sag, and the circuits on both wiring boards are electrically connected by some or all of the fixing points. We have found that the above drawbacks can be overcome by doing this.
すなわちリジツドな印刷配線板に部分的に固定
されたフレキシブル印刷配線板にチツプ部品を搭
載することによつて熱膨張係数の違いによつて生
じる応力を緩和することができるため接続信頼性
が向上するものである。しかも有機基板を用いる
ために誘電率が低く、加工も容易である。 In other words, by mounting chip components on a flexible printed wiring board that is partially fixed to a rigid printed wiring board, it is possible to alleviate stress caused by differences in thermal expansion coefficients, improving connection reliability. It is something. Moreover, since an organic substrate is used, the dielectric constant is low and processing is easy.
また全体がフレキシブル印刷配線板で構成され
ていては重量部品を搭載できない。全体が柔軟で
はケースに保持した場合不安定である。バツクボ
ードを利用しての３次元構造がとれないため全体
がコンパクト化できないという問題があるがリジ
ツドな印刷配線板を併用するとこれらの欠点も解
消できる。 Furthermore, if the entire board is made of a flexible printed wiring board, heavy components cannot be mounted on it. If the entire body is flexible, it will be unstable if held in a case. There is a problem that the entire structure cannot be made compact because a three-dimensional structure cannot be obtained using a back board, but these drawbacks can be overcome by using a rigid printed wiring board in combination.
以下、図面を参照して本発明の一実施例を詳細
に説明する。 Hereinafter, one embodiment of the present invention will be described in detail with reference to the drawings.
第１図に本発明の基板上にチツプキヤリヤ１を
搭載した斜視図を示した。チツプキヤリヤ搭載用
回路５を形成したフレキシブル配線板２はリジツ
ドな多層配線板３に接続ピン４によつて電気的に
接続される。フレキシブル配線板２の材質ははん
だ接続温度に耐えられるものなら何でもよいがポ
リイミドフイルムが好ましい。リジツドな多層配
線板３の材質についても特に制限はないが、外層
回路表面は湿気や薬品による回路の損傷、短絡を
防ぐためにオーバーコートされるのが望ましい。
フレキシブル配線板２とリジツド配線板３の電気
的接続方法についても特に制限はなく、第２図に
示した様にピン４によつて接続してもよいし、ハ
トメによつて接続してもよいし、またはんだによ
つて接続してもよい。またフレキシブル配線板２
とリジツド配線板３の物理的な固定が接続ピン４
のみによつては不十分な場合には電気的に無関係
な位置で固定ピン６によつて補強してもよいが、
多角形を構成するように選ばれた数点で補強す
る。 FIG. 1 shows a perspective view of a chip carrier 1 mounted on a substrate according to the present invention. A flexible wiring board 2 on which a chip carrier mounting circuit 5 is formed is electrically connected to a rigid multilayer wiring board 3 through connection pins 4. The flexible wiring board 2 may be made of any material as long as it can withstand the soldering temperature, but polyimide film is preferred. There are no particular restrictions on the material of the rigid multilayer wiring board 3, but it is desirable that the outer layer circuit surface be overcoated to prevent circuit damage and short circuits caused by moisture and chemicals.
There is no particular restriction on the electrical connection method between the flexible wiring board 2 and the rigid wiring board 3, and the connection may be made by pins 4 as shown in FIG. 2, or by eyelets. However, they may be connected by soldering. Also, flexible wiring board 2
The physical fixation of the rigid wiring board 3 and the connecting pin 4
If this is insufficient, it may be reinforced with a fixing pin 6 at an electrically unrelated position.
Reinforce with several points selected to form a polygon.
フレキシブル配線板２の大きさは特に制限はな
くフレキシブル配線板２がリジツド配線板３より
も小さい場合にはリジツド配線板３の空いた部分
にはデイスクリート部品等を搭載してもよい。第
１図にはフレキシブル配線板２上にはチツプキヤ
リヤ１は１個しか搭載されていないが、チツプ部
品の搭載数についてはもちろん制限はない。 There is no particular restriction on the size of the flexible wiring board 2, and if the flexible wiring board 2 is smaller than the rigid wiring board 3, discrete components or the like may be mounted in the vacant portion of the rigid wiring board 3. Although only one chip carrier 1 is mounted on the flexible wiring board 2 in FIG. 1, there is of course no limit to the number of chip components mounted.
本発明の基板上へのチツプ部品の搭載方法につ
いても特に制限はないが、チツプ部品搭載面下の
フレキシブル配線板２とリジツド配線板３の間に
は非接着面が存在しなければならず、好ましくは
はんだリフロー法により搭載される。チツプ部品
の搭載順序は、リジツド配線板に固定されたフレ
キシブル配線板にチツプ部品を搭載してもいい
し、フレキシブル配線板に前もつてチツプ部品を
搭載した後、リジツド配線板に固定してもよい。 There are no particular restrictions on the method of mounting chip components on the substrate of the present invention, but there must be a non-adhesive surface between the flexible wiring board 2 and the rigid wiring board 3 below the chip component mounting surface. Preferably, it is mounted by a solder reflow method. The order in which chip components are mounted can be either mounted on a flexible wiring board that is fixed to a rigid wiring board, or mounted on a flexible wiring board first and then fixed on a rigid wiring board. good.
第１図にはチツプ部品の１例としてチツプキヤ
リヤを示してあるが、チツプ部品としては抵抗や
コンデンサー等のチツプ部品や、LSIチツプその
ものでもよいことはもちろんである。 Although FIG. 1 shows a chip carrier as an example of a chip component, it goes without saying that the chip component may also be a resistor, a capacitor, etc., or an LSI chip itself.
本発明の基板は、チツプ部品の高密度実装に適
しており、この基板を用いることによってチツプ
部品の線膨張係数と基板の線膨張係数が異なるこ
とから発生する熱応力は、部分的に固定されたフ
レキシブル配線板のフレキシビリテイーによつて
緩和されるためチツプ部品のはんだ接続部の接続
信頼性は飛躍的に向上する。また有機基板を使用
するため、加工性に優れており、誘電率も低いこ
とから伝送速度の高速化にも有利である。 The substrate of the present invention is suitable for high-density mounting of chip components, and by using this substrate, the thermal stress generated due to the difference in linear expansion coefficient of the chip component and that of the substrate is partially fixed. The reliability of the soldered joints of chip components is dramatically improved because the flexibility of the flexible wiring board reduces this problem. Furthermore, since it uses an organic substrate, it has excellent processability and has a low dielectric constant, which is advantageous for increasing transmission speed.
第１図は本発明に従つて形成されたチツプキヤ
リヤを搭載した基板の斜視図であり、第２図は第
１図の基板の断面図である。
符号の説明、１……チツプキヤリヤ、２……フ
レキシブル配線板、３……リジツド配線板、４…
…接続ピン、５……回路、６……固定ピン、７…
…スルーホール、８……バイアホール、９……内
層回路。
FIG. 1 is a perspective view of a board carrying a chip carrier formed in accordance with the present invention, and FIG. 2 is a cross-sectional view of the board of FIG. Explanation of symbols, 1...Chip carrier, 2...Flexible wiring board, 3...Rigid wiring board, 4...
...Connection pin, 5...Circuit, 6...Fixed pin, 7...
...Through hole, 8... Via hole, 9... Inner layer circuit.
Claims (1)
キシブル印刷配線板とリジツドな配線板とが、よ
り小さな配線板の全部または大部分がより大きな
配線板と重なるように重なり合わされ、重なり部
分において多角形を構成できるように選ばれた数
点を含む３点以上でかつチツプ部品搭載面下で両
配線板間に非接着面が存在し、チツプ部品搭載面
下でフレキシブル印刷配線板がたるまないような
条件下で固定され、固定点の一部ないしは全部に
よつて両配線板上の回路が電気的に接続されてい
ることを特徴とするチツプ部品搭載用基板。1 A flexible printed wiring board on which a circuit for mounting chip components is formed and a rigid wiring board are overlapped so that all or most of the smaller wiring board overlaps the larger wiring board, and a polygon is formed in the overlapped part. Conditions where there is a non-adhesive surface between both wiring boards under the chip component mounting surface, and the flexible printed wiring board does not sag under the chip component mounting surface. A circuit board for mounting a chip component, characterized in that circuits on both wiring boards are electrically connected by part or all of the fixing points.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57189847A JPS5978590A (en) | 1982-10-28 | 1982-10-28 | Substrate for carrying chip part |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57189847A JPS5978590A (en) | 1982-10-28 | 1982-10-28 | Substrate for carrying chip part |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5978590A JPS5978590A (en) | 1984-05-07 |
| JPH03798B2 true JPH03798B2 (en) | 1991-01-08 |
Family
ID=16248189
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP57189847A Granted JPS5978590A (en) | 1982-10-28 | 1982-10-28 | Substrate for carrying chip part |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5978590A (en) |
Families Citing this family (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6122378U (en) * | 1984-07-16 | 1986-02-08 | 富士通テン株式会社 | Connection structure of flexible printed wiring board |
| US4855872A (en) * | 1987-08-13 | 1989-08-08 | General Electric Company | Leadless ceramic chip carrier printed wiring board adapter |
| JP2740028B2 (en) * | 1989-12-20 | 1998-04-15 | 株式会社東芝 | Multilayer printed wiring board |
| JP2008091638A (en) | 2006-10-02 | 2008-04-17 | Nec Electronics Corp | Electronic equipment, and manufacturing method thereof |
| JP5510877B2 (en) * | 2008-10-07 | 2014-06-04 | 株式会社リコー | Sensor module and sensing device |
| JP7197448B2 (en) * | 2019-09-06 | 2022-12-27 | ルネサスエレクトロニクス株式会社 | electronic device |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5640685B2 (en) * | 1970-04-13 | 1981-09-22 |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5640685U (en) * | 1979-09-04 | 1981-04-15 |
-
1982
- 1982-10-28 JP JP57189847A patent/JPS5978590A/en active Granted
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5640685B2 (en) * | 1970-04-13 | 1981-09-22 |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5978590A (en) | 1984-05-07 |
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