JPH0377375A - High speed semiconductor device - Google Patents

Abstract

PURPOSE:To obtain a high speed semiconductor device which has little scattering between valleys, facilitates high speed operation and has ensured voltage withstand characteristics between the base and the collector by a method wherein a collector barrier is formed in a collector barrier layer with a potential barrier provided by a doped layer and a potential barrier provided by a inclined composition mixed crystal layer. CONSTITUTION:An injected electron (e<->) is transmitted through an n<+>-type GaAs base layer 34 in a ballistic manner and crosses over the collector barrier 59 of a collector barrier layer 32 and reaches an n<+>-type GaAs collector layer 24 to form a collector current Ic. At that time, the collector barrier 59 has a shape of trapezoid whose height is about 0.28 eV. Further, as the height about 0.28 eV of the collector barrier 59 is defined by an inclined composition AlxGa1-xAs layer at the boundary between the collector barrier layer 32 and the n<+>-type GaAs base layer 34, even if a base-collector voltage VBC is applied, the height is not degraded. Therefore, a withstand voltage between the base and the collector can be ensured and the voltage withstand characteristics of the device are not deteriorated.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a high-speed semiconductor device, and more particularly to a three-terminal high-speed semiconductor device having negative resistance characteristics using resonant tunneling effect.

[Prior Art] Conventionally, there have been voltage-controlled negative resistance elements such as Esaki diodes, but all of these are two-terminal elements, and a three-terminal negative resistance element has not been realized.

On the other hand, recently, research has been conducted on semiconductor devices that utilize the resonant tunneling effect, and three-terminal high-speed semiconductor devices having negative resistance characteristics have been proposed.

First, the resonance tunnel effect will be explained using FIG. 5.

Between the semiconductor layers 62, 64 there is a barrier 66, 68 which can be tunneled by resonant tunneling.
A superlattice layer is formed of the quantum well 70 sandwiched between the resonant tunnel barriers 66 and 68. At this time, discrete energy levels, that is, resonance levels, are formed in the quantum well 70, and here, the lowest co-III! Only level E1 is illustrated.

Now, as shown in FIG. 5(a), the semiconductor layer 62.
64, the resonance level E1 of the quantum well 70 is higher than the energy of the electron e- of the semiconductor layer 62, and the electron e- injected from the semiconductor layer 62
is reflected in the quantum well region and cannot reach the semiconductor layer 64.

Next, as shown in FIG. 5(b), the semiconductor layer 62
．． A bias is further applied between the semiconductor layer 64 and the resonance level E1 so that the energy of the electron e- of the semiconductor layer 62 becomes equal to the resonance level E1. In reality, the energy of electrons has a certain distribution, so the energy distribution of electrons e- in the semiconductor layer 62 may be made to approach the resonance level E1. At this time, electrons e- injected from the semiconductor layer 62 pass through the resonant tunnel barriers 66 and 68 due to the resonant tunnel effect and reach the semiconductor layer 64.

Next, as shown in FIG. 5(e), the semiconductor layer 62
．． If the bias between 64 is further increased, the semiconductor layer 6
The resonance level E1 becomes lower than the energy of the second electron, and the electrons e'''' injected from the semiconductor layer 62 again cannot reach the semiconductor layer 64.

In this manner, the resonant tunnel barriers 66, 68 have the property of selectively transmitting only electrons with an energy matching the resonance level E, and reflecting electrons with other energies.

Therefore, the relationship between the bias voltage (2) and the current (2) applied to the resonant tunnel barriers 66, 68 exhibits negative resistance characteristics, as shown in FIG.

That is, as the bias voltage V is gradually increased from the state corresponding to FIG. 5(a), the current I also increases accordingly. Corresponding to FIG. 5(b), when the bias voltage V reaches the resonant voltage Vp=2E1/q (where q represents the electron charge), the current I becomes maximum. When the bias voltage V is further increased, the current I decreases in contrast, corresponding to FIG. 5(c).

As a semiconductor device that utilizes such a resonant tunneling effect, a semiconductor device such as R) (ET (Resona Tunneling) as shown in FIG.
nt-tunneling Hot Electron
There is a T "ansistor".

This RHET uses a resonant tunnel barrier as an emitter barrier. That is, in FIG. 7(a), the n+ type GaAs emitter layer 72 and the n4' type GaAs
GaAs is used as an emitter barrier between the base layer 74 and the base layer 74.
/AjGaAs 4M heterostructure 76.78 and these resonant tunnel barriers 76.
A quantum well 80 sandwiched between quantum wells 78 and 78 is formed.

In addition, an n4' type GaAs base layer 74 and an n+ type GaAs base layer 74
s collector layer 82, AjxGa+, A, s (
x=0.24) A collector barrier layer 84 is provided to form a collector barrier 85.

Now, as shown in FIG. 7<b>, a voltage VB is applied between the emitter and the base to match the energy of the electron e- in the n'' type GaAs emitter layer 72 to the resonance level E1 of the quantum well 80. Then, n+ type Ga is transmitted from the n4 type QaAs layer 72 through the resonant tunnel barrier 76.78.
As is implanted into the As base layer 74. Of the injected electrons e-, the electrons e- that have traveled through the n1 type GaA,s base layer 74 in a parisistic manner pass through the collector barrier 8.
5 to form a collector current. At this time, the collector current also exhibits negative resistance characteristics due to the negative resistance characteristics caused by the resonant tunnel barriers 76 and 78.

However, in this conventional RHE "?", the collector barrier 85 is A 'J x G a + -x A
s, the electron e- passing through the collector barrier 85 is A J xG a + -x A
Inter-valley scattering occurs to the upper valley L present in the s collector barrier layer 74. If the potential of the valley L is shown by a broken line in FIG. 7(b), for example, the collector barrier 85
To make the height of about 0-27eV, A, Q, Ga1-X
It is necessary that the AI composition ratio of the AS collector barrier layer 74 is
This is considerably smaller than the energy difference between the valleys r and L in the base layer 74, which is about 0928 eV.

Therefore, in order to increase the height of the collector barrier 85,
. G a l-x A of collector barrier layer 74
As the composition ratio X increases, the energy difference between valleys r and L decreases. Furthermore, as is clear from FIG. 7(b), in the @ range of the 82 pieces of the 4+ type GaAs collector layer within the 7 layers of the AE x Gar-x As collector barrier layer, the degree of occurrence of several layers between valleys is large.

In this way, A, l! When inter-valley scattering occurs from the valley r to the upper valley in the xG a r-x A S collector barrier layer 74, there is a problem that the speed of passing electrons decreases.

In order to solve this problem, as shown in FIG. 8, a RHEET using a Bote-Char barrier formed by Brenner toping as a collector barrier is considered.

That is, the n" type GaAs base layer 74 and the n+ type GaAs
A p+ type GaAs collector barrier layer 86 doped with acceptor impurities is interposed between the s collector layer 82 and the s collector layer 82.
will be established. By this Brenner toping, p medium Ga
A triangular potential barrier is formed in the As collector barrier N86.

In the collector barrier 87 formed by Brenner toping, unlike the collector barrier 85 shown in FIG. 7, the constituent material of the barrier layer is GaAs and is not a mixed crystal containing AI, so that the energy difference between the valleys r and L is approximately 0. .28eV
Therefore, inter-valley scattering can be suppressed to a small value.

However, in this RHET, as shown by the broken line in FIG. 8, when the voltage Vac is applied between the base and collector, the height of the collector barrier 87 also increases to Vac.
It decreases by sc/2. As the height of the collector barrier 87 decreases, the breakdown voltage between the base and the collector decreases, resulting in a problem that the breakdown voltage characteristics of the RHET deteriorate.

[Problems to be Solved by the Invention] As described above, in the conventional RHET, when GaAs is used as the semiconductor material and the collector barrier layer is formed from a ternary mixed crystal such as AjGaAs,
There was a problem in that the energy difference between the valleys r and L becomes small depending on the composition of j, and inter-valley scattering occurs from the valley r to the upper valley L, thereby slowing down the speed of passing electrons.

Furthermore, when the collector barrier layer is formed by Brenner doping, there is a problem in that the breakdown voltage between the base and the collector is lowered, and the breakdown voltage characteristics of the device are deteriorated.

Therefore, the present invention enables high-speed operation by reducing inter-valley scattering in the collector barrier layer, and
The object of the present invention is to provide a high-speed semiconductor device as a negative resistance 3@ element that utilizes the resonant tunneling effect and can ensure the withstand voltage characteristics between the base and the collector.

[Means to solve the problem] The present invention will be explained in detail with reference to FIG.

FIG. 1 is a diagram showing the shape of the conduction band bottom of the energy band of a high-speed semiconductor device according to the present invention.

Note that a case will be described here in which GaAs is used as the semiconductor material.

Between the emitter layer 2 and base layer 4 made of GaAs,
A superlattice layer consisting of a GaAs quadruple j GaAs quadruple heterostructure is provided, forming a resonant tunnel barrier 6.8 as an emitter barrier and a quantum well 10 sandwiched between these resonant tunnel barriers 6.8. Discrete energy levels, that is, resonance levels are formed in this quantum well 10, but only the lowest resonance level E1 is illustrated here.

By the way, the base layer 4 and the collector 11 made of GaAs
When a p+ type GaAs layer as a doping layer formed by Brenner doping of acceptor impurities is provided as a collector barrier N14 between the collector barrier N14 and the collector impurities N14, the height φ0. triangular potential barrier 1
6 is formed by spreading out on both sides.

Further, the collector barrier layer 14 is provided with 8 layers of A j
If the slope is made such that the N composition ratio is formed.

In the present invention, the collector barrier 20 is formed by combining the potential barriers 16 and 18 shown in FIGS. 1(a) and 1(b), respectively. That is, the collector barrier layer 14 has a p+ type GaAs layer and a composition ratio of X
An AIX Gai-x As layer having an inclination is provided to form a triangular potential barrier 16 with a height φ shown in FIG. A triangular bodential barrier 18 with a height of φ8□ as shown in FIG. 1(b) is formed on the base half, and the potential barrier 16.
By making 82 substantially equal, a trapezoidal collector barrier 20 is formed as shown in FIG. 1(e).

[Function 1] When voltages V and c are applied between the base and collector of a high-speed semiconductor device having the shape of the conduction band bottom of the energy band as shown in FIG. 1(e), as shown in FIG. 1(d) As shown in , the height φ11 of the potential barrier due to the p+ type GaAs layer decreases, but Aj! x G a +-x
The height φs2 of the potential barrier at the boundary with the base layer 4 shaped by the As layer does not decrease, so the breakdown voltage between the base and the collector is ensured, and the breakdown voltage characteristics as an element are not deteriorated.

Further, in the collector barrier layer 14. 11
1 to X AsJil exists only in the base side half of the collector barrier layer 14, and furthermore, since the composition ratio X of Aj is sloped so as to decrease toward the collector side,
The energy difference between the valleys r and L in the collector barrier layer 14 is suppressed from becoming small. Therefore, inter-valley scattering is also suppressed.

Furthermore, since the AJ composition is not included in the collector side half where inter-valley scattering occurs to a high degree, the effect of suppressing inter-valley scattering is large.

[Example] The present invention will be specifically described below based on an illustrative example.

FIG. 2 is a cross-sectional view showing a high-speed semiconductor device according to an embodiment of the present invention.

On the semi-insulating GaAs substrate 22, the thickness is 3000 mm, the carrier concentration N o = L x 10 "c 1ri-'
An n4 type GaAs collector layer 24 is formed. On this n+ type Ga, A s collector 424, there is a thickness l.

A non-doped GaAs layer 26 with a thickness of approximately 3000 nm, carrier concentration NA
=4X ], Ocm-' p-type GaAs layer 28, and non-doped compositionally graded AjxGa,- to a thickness of 1000 as a compositionally graded mixed crystal layer.

As layers 30 are laminated in order to form a collector barrier layer 32. And on this collector barrier layer 32,
Thickness 200 people, carrier concentration No = 5X10"am-'
An n+ type GaAs base layer 34 is formed.

At this time, the composition gradient Aj x Ga +-x A
The 8 layer 30 has an A' composition ratio x=0.24 at the boundary with the n4 type GaAs base layer 34, and has a p
Composition ratio x=0 at the boundary with + type G a A s N 28
, and it changes almost linearly during that time.

Further, on the n'' type GaAs base layer 34, a non-doped GaAs buffer layer 36 with a thickness of 50A is interposed, and a thickness of 3
0 non-doped A j xG a + -x As
(x=0.5) barrier layer 38, a 30-thick non-doped GaAs single well layer 40, and a 30-thick non-doped Aix Gat-X As (x=0.5) barrier layer 42 are laminated in this order. As a result, an upper transmitter barrier NJ44 having a resonant tunnel barrier structure is formed.

Further, on this emitter barrier layer 44, a non-doped GaAs buffer layer 46 with a thickness of 30 mm is interposed, and a layer 46 with a thickness of 30 mm is formed.
An n+ type GaAs emitter layer 48 with a carrier density No. 000 and a carrier concentration No=1×10 18 cm−′ is formed.

and an n1 type GaAs collector layer 24, an n+ type GaAs collector layer 24;
A collector tfffi50 and a base electrode 52 are disposed on the base layer 32 and the n+ type GaAs emitter layer 48, respectively.
and an emitter electrode 54 are provided.

Next, the operation will be explained using FIG.

FIG. 3 is a diagram showing the shape of the conduction band bottom of the energy band of the high-speed semiconductor device of FIG. 2.

A base collector voltage VlIE is applied between the n1 type GaAs processed layer 48 and the n+ type GaAs base layer 32, and the base collector voltage VlIE is applied between the n+ type GaAs base layer 32 and the n+ type GaAs base layer 32.
There is a base collector voltage V8C between the s collector layer 24 and
is applied.

Now, the base-emitter voltage V! 12 is small, as shown in FIG.
Since the resonance level E1 of the quantum well 58 sandwiched between the resonance tunnel barriers 56 and 57 in
Electrons e- injected from the quantum well layer 48 are reflected in the quantum well region and form n+ type GaA,s collector layer 24.
Therefore, the collector current Ic
is extremely small.

Next, as shown in FIG. 3(b), the base-emitter voltage VIIE is increased so that the energy of the electron e- of the n" type GaAs emitter layer 48 becomes equal to the resonance level B1. To be precise, if the energy distribution of electrons e in the n+ type GaAs emitter layer 48 is made to be on the resonance level E1, the electrons e- injected from the n+ type GaAs emitter layer 48 will be affected by the resonance tunnel effect. Resonant L-channel barrier 56.5 of emitter barrier layer 44
7 and is implanted into the n+ type GaAs base 132. Then, the injected electrons e- pass through the n+ type GaAs base layer 32 in a parisistic manner, and pass through the collector barrier 59 of the collector barrier layer 32 to form n4' type GaAs base layer 32.
It reaches the As collector layer 24 and forms a collector current He.

At this time, the collector barrier 59 is the ρ“ type GaAs layer 2
8 and compositional gradient A j x G a + −x A 8
The layer 30 forms a trapezoidal shape with a height of about 0.28 eV. And the collector barrier layer 32 is made of n+ type GaAs.
At the boundary with the base layer 34, a collector barrier 59
The height of about 0.28 eV is the compositional gradient Aj x Ga
Since it is defined by the +-x As layer 30, it does not decrease even when the base-collector voltage VIC is applied.
Therefore, the breakdown voltage between the base and the collector is ensured, and the breakdown voltage characteristics of the element are not deteriorated.

Furthermore, the composition gradient A j in the collector barrier layer 32
The x G a + -x A 5 layer 30 exists only in the base half of the collector barrier layer 322, and is also inclined7 so that the AN composition ratio X decreases toward the collector side. The energy difference between the valleys r and L in the barrier layer 32 is minimum at about 0.15 eV at the boundary with the n+ type Ga A, s base layer 34,
It gets bigger as the number of collectors increases. 9th,
Inter-valley scattering from valley F to upper valley L is suppressed. Particularly in the collector measurement half where the degree of inter-valley scattering is high, the A1 composition is not included at all, so the energy difference between valleys r-1- is approximately 0°28
eV, which is sufficiently large, and the effect of suppressing inter-valley scattering to the upper valley I- is large.

Next, when the base-emitter voltage V■ is further increased, the energy of the electron e- of the n" type GaAs emitter layer 48 becomes higher than the resonance level E1 and matches, as shown in FIG. 3(c). It disappears and becomes n + type GaAs again.
Electrons e- injected from the emitter layer 48 are reflected by the quantum well region and cannot reach the n+ type GaAs collector layer 24. Therefore, the collector current IC decreases significantly.

This operating characteristic is shown in the graph of FIG.

That is, the relationship between the base-emitter voltage VIIm and the collector current 1c gradually becomes the base-emitter voltage ■ from the state corresponding to FIG. 3(a). As the collector current IC increases, the collector current IC also increases, as shown in Figure 3 (
Corresponding to b), when the base-emitter voltage Veg reaches the resonant voltage VP-2E1/Q, the collector current IC becomes maximum. When the base-emitter voltage VILE is further increased, the collector current increases as shown in FIG. 3(c).

is rapidly decreasing.

In this way, the high-speed semiconductor device shown in FIG.
c) Negative resistance can be obtained between.

As described above, according to this embodiment, the collector barrier layer 32 is not doped with acceptor impurities, and the
a As N 28 and compositional gradient, Il, Gat-
By combining the xAS layers 30 to form the collector barrier 59, the withstand voltage between the base and the collector is ensured, and the energy between the valley r and L in the collector barrier layer 32, which is half the collector measurement, is ensured. Inter-valley scattering can be suppressed by making the difference sufficiently large.

This makes it possible to ensure the breakdown voltage characteristics as an element, and also to sufficiently shorten the transit time of electrons in the collector barrier layer 32, thereby increasing the operating speed.

In addition, in the two-part embodiment, G is used as the semiconductor material.
a A, s, Aj x G a l-x A S as a compositionally graded ternary mixed crystal forming the collector barrier layer.
The present invention is not limited to this material, and can also be applied to the case where other group III-V compound semiconductors and other compositionally graded ternary mixed crystals are used.

[Effects of the Invention] As described above, according to the present invention, in a high-speed semiconductor device in which a resonant tunnel barrier is provided between an emitter layer and a base layer, the collector barrier layer between the base layer and the collector layer is The doping layer includes a doping layer provided inside the collector barrier layer, and a compositionally graded mixed crystal layer provided between the doping layer and the base layer and having a maximum composition ratio near the boundary with the base layer. Since the collector barrier is formed by the potential barrier caused by the crystal and the potential barrier caused by the compositionally graded mixed crystal layer, it is possible to suppress inter-valley scattering by sufficiently increasing the energy difference between the valleys in the collector barrier layer. At the same time, withstand voltage between the base and the collector can be ensured.

Thereby, it is possible to ensure the withstand voltage characteristics of the negative resistance three-terminal element that utilizes the resonant tunnel effect, and to improve the high-speed operation characteristics.

[Brief explanation of drawings]

1 is a diagram illustrating the principle of the present invention; FIG. 2 is a sectional view showing a high-speed semiconductor device according to an embodiment of the present invention; FIG. 3 is a diagram illustrating the operation of the high-speed semiconductor device shown in FIG. 2; FIG. 4 is a graph for explaining the operation of the high-speed semiconductor device in FIG. 2, FIG. 5 is a graph for explaining the conventional high-speed semiconductor device, and FIG. 6 is a graph for explaining the conventional high-speed semiconductor device. The graphs, FIGS. 7 and 8 are diagrams for explaining conventional high-speed semiconductor devices, respectively. In the figure, 2... Emitter layer, 4... Base layer, 6.8, 56, 57.66... Resonant tunnel barrier, ], 0.58.70.80 ...Quantum well, 6 8 8 12 ... Collector layer, 14 ... Collector barrier layer, 16.18 ... Potential barrier, 20.5
9.85.87... Collector barrier, 22...
... Semi-insulating GaAs substrate, 24, 82-- r
l+ type Ga As collector layer, 26...Ga
As layer, 28...ρ1 type Ga As layer, 30 =-
----Composition gradient Aj x G a l-x A, S
Layer, 32...Collector barrier layer, 34.74---n+ type GaAs base layer, 36.46...GaA,s rose layer, 38. 42=...Aj x Ga+-x As barrier layer, 40...GaAs quantum well layer, 44.
...Emitter barrier fake, 48.72...N4 type GaAs emitter layer, 5
0...'fl in the collector, 52...Base electrode, 54...Emitter electrode, 62.64...Semiconductor layer, 84... - Aj x Ga + - x As collector barrier layer, 86...p-type GaAs collector barrier layer. /□It+LeP 20 Collector barrier explanatory diagram of the theory of the present invention Fig. 2 A sectional view showing the high-speed half-body technique in the embodiment of the present invention Fig. 2 +Conductor Technique Summer 0 Movement Mugi Translation 0 Diagram~
'+tr Nre-?

Claims (1)

[Claims] A high-speed semiconductor device having three terminals, an emitter, a base, and a collector, and having a resonant tunnel barrier between the emitter layer and the base layer, comprising: a collector barrier between the base layer and the collector layer; The layer includes a doped layer provided inside the collector barrier layer, and a compositionally graded mixed crystal layer provided between the doped layer and the base layer and having a maximum composition ratio near the boundary with the base layer. A high-speed semiconductor device comprising: a collector barrier in the collector barrier layer formed by a potential barrier formed by the doped layer and a potential barrier formed by the compositionally graded mixed crystal layer.