JPH0377368A - Semiconductor memory device and manufacture thereof - Google Patents
Semiconductor memory device and manufacture thereofInfo
- Publication number
- JPH0377368A JPH0377368A JP1213008A JP21300889A JPH0377368A JP H0377368 A JPH0377368 A JP H0377368A JP 1213008 A JP1213008 A JP 1213008A JP 21300889 A JP21300889 A JP 21300889A JP H0377368 A JPH0377368 A JP H0377368A
- Authority
- JP
- Japan
- Prior art keywords
- conductive layer
- memory device
- semiconductor memory
- insulating film
- data lines
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 35
- 238000004519 manufacturing process Methods 0.000 title claims description 13
- 238000013500 data storage Methods 0.000 claims abstract description 17
- 238000000034 method Methods 0.000 claims abstract description 17
- 239000000758 substrate Substances 0.000 claims abstract description 13
- 230000008018 melting Effects 0.000 claims description 7
- 238000002844 melting Methods 0.000 claims description 7
- 238000000206 photolithography Methods 0.000 claims description 7
- 229910052751 metal Inorganic materials 0.000 claims description 6
- 239000002184 metal Substances 0.000 claims description 6
- 229910021332 silicide Inorganic materials 0.000 claims description 5
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims description 5
- 238000004544 sputter deposition Methods 0.000 claims description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical group [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 4
- 238000005229 chemical vapour deposition Methods 0.000 claims description 4
- 229910052710 silicon Inorganic materials 0.000 claims description 4
- 239000010703 silicon Substances 0.000 claims description 4
- 229910052782 aluminium Inorganic materials 0.000 claims description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 2
- 238000002955 isolation Methods 0.000 abstract description 7
- 230000006641 stabilisation Effects 0.000 abstract 1
- 238000011105 stabilization Methods 0.000 abstract 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 5
- 229910052814 silicon oxide Inorganic materials 0.000 description 5
- 239000003990 capacitor Substances 0.000 description 3
- 238000009413 insulation Methods 0.000 description 3
- 239000002131 composite material Substances 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 230000003071 parasitic effect Effects 0.000 description 2
- 239000003870 refractory metal Substances 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 230000003321 amplification Effects 0.000 description 1
- JRPBQTZRNDNNOP-UHFFFAOYSA-N barium titanate Chemical compound [Ba+2].[Ba+2].[O-][Ti]([O-])([O-])[O-] JRPBQTZRNDNNOP-UHFFFAOYSA-N 0.000 description 1
- 229910002113 barium titanate Inorganic materials 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 229910000449 hafnium oxide Inorganic materials 0.000 description 1
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000003199 nucleic acid amplification method Methods 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- BPUBBGLMJRNUCC-UHFFFAOYSA-N oxygen(2-);tantalum(5+) Chemical compound [O-2].[O-2].[O-2].[O-2].[O-2].[Ta+5].[Ta+5] BPUBBGLMJRNUCC-UHFFFAOYSA-N 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 230000000087 stabilizing effect Effects 0.000 description 1
- 229910001936 tantalum oxide Inorganic materials 0.000 description 1
Abstract
Description
【発明の詳細な説明】
（産業上の利用分野）
本発明は、半導体記憶装置及びその製造方法に係り、特
にデータ蓄積領域（キャパシタ）に蓄積された電荷によ
り情報記憶を行う、ｌトランジスタ／１データ蓄積領域
のメモリセル構造をもつ半導体記憶装置及びその製造方
法に関する。DETAILED DESCRIPTION OF THE INVENTION (Industrial Application Field) The present invention relates to a semiconductor memory device and a method of manufacturing the same, and particularly relates to a semiconductor memory device and a method for manufacturing the same, and particularly to a semiconductor memory device and a method for manufacturing the same. The present invention relates to a semiconductor memory device having a memory cell structure in a data storage area and a method for manufacturing the same.
（従来の技術）
第３図は従来のダイナミックＲＡＭ（ｄＲＡＭ）の断面
図であって、２０は半導体基板、２１は分離領域、２２
はデータ線、２３はノード電極、２４は容量絶縁膜、２
５はプレート電極、２６はデータ蓄積領域。(Prior Art) FIG. 3 is a cross-sectional view of a conventional dynamic RAM (dRAM), in which 20 is a semiconductor substrate, 21 is an isolation region, and 22 is a sectional view of a conventional dynamic RAM (dRAM).
is a data line, 23 is a node electrode, 24 is a capacitive insulating film, 2
5 is a plate electrode, and 26 is a data storage area.
２７はＡ６（アルミニウム）配線である。27 is an A6 (aluminum) wiring.
同図において、ｄＲＡＭのメモリセルは、情報を電荷の
形で保持するデータ蓄積領域２６と、その電荷を外部回
路とやりとりするためのデータ線２２と１図示しないス
イッチングＭＯＳトランジスタとにより構成されている
。In the figure, a dRAM memory cell is composed of a data storage region 26 that holds information in the form of electric charge, a data line 22 that exchanges the electric charge with an external circuit, and a switching MOS transistor (not shown). .
（発明が解決しようとする課Ｍ）
上記のような構成のｄＲＡＭのメモリセルは、増幅作用
が本質的に小さく、その分、低雑音化が重要となる。し
かも高集積・大容量化と共に、メモリセルからの信号電
圧が小さくなり、雑音は大きくなるため、これらの雑音
対策が一層重要となる。(Problem M to be Solved by the Invention) The dRAM memory cell configured as described above has essentially a small amplification effect, and accordingly, it is important to reduce noise. Moreover, as the integration and capacity increase, the signal voltage from the memory cells becomes smaller and the noise becomes larger, so countermeasures against these noises become even more important.
高集積・大容量化と共に雑音が増大する理由の１つとし
て、各種寄生容量の増大による影響があるが、特にデー
タ線間の寄生容量の増大によって生じる雑音はｄＲＡＭ
を作製する上で重要な問題となる〔これらの技術に関し
ては、′″雑誌ニスペクトラム、 Ｖｏｌ、ＯＬ Ｎｏ
、１２１９８８−１２ ｐ、１２日立製作所 伊藤”に
記載がある〕。One of the reasons why noise increases with higher integration and larger capacity is due to the increase in various parasitic capacitances. In particular, the noise caused by the increase in parasitic capacitance between data lines is
[Regarding these techniques, please refer to '''Magazine Nispectrum, Vol. OL No.
, 121988-12 p. 12 Hitachi, Ltd. Ito].
本発明の目的は、雑音の防止を図り、動作の安定化を可
能にした半導体記憶装置及びその製造方法を提供するこ
とにある。SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor memory device that prevents noise and stabilizes its operation, and a method for manufacturing the same.
（課題を解決するための手段）
上記目的を達成するため、本発明は、半導体記憶装置と
して、メモリセルのデータ線間及びデータ線上部に、定
電位に固定できる導電層を設けたことを特徴とし、また
、半導体記憶装置の製造方法として、半導体基板に所定
の構造を形成したメモリセル領域上にデータ線を形成し
、このデータ線間及びデータ線上に第１の絶縁膜と電導
層とを積層形成し、前記導電層に第１の開孔部を写真食
刻法を用いて設け、次に前記導電層上に形成した第２の
絶縁膜上に前記第１の開孔部内部を通って半導体基板中
の前記メモリセル領域に接続したデータ蓄積領域を形成
し、その後、前記データ蓄積領域上に形成した第３の絶
縁膜上に前記導電層に接続するＡＱ配線を形成したこと
を特徴とする。(Means for Solving the Problems) In order to achieve the above object, the present invention provides a semiconductor memory device characterized in that a conductive layer that can be fixed at a constant potential is provided between data lines of a memory cell and above the data lines. Further, as a method for manufacturing a semiconductor memory device, a data line is formed on a memory cell region in which a predetermined structure is formed on a semiconductor substrate, and a first insulating film and a conductive layer are formed between and on the data line. A first opening is provided in the conductive layer using a photolithography method, and then a second insulating film formed on the conductive layer is formed through the inside of the first opening. forming a data storage region connected to the memory cell region in the semiconductor substrate, and then forming an AQ wiring connected to the conductive layer on a third insulating film formed on the data storage region. shall be.
（作 用）
上記手段を採用して、隣接線の電位変化の影響が大きな
各データ線間、及びデータ線の上部に定電位に固定でき
る導電層を設けたことによりデータ線に対する電磁シー
ルドがなされる。(Function) By employing the above means and providing a conductive layer that can be fixed at a constant potential between each data line and above the data line, where the influence of potential changes of adjacent lines is large, electromagnetic shielding for the data line is achieved. Ru.
（実施例） 以下、本発明の実施例を図面に基づいて説明する。(Example) Embodiments of the present invention will be described below based on the drawings.
第１図は本発明による半導体記憶装置の一実施例である
ｄＲＡＭの断面図であって、１はシリコンよりなる半導
体基板、２は分離領域、２ａは下層の絶縁膜、３はデー
タ線、４は第１の絶縁膜、５は導電層、６は第２の絶縁
膜、７は開孔部、８はノード電極、９は容量絶縁膜、１
０はプレート電極、１１は第３の絶縁膜、１２はＡＩ配
線、１３はデータ蓄積領域（キャパシタ）である。FIG. 1 is a cross-sectional view of a dRAM which is an embodiment of a semiconductor memory device according to the present invention, in which 1 is a semiconductor substrate made of silicon, 2 is an isolation region, 2a is an underlying insulating film, 3 is a data line, and 4 1 is a first insulating film, 5 is a conductive layer, 6 is a second insulating film, 7 is an opening, 8 is a node electrode, 9 is a capacitive insulating film, 1
0 is a plate electrode, 11 is a third insulating film, 12 is an AI wiring, and 13 is a data storage region (capacitor).
同図において、所定の分離領域２とスイッチングＭＯＳ
トランジスタ（図示せず）を形成した半導体基板１上に
、下層の絶縁膜２ａを介して所定のデータ線３を形成し
、このデータ線３間及びデータ線３上に第１の絶縁膜４
を介して導電層５を形成している。In the figure, a predetermined isolation region 2 and a switching MOS
A predetermined data line 3 is formed on a semiconductor substrate 1 on which a transistor (not shown) is formed via a lower layer insulating film 2a, and a first insulating film 4 is formed between and on the data line 3.
A conductive layer 5 is formed through the conductive layer 5.
前記導電層５の所定の領域に後述する方法で、開孔部７
が設けられ、導電層５上に第２の絶縁膜６が形成されて
いる。そして、前記開孔部７内部を通り、かつ、半導体
基板１中のメモリセル領域所定部に接続するように第２
の絶縁膜６上には、ノード電極８と容量絶縁膜９とプレ
ート電極１０よりなるデータ蓄積領域１３が形成されて
いる。前記プレート電極１０の上には第３の絶縁膜１１
を介してＡＱ配線１２が形成されている。An opening 7 is formed in a predetermined region of the conductive layer 5 by a method described later.
is provided, and a second insulating film 6 is formed on the conductive layer 5. Then, a second
A data storage region 13 consisting of a node electrode 8, a capacitor insulating film 9, and a plate electrode 10 is formed on the insulating film 6. A third insulating film 11 is provided on the plate electrode 10.
An AQ wiring 12 is formed through the AQ wiring 12.
なお、前記導電層５を定電位に固定するためのＡＪ配線
１２部分はメモリセル周辺領域で形成されるため図示し
ていない。Note that a portion of the AJ wiring 12 for fixing the conductive layer 5 at a constant potential is not shown because it is formed in the peripheral area of the memory cell.
上記のｄＲＡＭのメモリセルは、情報を電荷の形で保持
するノード電極８と容Ｍ′絶縁膜９とプレート電極１０
よりなるデータ蓄積領域１３と、その電荷を外部回路を
やりとりするためのデ〜り線３と、図示しないスイッチ
ングＭＯＳトランジスタにより構成されている。The dRAM memory cell described above consists of a node electrode 8 that holds information in the form of charges, a capacitance M' insulating film 9, and a plate electrode 10.
The data storage area 13 includes a data storage area 13, a data line 3 for transferring the electric charge to and from an external circuit, and a switching MOS transistor (not shown).
上記構成にしたため、配線間の干渉雑音の低減化が必要
な１゜トランジスタ／１データ蓄積領域の構成であるメ
モリセルのデータ線３周囲を定電位に固定できる導電層
５で囲んで電磁シールドしたことになり、雑音の影響を
受れずに安定した動作のｄＲＡＭとなる。With the above configuration, the data line 3 of the memory cell, which has a 1° transistor/1 data storage area configuration that requires reduction of interference noise between wiring lines, is surrounded by a conductive layer 5 that can be fixed at a constant potential for electromagnetic shielding. This results in a dRAM that operates stably without being affected by noise.
第２図（ａ）〜（ｅ）は本発明による半導体記憶装置の
製造方法の・一実施例のＪ：、程を説明するための断面
図である。FIGS. 2(a) to 2(e) are cross-sectional views for explaining steps of an embodiment of the method for manufacturing a semiconductor memory device according to the present invention.
第２図（ａ）において、例えば絶縁膜を用いた理込み分
離法で形成した分離領域２と図示しないスイッチン）ｊ
Ｍ０Ｓトランジスタとを形成した半導体基板１」二に、
高融点金属シリサイドや、そのポリサイドを用いたデー
タ線３を写真食刻法で形成し、その後、データ線３間及
びデータ線３Ｊ：、にＣＶＤ法で形成した酸化シリコン
膜などの第１の絶縁膜４を介してシリコン膜、高融点金
属シリサイド１摸、高融点金屈膜などの導電層５を、例
えばＣＶ’ Ｄ法またはスパッタ蒸着法で形ノ戊する。In FIG. 2(a), for example, an isolation region 2 formed by a rational isolation method using an insulating film and a switch (not shown) are shown.
Semiconductor substrate 1'' on which an M0S transistor is formed;
Data lines 3 made of high melting point metal silicide or its polycide are formed by photolithography, and then a first insulator such as a silicon oxide film is formed between the data lines 3 and between the data lines 3J by CVD. A conductive layer 5 such as a silicon film, a refractory metal silicide 1, or a refractory metal film is formed via the film 4 by, for example, CV'D or sputter deposition.
次に前記導電層５の所定の領域に、この導電層５の上層
と下層を電気的に接続する第Ｉの開孔部７ａをレジスト
１４を用いた写真食刻法で形成する。Next, a first opening 7a for electrically connecting the upper and lower layers of the conductive layer 5 is formed in a predetermined region of the conductive layer 5 by photolithography using a resist 14.
第２図（ｂ）において、前記導電層５上に酸化シリコン
膜などの第２の絶縁膜６をＣＶＤ法で形成し、次に前記
第１の開孔部７８内部の所定の領域の十Ｍの絶縁膜２ａ
ヒ第工、第２の絶縁膜４，６に第２の開孔部７ｂをレジ
スト＋５を用いた写真食刻法で形成する。In FIG. 2(b), a second insulating film 6 such as a silicon oxide film is formed on the conductive layer 5 by a CVD method, and then a predetermined area of 10M is formed inside the first opening 78. Insulating film 2a of
In the second step, second openings 7b are formed in the second insulating films 4 and 6 by photolithography using resist +5.
第２図（ｃ）において、前記第２の絶縁１１’、％ ６
−、、、Ｉ’Ｚに前記第２の開孔部７ｂ内部の所定の領
域を通り、かつ半導体基板１中のメモリセル領域に接続
するノード電極８．容量絶縁膜９．プレート電極１０よ
りなるデータ蓄積領域１３を写真食刻法を用いて形成す
る。In FIG. 2(c), the second insulation 11', % 6
-, , Node electrode 8. passing through a predetermined region inside the second opening 7b to I'Z and connecting to the memory cell region in the semiconductor substrate 1. Capacitive insulation film 9. A data storage region 13 consisting of a plate electrode 10 is formed using photolithography.
この時、前記ノード電極８とプレートｍｔＪｉＡｘｏの
材料に、例えばＣＶＤ法またはスパッタ蒸着法で形成し
た多結晶シリコン、高融点金属シリサイド。At this time, the material of the node electrode 8 and the plate mtJiAxo is, for example, polycrystalline silicon or high melting point metal silicide formed by CVD or sputter deposition.
高融点全屈などの単一膜またはそれらの複合膜を用いる
ことが可能であり、また前記容量絶縁膜９には、熱酸化
法やＣＶＤ法で形成したシリコン酸化膜、ＣＶｉ）法で
形成したシリコン窒化膜、タンタル酸化膜、ハフニウム
酸化膜などの誘電体膜、または例えばスパッタ蒸着法で
形成したチタン酸バリウムなどの強誘電体膜を、単一ま
たはこれらの複合膜にして用いることが可能である。It is possible to use a single film with a high melting point or a composite film thereof, and the capacitor insulating film 9 may be a silicon oxide film formed by a thermal oxidation method or a CVD method, or a silicon oxide film formed by a CVi method. A dielectric film such as a silicon nitride film, a tantalum oxide film, or a hafnium oxide film, or a ferroelectric film such as barium titanate formed by a sputter deposition method can be used alone or as a composite film of these films. be.
そして、前記データ蓄積領域１３のプレート電極ｊＯ上
に、ＣＶＤ法で形成したシリコン酸化膜などの第３の絶
縁膜１１を介して、前記導電層５や他の所定の下層領域
に接続するＡＩ２配線１２を写真食刻法で形１＆すると
所望のｃｉ、ＲＡＭが完成される。Then, on the plate electrode jO of the data storage region 13, an AI2 wiring is connected to the conductive layer 5 and other predetermined lower layer regions via a third insulating film 11 such as a silicon oxide film formed by a CVD method. When 12 is shaped 1& by photolithography, the desired ci and RAM are completed.
なお、本発明は、前記実施例に限られものでなく、例え
ば、データ蓄積領域１３を半導体基板１とデータ線３の
間や、半導体基板１中に形成するなど１種々の変形が可
能である。Note that the present invention is not limited to the embodiments described above, and various modifications can be made, such as forming the data storage region 13 between the semiconductor substrate 1 and the data line 3 or in the semiconductor substrate 1. .
（発明の効果）
本発明によれば、データ線周囲が定電位に固定できる導
電層で囲まれた電磁シールドされるこヒにより、雑音の
防止が図れ、動作が安定化した半導体記憶装置及びその
製造方法を提供できる。(Effects of the Invention) According to the present invention, a semiconductor memory device and its semiconductor memory device are provided with electromagnetic shielding in which the periphery of the data line is surrounded by a conductive layer that can be fixed at a constant potential, thereby preventing noise and stabilizing the operation. We can provide manufacturing methods.
第１図は本発明により半導体記憶装置の一実施例の断面
図、第２図（ａ）、第２図（ｂ）、第２図（ｃ）は本発
明による半導体記憶装置の製造方法の一実施例の工程を
説明するための断面図、第３図は従来例の半導体装置の
断面図である。
１ ・・・半導体基板、 ２ ・・・分離領域、２ａ・
・ 下層の絶縁膜、 ３ ・・・データ線。
４・・・第１の絶縁膜、 ５・・・導電層、６・・・第
２の絶縁膜、 ７，７ａ、７ｂ ・・開孔部、 ８・
・・ノード電極、 ９ ・・・容量絶縁膜、１０・・・
プレート電極、１１・・・第３の絶縁１漠、 】２・・
Ａ、Ｇ配線、 １３ ・・データ蓄積領域、１４．１
５ ・・ レジスト。FIG. 1 is a cross-sectional view of one embodiment of a semiconductor memory device according to the present invention, and FIGS. A cross-sectional view for explaining the steps of the embodiment, and FIG. 3 is a cross-sectional view of a conventional semiconductor device. 1...Semiconductor substrate, 2...Isolation region, 2a.
- Lower layer insulating film, 3...Data line. 4... First insulating film, 5... Conductive layer, 6... Second insulating film, 7, 7a, 7b... Opening portion, 8.
... Node electrode, 9 ... Capacitive insulating film, 10...
Plate electrode, 11...Third insulation 1, ]2...
A, G wiring, 13...Data storage area, 14.1
5... Resist.
Claims (8)
電位に固定できる導電層を設けたことを特徴とする半導
体記憶装置。(1) A semiconductor memory device characterized in that a conductive layer that can be fixed at a constant potential is provided between data lines of memory cells and above the data lines.
請求項（１）記載の半導体記憶装置。(2) The semiconductor memory device according to claim (1), wherein the conductive layer is a silicon film.
を特徴とする請求項（１）記載の半導体記憶装置。(3) The semiconductor memory device according to claim (1), wherein the conductive layer is a high melting point metal silicide film.
る請求項（１）記載の半導体記憶装置。(4) The semiconductor memory device according to claim (1), wherein the conductive layer is a high melting point metal film.
域上にデータ線を形成し、このデータ線間及びデータ線
上に第１の絶縁膜と導電層とを積層形成し、前記導電層
に開孔部を写真食刻法を用いて設け、次に前記導電層上
に形成した第２の絶縁膜上に前記開孔部内部を通って半
導体基板中の前記メモリセル領域に接続したデータ蓄積
領域を形成し、その後、前記データ蓄積領域上に形成し
た第３の絶縁膜上に前記導電層に接続するアルミニウム
配線を形成したことを特徴とする半導体記憶装置の製造
方法。(5) A data line is formed on a memory cell region in which a predetermined structure is formed on a semiconductor substrate, a first insulating film and a conductive layer are laminated between and on the data line, and an opening is formed in the conductive layer. A data storage area is formed by forming a hole using a photolithography method, and then connected to the memory cell area in the semiconductor substrate through the inside of the hole on a second insulating film formed on the conductive layer. 1. A method of manufacturing a semiconductor memory device, comprising: forming an aluminum wiring connected to the conductive layer on a third insulating film formed on the data storage region.
ることを特徴とする請求項（５）記載の半導体記憶装置
の製造方法。(6) The method for manufacturing a semiconductor memory device according to claim (5), wherein the conductive layer is a silicon film formed by a CVD method.
属シリサイド膜であることを特徴とする請求項（５）記
載の半導体記憶装置の製造方法。(7) The method for manufacturing a semiconductor memory device according to claim (5), wherein the conductive layer is a high melting point metal silicide film formed by sputter deposition.
属膜であることを特徴とする請求項（５）記載の半導体
記憶装置の製造方法。(8) The method for manufacturing a semiconductor memory device according to claim (5), wherein the conductive layer is a high melting point metal film formed by sputter deposition.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1213008A JPH0377368A (en) | 1989-08-21 | 1989-08-21 | Semiconductor memory device and manufacture thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1213008A JPH0377368A (en) | 1989-08-21 | 1989-08-21 | Semiconductor memory device and manufacture thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0377368A true JPH0377368A (en) | 1991-04-02 |
Family
ID=16631964
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1213008A Pending JPH0377368A (en) | 1989-08-21 | 1989-08-21 | Semiconductor memory device and manufacture thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0377368A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6384445B1 (en) | 1994-09-26 | 2002-05-07 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor memory device including memory cell transistors formed on SOI substrate and having fixed body regions |
-
1989
- 1989-08-21 JP JP1213008A patent/JPH0377368A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6384445B1 (en) | 1994-09-26 | 2002-05-07 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor memory device including memory cell transistors formed on SOI substrate and having fixed body regions |
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