JPH0376343A - Packet processing equipment - Google Patents

Abstract

PURPOSE:To control packet processing of a binary signal and its output processing in response to an inputted signal by providing an N-bit composing means outputting an input signal as an N-bit parallel data, a signal monitor means and a control means. CONSTITUTION:An input signal 100 is written in each 1-bit memory 10 in an N-bit composing circuit 1 by a timing signal 112, data D0-DN-1 are read simultaneously to compose an N-bit parallel data. Then the parallel data is outputted to an N-bit data bus 300 and a signal monitor circuit 2 via a gate circuit 14 by a control signal 104. The circuit 2 detects a changes in a signal from a sample of the parallel data and outputs a detection signal corresponding to the change to the bus 300. Then the control circuit 3 stops the packet processing of the input signal and its output at a data change obtained via the bus 300 from the circuits 1, 2 while no change in the input signal is decided and applies the packet processing and its output when the input signal has a change. Thus, efficient packet processing is attained.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a packetization device, and particularly to a packetization device that is advantageously applied to a switching equipment or an information processing device, and packetizes 200 million input numbers.

(Prior Art) Conventionally, as this type of device, there is a device called a packet type terminal, for example. A packet-type terminal is a terminal that can directly communicate with a packet-switched network, for example, via a packet-multiplexed transmission path. Specifically, a computer with a packetization function or a computer capable of assembling and
This includes intelligent terminals equipped with microprocessors with disassembly functions.

There are two types of connection classes for data terminal devices in packet switching services including packet type terminals: a partner selection class and a partner fixed class. The communication sequence of the partner selection class is divided into three sequences: a connection sequence, a data transfer sequence, and a disconnection sequence, and packet types required for each sequence phase are prepared.

For example, in the connection phase, a call request packet, an incoming call acceptance packet, and a connection completion packet are output; and in the disconnection phase, a recovery request packet, a disconnection confirmation packet, and a recovery confirmation packet are output. Then, in the data transfer phase, the data stored as data in the information section is output as a data packet. Note that this output data packet is an accumulation of values obtained by sampling 200 million input signals at a constant period.

(Problems to be Solved by the Invention) However, such conventional techniques do not have a function of controlling packetization of input signals and packet output processing in response to changes in input signals. For this reason, even if data that does not have much meaning as information is input, it will be packetized and output. therefore,
There was a problem that the processing efficiency of the device deteriorated.

The present invention overcomes these drawbacks of the prior art.

It is an object of the present invention to provide a packetization device that can control the packetization of 200 million signals and its output processing according to signals produced by one person.

(Means for Solving the Problems) In order to solve the above-mentioned problems, the present invention provides a packetization device that extracts an input signal at a constant period and outputs the extracted value as a packet. Then, an N-bit assembling means outputs this as N-bit parallel data, and the parallel data output from the N-bit assembling means is input, detecting changes in the signal from the sample value string of the parallel data, and responding to the changes. signal monitoring means for outputting a detection signal;
and control means that receives a detection signal from the signal monitoring means and determines whether the input signal changes or remains unchanged based on the content of the detection signal, and the control means determines that there is no change in the input signal based on the detection signal, Pauses input signal packetization and packet output.

(Function) According to the present invention, when the N-bit assembling means receives an input signal, it extracts the input signal at regular intervals, assembles it as N-bit parallel data, and outputs it to the data bus and the signal monitoring means. When the signal monitoring means receives this parallel data, it detects a change in the signal from the sample value sequence of the parallel data and outputs a detection signal corresponding to the change to the data bus. The control means receives this detection signal via the data bus and suspends packetization of the input signal and packet output while determining that there is no change in the input signal.

(Example) Next, an example of a packetization device according to the present invention will be described in detail with reference to the accompanying drawings.

Referring to FIG. 1, a functional block diagram of a packetization device in this embodiment is shown. The packetizer in this embodiment is advantageously applied to, for example, a private branch exchange or large computer that can be directly connected to a packet network, and is used to control the information section of these or the information section (not shown) of a device to which these are connected. This is a device that packetizes an input signal 100 containing data and outputs the packet.

As shown in the figure, this packetizer includes an N-bit assembly circuit 1, a signal monitoring circuit 2i3, and a control circuit 3. The figure is for understanding this example.
Components that are not directly related to this embodiment are omitted from the description, and the control data of the input signal 100 in this embodiment has meaning as information when it changes as data, for example. Specifically, changes in data indicate, for example, a connection phase such as a call request, reception of an incoming call, and connection completion, or a disconnection phase such as a recovery request, disconnection confirmation, and recovery confirmation.

The N-bit assembly circuit 1 receives an input signal 100 which is a two-shot signal.
The 0 assembly circuit l is a bit assembly circuit that inputs the signal 100, extracts the control data included in the signal 100 at regular intervals, and outputs it as N-bit parallel data.
N-1 N l-bit memories 10, timing circuit 1
2 and a gate circuit 14.

Each of the N 1-bit memories 10 has its input side connected to the input signal line 100 and the timing signal $1112 of the timing circuit 12. Each memory lO has an input signal! ! The signal 100 sent via the timing circuit 100 is stored at the timing 112 from the timing circuit 12. Also, at this timing 112, the stored contents are read out.

The timing circuit 12 is a circuit that receives the synchronization signal 102 and thereby generates a timing signal 112 to be supplied to each 1-bit memory 10. This timing signal 11
2, the input signal 1 stored in the l-bit memory IO
00 is assembled as N-bit parallel data and output to the gate circuit 14.

The gate circuit 14 is connected to the control circuit 3, and outputs the N-bit data output from the memory 10 to the N-bit data bus 300 and the signal monitoring circuit 2, respectively, in response to the control signal 104 sent therefrom.

The signal monitoring circuit 2 is a monitoring circuit that detects a change in a signal from a sample value of received N-bit parallel data. As shown in the figure, the signal monitoring circuit 2 has an N-bit memory 20, and when this memory 20 receives N-bit parallel data, it identifies the value of the N-bit parallel data and its change. That is, in the N-bit memory 20, the values of the N-bit data are set in advance as all data "l" and all data "0".
.

The change from rQJ to rl and the change from rlJ to 0 are determined by the outputs of the N-bit memory from 0° to 0, respectively.
It corresponds to either 0□1.

The N-bit memory 20 outputs the output 0゜-〇H-3, which is N-bit parallel data detection information, to the N-bit data bus 30 as N-bit information 220 in response to the control signal 200 sent from the control circuit 3. Output.

The control circuit 3 is connected to an N-bit data bus 300,
Through this, the N-bit parallel data detection information 220 is manually generated. The control circuit 3 is a determination circuit that receives this information N 220 and determines whether the N-bit parallel data output from the gate circuit 14 has changed or not. The control circuit 3 inputs the input signal 1 while the N-bit parallel data remains unchanged.
Packetization processing and packet output are stopped because 00 is data that does not have much meaning as information, and when the data changes, the input signal 100 that is output as N-bit parallel data to the N-bit data bus 300 is packetized. Processes and outputs packets.

Control circuit 3 is also. If there is no change in the N-bit parallel data for a predetermined period of time, a packet containing information indicating the data value is generated and output at regular intervals. Note that if the N-bit parallel data does not change continuously for a predetermined period of time, the data value may be packetized and output.

Explain the operation. In the N-bit assembly circuit l, the synchronization signal 10
A binary input signal 100 is written into the 1-bit memories 0 to 1-bit memories N-1 by the timing signal 112 generated by the timing circuit 12 having the input signal 2. Also, by this timing signal 112, data 0 is transferred from 1-bit memory 0 to 1-bit memory N-1, respectively.
N bits of read data are assembled by reading 0 to 1 and I at the same time. The read N-bit read data is sent to the gate circuit 1 by the control signal 104.
4 to N bits are output to the system data bus 300 and the signal monitoring circuit 2, respectively.

When the signal monitoring circuit 2 receives N-bit read data, all data "l", all data rOJ, and from rOJ to rlJ
, and a change from "l" to "O", and outputs 0° to On-+ corresponding to the N-bit data value to the N-bit system data bus 300 by the control signal 200. Output.

When the data obtained from the N-bit assembly circuit 1 and the signal monitoring circuit 2 change, the control circuit 3 suspends packetization processing and packet output until no change is observed.
When a change occurs, packetization processing and packet output are performed. However, if no change is observed for a predetermined period of time or longer, the control circuit 3 generates and outputs a packet containing information indicating the data value at regular intervals, or packetizes the data value and outputs it.

In addition, an N-bit assembly circuit l that records/disables the input signal 100
In this embodiment, the memory 10 is a 1-bit memory, but if the input signal 100 is sent by multiplexing a plurality of channels in units of frames, it may be stored in each unit. In this case, the timing circuit 12 sends N-bit parallel data to the gate circuit 14 for each channel.

Furthermore, in this embodiment, the input signal 100 containing, for example, control wholesale data of the information section is packetized.
In the present invention, the input signal to be packetized is of course not limited to such signals.

The embodiments described here are for illustrating the present invention, and the present invention is not necessarily limited thereto, and variations and modifications that can be made by those skilled in the art without departing from the spirit of the present invention are possible. It is included within the scope of the present invention.

(Effects of the Invention) As described above, according to the present invention, since the packetization and output processing are controlled based on changes in the input signal, data that does not have much meaning as information is not packetized. Therefore, efficient packet processing can be realized in the packet conversion device.

[Brief explanation of drawings]

FIG. 1 is a functional block diagram showing an embodiment of a packetization device according to the present invention. 1-N-bit assembly circuit Signal monitoring circuit Control circuit 1-bit memory Timing circuit Gate circuit N-bit memory

Claims (1)

[Claims] 1. A packetization device that extracts an input signal at a constant period and outputs the extracted value as a packet, which device: N
N-bit assembling means that outputs parallel data of bits; inputting the parallel data output from the N-bit assembling means; detecting a change in a signal from a sample value sequence of the parallel data; and generating a detection signal corresponding to the change; signal monitoring means for outputting a signal; and control means for receiving a detection signal from the signal monitoring means and determining whether or not the input signal has changed based on the content of the detection signal; A packetization device characterized in that packetization of the input signal and packet output are suspended while it is determined that there is no change in the input signal. 2. In the packetization device according to claim 1, the control means outputs a packet containing information indicating the value of the input signal at regular intervals when the input signal continues to remain unchanged. A packetization device characterized by: 3. The packetizing device according to claim 1, wherein the control means packetizes and outputs the value of the input signal at regular intervals when the input signal continues to remain unchanged. packetizer. 4. The packetization device according to claim 1, wherein the device packetizes data serving as control data of a predetermined information section.