JPH0375876A - Interactive wiring device - Google Patents

Interactive wiring device

Info

Publication number
JPH0375876A
JPH0375876A JP1212225A JP21222589A JPH0375876A JP H0375876 A JPH0375876 A JP H0375876A JP 1212225 A JP1212225 A JP 1212225A JP 21222589 A JP21222589 A JP 21222589A JP H0375876 A JPH0375876 A JP H0375876A
Authority
JP
Japan
Prior art keywords
wiring
wiring length
input
length
display
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP1212225A
Other languages
Japanese (ja)
Other versions
JP2540952B2 (en
Inventor
Osamu Ito
修 伊藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP1212225A priority Critical patent/JP2540952B2/en
Publication of JPH0375876A publication Critical patent/JPH0375876A/en
Application granted granted Critical
Publication of JP2540952B2 publication Critical patent/JP2540952B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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  • Design And Manufacture Of Integrated Circuits (AREA)

Abstract

PURPOSE:To remove the defect of a circuit due to wiring length prior to manufacture by executing the check of the designated wiring length and the input wiring length of an objective pin pair at the time of interactive wiring, and highlight-displaying an error when the input wiring length exceeds the designated wiring length. CONSTITUTION:At the time of the interactive wiring, an input wiring length check part 4 checks the designated wiring length of the objective pin pair and a wiring plan at the point of time of input during connection connecting work at real time. Then, when the input wiring length exceeds the designated wiring length, an error path highlight part 5 displays this whole wiring path by changing its color. Thus, the defect of the wiring length exerting influence on the operation of the circuit is removed, and the normal operation of a product is obtained.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明はCADシスデj\において、特にl−78■や
印刷配線基板に対して対話的に配線を行うための対話配
線装置に関する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an interactive wiring device for interactively wiring a 1-78■ or a printed wiring board in a CAD system.

〔従来の技術〕[Conventional technology]

CADシステl\において特にLSIや印刷配線基板(
PWB)に対して配線を行うための従来の対話配線方式
は、末結線接続処理に重点かおかれれている傾向にあり
、そのための改善は色々とされてきているか、回路動作
に影響を及ぼず配線長については殆んどチェックがなさ
れていない。
In the CAD system, especially LSI and printed wiring boards (
Conventional interactive wiring methods for wiring to PWBs tend to place emphasis on terminal connection processing, and various improvements have been made for this purpose, or there is no need to worry about the impact on circuit operation. The wiring length is hardly checked.

〔発明か解決しようとする課題〕[Invention or problem to be solved]

このため、」二連のような従来の対話配線方式は、かな
りの工数を費やして配線を完成させたとしても、接続し
た配線か回路的に全く問題ないという保証がなく、また
、運悪くとこかのパスで不具合が生しるような配線長に
なっている場合は、結果として製品の正常な動作か得ら
れないという欠点がある。
For this reason, with conventional interactive wiring methods such as "double wiring," even if a considerable amount of man-hours are spent to complete the wiring, there is no guarantee that the connected wiring will have any circuit problems. If the wiring length is such that a problem occurs in any path, there is a drawback that the product cannot operate normally as a result.

〔課題を解決するための手段〕[Means to solve the problem]

本発明の対話配線装置は、対象ビンペアの末結線接続作
業中に入力配線長が指定配線長をオーバーしたときの表
示を切換えるエラー表示モード切換部と、末結線ピンペ
アの表示を行う末結線表示部と、前記対象ビンペアの指
定配線長および結線接続作業中の現在長を表示する配線
長表示部と、入力時点における前記現在長をリアルタイ
ムにチェックする入力配線長チェック部と、前記入力配
線長か前記指定配線長をオーバーしたときのその配線パ
ス全体を色をかえて表示するエラーパスハイライト部と
、前記入力配線長か指定配線長をオーバーしたとき最後
の入力点を拒否する入力点拒否部とを備えている。
The interactive wiring device of the present invention includes an error display mode switching unit that switches the display when the input wiring length exceeds the specified wiring length during the end connection work of the target bin pair, and an end connection display unit that displays the end connection pin pair. a wiring length display section that displays the specified wiring length of the target bin pair and the current length during connection work; an input wiring length check section that checks the current length at the time of input in real time; an error path highlighting section that displays the entire wiring path in a different color when the specified wiring length is exceeded; and an input point rejection section that rejects the last input point when the input wiring length or specified wiring length is exceeded. It is equipped with

〔実施例〕〔Example〕

次に、本発明の実施例について図面を参照して説明する
Next, embodiments of the present invention will be described with reference to the drawings.

第2図は第1図の一実施例の配線長表示部におけるCR
T表示画面の一関を示し、第21J(a>は配線対象の
ビンペア(A〜Z〉とその末結線表示および指定配線長
と現在の配線長との表示列、第21’J(b)および(
()は、それぞれ点A・〜・点Bのパスエラーの色表示
および点りへ・点Eのパスの入力拒否を示す表示列であ
る。第1図は本発明の一実施例を示すフロック図である
Figure 2 shows the CR in the wiring length display section of one embodiment of Figure 1.
The 21st J(a> is the display column of the bin pair (A to Z) to be wired and its terminal connection display, the designated wiring length and the current wiring length, and the 21st J(b) and (
The parentheses are a display column showing path errors at points A, . FIG. 1 is a block diagram showing one embodiment of the present invention.

第1図の実施例は、対虫ピンペアの末結線接続作業中に
指定配線長をオーバーした時にエラー表示を切換えるエ
ラー表示モー1−’切換部]と、末結線ピンペアの表示
を行う末結線表示部2と、列象ピンペアの指定配線長と
結線接続作業中の入力時点における現在長を表示する配
線長表示部3と、入力時点にお番つる配線長をリアルタ
イムにチェックする入力配線長チェック部4と、入力配
線長が指定配線長をオーバーしたときにその配線パス全
体を色を変えて表示するエラーパスハイライト部5と、
入力配線長か指定配線長をオーバーしたときにオーバー
の原因となった最後の入力点を拒否する入力点拒否部6
とを備えており、エラーパスハイライ1一部5と入力点
拒否部6とは、エラー表示モー1〜切換部1の切換えに
よって選11<される。
The embodiment shown in Fig. 1 includes an error display mode 1-' switching section which switches the error display when the specified wiring length is exceeded during the end-connection work of the anti-insect pin pair, and an end-connection display which displays the end-connection pin pair. part 2, a wiring length display part 3 that displays the designated wiring length of the imaginary pin pair and the current length at the time of input during connection work, and an input wiring length check part that checks the actual wiring length at the time of input in real time. 4, an error path highlighting section 5 that displays the entire wiring path in a different color when the input wiring length exceeds the specified wiring length;
Input point rejection unit 6 that rejects the last input point that caused the overage when the input wiring length or designated wiring length is exceeded.
The error path highlight 1 part 5 and the input point rejection section 6 are selected by switching the error display mode 1 to the switching section 1.

第1図の実施例について第2図を参照してさらに詳細に
説明する。
The embodiment shown in FIG. 1 will be described in more detail with reference to FIG. 2.

まずエラー表示モート切換部1によってエラーパスのハ
イライト表示が選択されていると、点A〜点Eが対象ビ
ンペアてあり、点A〜点Eまて配線している状態を第2
図(a)に示すように表示する。この例では、点Eにお
いて人力配線長が指定配線長をオーバーし、配線長表示
部3には指定長と現在の配線長を示す現在長がリアルタ
イl\に表示される(9照符号13)。さらに、入力配
線長が指定配線長をオーバーしているため、第2図(b
)に示すように、点A〜点Eのパス全体か一目でわかる
様な色でハイライ1へ表示する。第2図(c)は、エラ
ー表示モード切換部1で入力点拒否を選択した場合の表
示例で、点A〜点E迄入力していることを示している。
First, when the highlight display of the error path is selected by the error display mode switching unit 1, points A to E are the target bin pair, and the state in which points A to E are wired is displayed as the second
Display as shown in Figure (a). In this example, the manual wiring length exceeds the specified wiring length at point E, and the wiring length display section 3 displays the specified length and the current length indicating the current wiring length in real time l\ (9 reference code 13 ). Furthermore, since the input wiring length exceeds the specified wiring length,
), the entire path from point A to point E is displayed on highlight 1 in a color that can be seen at a glance. FIG. 2(c) is a display example when input point rejection is selected in the error display mode switching unit 1, and shows that input points A to E are being input.

このとき、点Eの入力時点において入力配線長チェック
部4によって入力配線長が指定線長をオーバーしている
ことが検知されると、入力点拒否部6か働いて点0〜点
Eのパスか拒否される。
At this time, if the input wiring length check unit 4 detects that the input wiring length exceeds the specified line length at the time of inputting point E, the input point rejection unit 6 operates to pass the point 0 to point E. or be rejected.

〔発明の効果〕〔Effect of the invention〕

以上説明したように、本発明の対話配線装置は、対話配
線時に対象ピンペアの指定配線J(と入力配線長とのチ
ェックを行い、入力配線長が指定配線長をオーバーした
ときはエラーのハイライ1ル表示等を行うことにより、
配線長による回路の不具合を製造に先立って除去するこ
とがきるという効果かある。
As explained above, the interactive wiring device of the present invention checks the specified wiring J (and input wiring length) of the target pin pair during interactive wiring, and when the input wiring length exceeds the specified wiring length, an error is raised. By displaying the following information,
This has the effect that circuit defects due to wiring length can be eliminated prior to manufacturing.

【図面の簡単な説明】[Brief explanation of drawings]

第工図は本発明の一実施例を示すフロック図、第2図は
第1図の実施例における末結線ピンペアの画面表示の一
例を示す画像図である。 1−・・・エラー表示モード切換部、2・・末結線表示
部、3・・・配線長表示部、4・・入力配線長チェック
部、5・・エラーパスハイライ1〜部、6・・入力点拒
否部。
FIG. 2 is a block diagram showing one embodiment of the present invention, and FIG. 2 is an image diagram showing an example of a screen display of the end-connection pin pair in the embodiment of FIG. 1. 1--Error display mode switching unit, 2-End line display unit, 3-Wire length display unit, 4-Input wiring length check unit, 5-Error path highlight 1-unit, 6-. Input point rejection section.

Claims (1)

【特許請求の範囲】[Claims]  対象ピンペアの末結線接続作業中に入力配線長が指定
配線長をオーバーしたときの表示を切換えるエラー表示
モード切換部と、末結線ピンペアの表示を行う末結線表
示部と、前記対象ピンペアの指定配線長および結線接続
作業中の現在長を表示する配線長表示部と、入力時点に
おける前記現在長をリアルタイムにチェックする入力配
線長チェック部と、前記入力配線長が前記指定配線長を
オーバーしたときのその配線パス全体を色をかえて表示
するエラーパスハイライト部と、前記入力配線長が指定
配線長をオーバーしたとき最後の入力点を拒否する入力
点拒否部とを備えることを特徴とする対話配線装置。
An error display mode switching unit that switches the display when the input wiring length exceeds the specified wiring length during the end connection work of the target pin pair, an end connection display unit that displays the end connection pin pair, and the specified wiring of the target pin pair. a wire length display section that displays the length and the current length during connection work; an input wire length check section that checks the current length at the time of input in real time; An interaction characterized by comprising: an error path highlighting section that displays the entire wiring path in a different color; and an input point rejection section that rejects the last input point when the input wiring length exceeds a specified wiring length. Wiring device.
JP1212225A 1989-08-17 1989-08-17 Interactive wiring device Expired - Fee Related JP2540952B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1212225A JP2540952B2 (en) 1989-08-17 1989-08-17 Interactive wiring device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1212225A JP2540952B2 (en) 1989-08-17 1989-08-17 Interactive wiring device

Publications (2)

Publication Number Publication Date
JPH0375876A true JPH0375876A (en) 1991-03-29
JP2540952B2 JP2540952B2 (en) 1996-10-09

Family

ID=16619026

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1212225A Expired - Fee Related JP2540952B2 (en) 1989-08-17 1989-08-17 Interactive wiring device

Country Status (1)

Country Link
JP (1) JP2540952B2 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102016205049A1 (en) 2016-03-24 2017-09-28 Schunk Bahn- Und Industrietechnik Gmbh Discharge device and method for dissipating electrostatic charges

Also Published As

Publication number Publication date
JP2540952B2 (en) 1996-10-09

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