JPH0374775A - Fault simulation system - Google Patents

Abstract

PURPOSE:To attain an accurate and highly efficient process in a fault simulation system by basically handling the elements of a fault list of each signal line in a lump at every fault occurring area and handling specially the fault list propagated to a feedback joining element or a reconvergence element. CONSTITUTION:The logic elements G5-G10 included in a logic circuit are sorted into the element G6 serving as a feedback joining element, the element G9 serving as a reconvergence element, and elements G5, G7, G8 and G10 serving as the simple elements respectively. The logic elements G5, G7, G8 and G10 are simulated by inverting sequentially the signals applied to the input terminals of these elements respectively. Then the propagation of the fault lists of both elements G6 and G9 are decided at every fault occurring area included in the input signal line of the logic element. Thus, the propagation of the fault list can be accurately and effectively decided for the feedback joining or reconvergence element.

Description

[Detailed Description of the Invention] Industrial Field of Application The present invention relates to a fault simulation method in which a fault state is assumed in a logic circuit and a certain input is given, and a detectable fault is found for the input. BACKGROUND ART A conventional fault simulation method will be explained using FIGS. 6 to 9. FIG. 6 is a circuit diagram used to explain the conventional fault simulation method, and 01 to G4 are logic elements. , a-j are signal lines, logic element G1 is an AND gate, and logic elements 02 to G4 are NAND gates! Simultaneous fault simulation is characterized by simulating only the part of the circuit that behaves differently from the normal circuit at the time of each fault at the same time as the normal circuit. , a simulation is performed by generating all the faults propagated to the input terminal, and the faults propagated to the output are registered as elements of the fault list of that logic element. By reducing the memory capacity by reducing the number of logic elements, and by making a batch propagation judgment on the fault list for each logic element, processing speed has been increased.9 In other words, if we take the circuit in Figure 6 as an example, The logic element G1-04 that constitutes the logic circuit in Figure 6, which is the target of fault simulation, is the logic element G4, which is a reconvergence element, and the other logic elements (hereinafter referred to as simple elements). Then, in the process of performing fault simulation on this logic circuit and propagating the fault list from the input side to the output side of the circuit as shown in Figure 7, the 8th and 9th elements are classified into elements G1-G3. As shown in the figure, the elements of the fault list determined for each signal line are set to the external input signal line of this logic circuit, the output signal line of a reconvergence element, the output signal line of a multi-output element, or the signal line immediately after branching or the board. Until it first reaches any of the external output signal line of this logic circuit, the single input signal line of the reconvergence element, the single input signal line of the multi-output element, or the single signal line immediately before branching. In other words, in FIG. 6, the stuck-at faults occurring on the signal lines of the external input signal lines
A stuck-at fault occurring in signal lines S, c, and e from signal line c to signal line e just before branching is connected to one Duluth external input signal line a.
A stuck-at fault occurring in the signal lines a, f, and h from the signal line f immediately after branching to the input signal line of the reconvergence element is connected to one Duluth external signal line d, and from the signal line g immediately after the branch to the input signal line of the reconvergence element. The stuck-at faults that occurred in the signal lines d, g, and i up to the input signal line i are grouped together.The stuck-at faults that occurred in the signal line j from the output of the brick element G4 to the external output of this logic circuit are grouped into one group. As shown in Figure 9, each group is grouped as shown in Figure 9. Then, in the process of propagation of the failure list, such grouping is performed. Even if it is registered as a subset of the fault list on the signal line, when determining the propagation of the fault list in each element (for logic elements G1-G3, which are simple elements; Perform the simulation by inverting each signal applied to the input terminal one by one.As shown in Figure 8, list the faults connected to the input terminal to which the signal whose output is inverted is applied to that input terminal. Among the faults applied to the logic element G4, which is a set of faults that are propagated to the output,
As shown in the figure, it is not all of the faults that are propagated to the input terminal, but a subset of the fault list. A fault is generated and a simulation is performed.As shown in Figure 8, the fault group propagated to the output is registered in the fault list of the reconvergence element.However, the problem that the invention attempts to solve is the combination of For delay-free logic circuits that consist only of circuits, the above-mentioned conventional fault simulation method can be reliably applied.8 Even in combinational circuits, if there is delay, it cannot be applied, and for sequential circuits, it cannot be applied directly. (It has the disadvantage that it is difficult to perform a fault simulation, but it can also be applied to a combinational circuit by approximating it to a combinational circuit by expanding the operation of a sequential circuit over time.) Although it takes time, the present invention maintains a high fault list propagation speed for combinational circuits without delay.An object of the present invention is to provide a fault simulation method that can also be applied to combinational circuits and sequential circuits with delay. In order to solve the above-mentioned problems, when a certain input is given to a logic circuit composed of a plurality of logic elements, a detection method is applied to the input. In a fault simulation system for determining possible faults, a fault list is propagated from the input side to the output side of the logic circuit. The output signal line or board of the feedback merging element closest to the external input of the logic circuit among the elements included on the output signal line of the multi-output element or the signal line immediately after branching or the signal line forming a ring structure. The signal line until it first reaches any of the external output signal line of the circuit, the input signal line of the reconvergence element, the input signal line of the multi-output element, the signal line immediately before branching, or the input signal line of the feedback merging element. The stuck-at faults that occur in each area up to are grouped as a subset of the fault list, and after the grouping is performed, when the fault list is propagated to the output side elements, the above subsets are grouped together. When a fault list is input to the input signal line of a feedback merging element or reconvergence element, the part of the fault list that has been input into the fault list of the other input signal line of the feedback merging element or reconvergence element When there is a subset that occurs in the same region as the set, and the elements of both are different (above), the propagation judgment is made individually for each element in the subset. The present invention has the above-mentioned configuration, and is a power-pulling system that is based on handling the elements of the fault list of each signal line at once according to the occurrence area.
By specially handling the fault list that has propagated to the feedback merging element or reconvergence element, the scope of application can be extended to circuits with delays and feedback signal lines without slowing down the fault propagation speed in conventional methods. Although the embodiments of the present invention can be expanded, the embodiments of the present invention will be explained below using FIGS. 1 to 5. However, FIG. The figure shows a logic element that is a feedback merging element or a reconvergence element included in a certain logic circuit. Figure 3 shows a fault simulation method according to the present invention for the logic element of Figure 2. The figure shows a fault list obtained from Fig. 3. Fig. 5 shows fault groups that are a subset of the fault list in Fig. 4. G5 to Gll are logic elements, and k - z are signals. Line logic element G5. G6, G
9. Gll is an AND gate, logic element G7. G10 is an inverter gate, and logic element G8 is a NOR gate, but in the fault simulation method that returns to the present invention, it is 41 mA.
The logic elements 05 to GIO included in the logic circuit shown in FIG. 1, which is the object of failure simulation, are fed back to a logic element G6 which is a confluence element, a logic element G9 which is a reconvergence element, and a logic element G5 which is a simple element. G7. G8
．． After classifying it into G10, a fault simulation is executed for this logic circuit, and in the process of propagating the fault list from the input side to the output side of the circuit, the elements of the fault list found for each signal line are An external input signal line of a circuit, an output signal line of a reconvergence element, an output signal line of a multi-output element (not shown), a signal line immediately after branching, or an element included on the path of a signal line forming a ring structure. The output signal line or board of the feedback merging element closest to the external input of the logic circuit, the external output signal line of this logic circuit, the single input signal line of the reconvergence element, or the single input signal line of the multi-output element, or Stuck-at faults that occur in the signal line that first reaches either the single signal line immediately before the branch or the single input signal line of the feedback merging element are grouped as a subset of the fault list.
That is, in FIG. 1, the external input signal line, the signal line from l to the input signal line n of the feedback merging element,
The stuck-at fault that occurred in l and n is connected to one group. The stuck-at fault that occurred in signal line 0 from the output of the feedback merging element to just before the branch is connected to one Duluth external input signal line.
One glue is the stuck-at fault that occurred in the signal lines m, q, and S from the signal line q immediately after the branch to the input signal line S of the reconvergence element. The stuck-at fault that occurred in the signal lines p and r is connected to one Duluth fault. Group the stuck-at faults that occurred in U into one group. Group the stuck-at faults that occurred in signal lines v and w from the signal line V immediately after the branch to the input signal line W of the reconvergence element into one group. Then, in the fault list. In the process of propagation, there is a sign that such grouping is performed. When determining propagation (for logic elements G5.G7.G8.GIO, which are very simple elements)
As before, perform the simulation by inverting each signal applied to the input terminal one by one. Apply the fault list connected to the input terminal to which the signal whose output is inverted is applied to that input terminal. It is possible to achieve sufficient efficiency by pointing to the set of faults propagated to the output as one set of faults propagated to the output as a set of faults propagated to the output. Fault list propagation determination in G9 It will be specifically explained below, but as an example, a fault propagation method in logic element Gll, which is a feedback merging element or reconvergence element included in a certain logic circuit, shown in FIG. will be described using FIGS. 3 to 5. At this time, processing is performed in units of fault occurrence regions included in the input signal line of the logic element. Center of the fault list for each input signal line of the element If there is a subset with the same occurrence area but different elements (force t to perform the simulation by generating all faults belonging to other subsets, the elements of both are equal) (9) If this is a subset of the fault list, and the signal values of the evaluation output signal lines are guaranteed to be the same, generate faults in group units and perform the simulation.
To accurately and efficiently determine the propagation of a fault list in a feedback merging element or reconvergence element by registering a fault group propagated to the coupling output in the fault list of the feedback merging element or reconvergence element. However, in FIGS. 4 and 5, the area consisting of signal lines a and b is Rb, and signal line c +
The region consisting of d and a is Re and LA Rb and Re
Let G b (1) denote each failure group that is a subset of the list of failures that occurred in .

Gb(2), --- and Ge(1), Ge(2),
... (The numbers in parentheses are the order in which fault groups were created in the same area) and the table also shows the fault occurrence area included in the input signal line of logic element Gll in Figure 2! ; LRe, Rh. There are two subsets of the fault list that occurred in the region Re: Ge (1) that exists in the signal line X and Ge (2) that exists in the signal line y. (1),
A simulation is performed by generating all the faults belonging to G e (2) (stuck-at-1 fault on signal line d and stuck-at-1 fault on signal line e). As a result, only the stuck-at-1 fault on signal line e is connected to the output signal line. In the fault list of the blowing signal line 2 propagated to 2 (table), we reconstruct the subset to which the fault that occurred in the region Re belongs, and make it \Ge(3). Also, as a subset of the fault list that occurred in area Rb, both signal lines x and y are G
b(1) exists and both elements are equal. Area Rh
(Stuck-at-0 fault on signal line a and 0 on signal line
Therefore, the fault propagation according to the present invention is performed as shown in FIG. 1. It can also be applied directly to sequential circuits consisting of combinational circuits and memory circuits. The operation of sequential circuits does not evolve over time, and the time required for preprocessing can be significantly shortened, as well as the input of logic circuits. In the process of propagating the fault list from the side to the output side, a set of signal line stuck-at faults that always cause the signal lines at subsequent stages to have the same signal value is grouped as a subset of the fault list. Accurate and efficient processing can be achieved by handling fault propagation of reconvergent elements in groups whenever necessary.

[Brief explanation of drawings]

FIG. 1 is a circuit explaining a fault simulation method in an embodiment of the present invention. FIG. 2 is a circuit showing a logic element that is a feedback merging element or a reconvergence element included in a certain logic circuit. U showing the fault simulation method according to the present invention for the logic element in FIG.
Figure 4 shows a fault list obtained from Figure 3. Figure 5 shows a fault group that is a subset of the fault list in Figure 4. Figure 6 shows a circuit explaining a conventional fault simulation method. Figure 7 shows the process of fault simulation of the circuit example in Figure 6 using the conventional method.
Figure 8 shows the fault list obtained from Figure 7. Figure 9 is a diagram showing failure groups that are a subset of the failure list in Figure 8.

Claims (1)

[Claims] In a fault simulation system that assumes a fault state in a logic circuit composed of a plurality of logic elements and provides a certain input, a detectable fault is found for the input, from the input side to the output side of the logic circuit. When propagating the fault list to the device, the elements of the fault list are used to form an external input signal line of the logic circuit, an output signal line of a reconvergence element, an output signal line of a multi-output element, a signal line immediately after a branch, or a ring structure. From the output signal line of the feedback merging element that is closest to the external input of the logic circuit among the elements included on the path of the signal line of the logic circuit, to the external output signal line of the logic circuit, the input signal line of the reconvergence element, or the multi-output element. Group the stuck-at faults that occur in each region up to the input signal line of the input signal line or the signal line immediately before the branch or the input signal line of the feedback merging element as a subset of the fault list. After performing the above grouping, when propagating the fault list to elements on the output side, the above subset is handled as a whole, and the fault list is input to the input signal line of the feedback merging element or reconvergence element. When, in the fault list of other input signal lines of the feedback merging element or the reconvergence element, there is a subset that occurs in the same area as a subset of the input fault list, and the elements of the two are different. If there is a failure simulation method, the failure simulation method is characterized in that, after individually determining propagation of each element in the subset, the subset is reconfigured and propagated to the output signal line of the element.