JPH0374557B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an abnormality detection device in an automobile integrated wiring system, and in particular detects an abnormality that occurs when controlling objects to be controlled such as lamps and various sensors installed in various parts of an automobile. related to a device for

Recently, with the increase in the number of control objects such as lamps and various sensors installed in automobiles, electrical wiring has become complicated, wiring work has become difficult, wiring errors are likely to occur, and the amount of electric wire used has increased, making it expensive. There is a problem. In order to solve this problem, the following can be considered.

That is, a plurality of control objects installed in an automobile are grouped according to their installation positions, and the control objects included in each group are configured to be controllable by the corresponding terminal control unit. One central control section is provided for a plurality of terminal control sections, and the central control section and each terminal control section are connected by a data transmission line. The central control section controls its own load based on signals from each operating means and data from each terminal control section, and transmits control data to each terminal control section. Each terminal control unit drives and controls the corresponding control target based on the control data given from the central control unit, and also sends signals from the sensors and switches connected to itself to the central control unit as series data. do.

According to the method described above, it is possible to consolidate each data transmission line between the central control unit and each terminal control unit into one data transmission line. Therefore, the wiring work can be simplified, and the amount of electric wires used can be reduced, making it possible to construct the device at low cost.

By the way, when an abnormality occurs in a certain terminal control section, control based on data from the terminal control section or normal drive control of the control object corresponding to the terminal control section becomes impossible. In such a case, depending on the type of object to be controlled, the driving of the vehicle may become extremely dangerous. For example, if the control target is a headlight, it is impossible to drive at night, and if the control target is a turn signal, it is not possible to notify other vehicles of a right or left turn, which can lead to traffic accidents. Therefore, the data exchanged between the central control unit and each terminal control unit is monitored for errors, and
It is important to check whether there is any abnormality in the terminal control unit. However, automobiles have many sources of noise, such as engines, and these noises may mix into communication data, causing temporary errors in the data. Therefore, in the method described above,
Abnormalities in the terminal control unit are frequently detected, making it impossible to expect smooth driving.

Therefore, the main object of the present invention is to provide an abnormality detection device in an automobile integrated wiring system that can distinguish and detect temporary data errors due to noise contamination and data errors due to abnormalities in the terminal control unit. It is.

In summary, the present invention includes: a central control unit monitors data received from a terminal control unit, detects errors therein, counts how many times an error is detected consecutively for each terminal control unit, and If the count result for a terminal control unit exceeds a predetermined number of times, that terminal control unit is separated from the control target of the central control unit.

Hereinafter, specific embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram schematically showing an integrated wiring system for an automobile to which the present invention is applied. In the configuration, for example, a master processor (hereinafter referred to as master
MPU) 10 is provided. A DC voltage is supplied to the master MPU 10 from the storage battery 1. In this embodiment, the master MPU 10 itself also has a function as a terminal, and is connected mainly to an operating means 2A and a controlled object 2B located in the center of the vehicle.
The operating means 2A includes various operating switches provided, for example, in relation to an instrument panel or a steering wheel. Further, illuminated push button switches 3A to 3D are connected to the MPU 10. These switches 3A to 3D correspond to terminal MPUs 20A to 20D, which will be described later, respectively, and their lighting indicates that an abnormality has occurred in the corresponding terminal MPU. The switch that is in the lit state is turned off by being pressed.

Furthermore, terminal processors (hereinafter referred to as terminal MPUs) 20A to 20D, which are examples of terminal control units provided at appropriate locations in the automobile, are connected to the master MPU 10 via cables 30A to 30D. Each terminal
A plurality of control objects and/or detection objects (hereinafter collectively referred to as a group of control objects) 40A to 40D are connected to the MPUs 20A to 20D. Here, the controlled object refers to electrical components such as various lamps and wipers that are installed in an automobile, as will be explained with reference to FIGS. 2A to 2D, which will be described later. Detection targets are various sensors that detect objects that are indicated by various indicators included in the instrument panel of an automobile. These control object groups 40A to 40D are a plurality of control objects grouped according to their arrangement positions, and terminals corresponding to each group.
It is controlled by the MPUs 20A to 20D. Here, although the illustration shows a case where there are four terminal MPUs, this is to represent a case where various control objects are divided and grouped on the front, rear, left and right sides of the automobile. The purpose is to
A includes various control objects provided on the front left side of the automobile, and the terminal MPU 20A is provided at a position close to the front left side of the automobile. Similarly, control object groups 40B, 40C, and 40D are provided in relation to the front right part, the rear left part, and the rear right part of the automobile, respectively, and the terminal MPU2 corresponds to the control object groups 40B, 40C, and 40D.
0B, 20C and 20D are provided.

Figures 2A to 2D show each terminal MPU20A to 2.
FIG. 2 is a diagram schematically showing an example of a controlled object or a detected object connected to an output terminal or an input terminal of 0D. Therefore, each output terminal is connected to a signal line for the various control objects shown in the figure or a switch for activating these control objects. As is clear from the illustration, the output terminal and input terminal of each terminal MPU 20A to 20D each consist of a fixed number of bits (for example, 8 bits), and the operating state of the controlled object is determined by the logic state output from one bit. It is something to control. In addition, Figure 2B and Figure 2
As shown in Figure C, the data input to each of the terminal MPUs 20B and 20C is a value detected by a sensor for detecting the water temperature or a sensor for detecting the amount of gasoline, which is an example of the detection target. .

Further, although not shown in FIGS. 2A to 2D, energization signals for each controlled object are input to each of the terminal MPUs 20A to 20D, respectively.

Further, FIG. 2E shows the manner in which operating means and controlled objects are connected to each terminal of the master MPU 10. If the number of operating means is more than 1 byte (e.g. 8 bits) as shown in the figure,
Receives the output of all operation means as input in multiple bytes.

The types of objects to be controlled and objects to be detected connected to each of these terminal MPUs 20A to 20D and the master MPU 10 are merely examples, and differ depending on the model and type of vehicle.

FIG. 3 is a sectional view showing the specific structure of cables 30A to 30D. Cable 30A~30D
includes a power line 31 in its center. Around the power line 31, a set of system power supply lines 32 and a set of optical fibers 331,
A data transmission line 33 including 332 is arranged. The peripheral portion of each line or optical fiber is coated with an insulator 34.

FIG. 4 is a specific circuit diagram of an embodiment of the integrated wiring system which is a feature of the present invention. In addition, in the illustrated embodiment, the master MPU 10 and one terminal
The relationship with MPU (for example, 20A) is shown.

In the configuration, the master MPU 10 includes a central processing unit (hereinafter referred to as CPU) 11. CPU11 has
A program and data table storage memory (hereinafter referred to as ROM) 13, a data storage memory (hereinafter referred to as RAM) 14, a transmission control circuit 15, an input/output interface 16, and an interface 18 are connected via the bus line 12. Although not shown, the CPU 11 includes registers J, K, and I. Further, a power supply control circuit 18 for controlling on/off of each terminal system power supply circuit is connected to the interface 18 . Connected to the input/output interface 16 are operating means 2A for selecting the operating states of a plurality of controlled objects corresponding to each terminal MPU 20A to 20D, and various indicators for indicating the operating states as the controlled objects 2B. The operation means 2A includes a plurality of operation switches 2a.
~2n is included. The transmission control circuit 15 includes a pair of optical fibers 331 and 332 included in each cable 30A to 30D (only 30A is shown in the figure).
Transmission buffer amplifiers 51a to 51d correspond to
and receiving buffer amplifiers 58a to 58d are connected. Furthermore, master MPU 10 includes a system power supply circuit 17. In this system, the power supply circuit is supplied with power from a storage battery 1.

The terminal MPU (for example, 20A) includes a CPU 21, a ROM 23 and a ROM 24 connected to the CPU 21 via a bus line 22, and a transmission control circuit 2.
5 and an input/output interface 26. Furthermore, the terminal MPU 20A includes a system power supply circuit 27 for supplying power to each section. A reception buffer amplifier 54a and a transmission buffer amplifier 55a are connected to the transmission control circuit 25. The transmitting buffer amplifier 51a and the receiving buffer amplifier 54a are connected via an optical coupler 52a, an optical fiber 331, and an optical coupler 53a. The transmitting buffer 55a and the receiving buffer 58a are connected to an optical coupler 56.
a, an optical fiber 332, and an optical coupler 57a. System power supply circuit 27 is connected to storage battery 1 via system power supply line 32 .

A plurality of controlled objects included in the controlled object group 40A,
For example, headlight (H beam) 410 and wiper 41
In connection with 5, a drive circuit is provided. This drive circuit includes a power switch 430 and a diode 440 connected in series to the headlamp 410, and a power switch 435 connected in series to the wiper 415.
and a diode 445. These power switches 430...435 are connected to the positive terminal of the storage battery 1 via the power line 31. Each power switch 430 is controlled by the output of CPU21.
... 435 is selectively turned on or off, a driver 42 is provided.

In addition, other terminals MPU20B to 20D are
The circuit configuration is the same as that of 20A, and the only difference is the group of controlled objects to be connected, so the detailed configuration will be omitted.

Figure 5 shows ROM1 included in master MPU10.
3 is a diagram schematically showing the storage contents of No. 3. FIG. In addition,
In the illustration, the controlled objects are shown in correspondence with each operating switch number included in the operating means 2A. ROM
13 has a 4-byte storage area for each operation switch, and the upper 3 bits of each byte indicate the terminal number corresponding to the group to be controlled.
The following 3 bits represent the load number to be operated on.
Note that the remaining 2 bits (lower 2 bits) are not used in this embodiment because it is assumed that the number of loads installed on one terminal MPU is 16 or less, but the number of terminal MPUs and the number of loads Used when there are too many.

For example, the input terminal (IN) of master MPU10
Headlamp connected to number 0 of
The load corresponding to the high beam switch is
Load number 0 of MPU20A (RS#0 if terminal number is shown), load number 0 of terminal MPU20B (RS#1), load number 4 of terminal MPU20C (RS#3),
This indicates that the load number of the master MPU 10 (MS#4) is 0. Further, when each 1-byte storage area of the ROM 13 is considered as a table, each table is indicated by M(J, I) in the illustration. However, J means the number of bytes (0 to 3) in the storage area corresponding to one operation switch, and I means the number (0 to 15) of the operation switch.

Note that there are five terminal control units including the master MPU 10, but if there is a switch that has five or more loads, an area of five bytes or more is required for each load.

Figure 6 shows RAM 1 included in master MPU 10.
FIG. 4 is a diagram schematically showing a storage area of No. 4; In the figure, RAM 14 includes storage areas MSW, MOUT, and MRCV. Here, the storage area MSW is
There are 16 operation switches connected to the master MPU10.
If the number is 16 bytes, it includes a 16-byte storage area SW ₀ to SW ₁₅ , and the numbers (#0 to #15) of the operation switches turned on are sequentially written and stored from the upper area. Storage area MOUT is each terminal MPU20
A to 20D (RS#0 to RS#3) and master
It includes areas MOUT ₀ to MOUT ₄ of 1 byte each for the MPU 10 (MS), and stores the number of the load to be driven using multiple (8 in the figure) bits of each 1 byte. Storage area MRCV is each terminal MPU20
It includes areas MRCV ₀ to MRCV ₃ of 1 byte each for A to 20D (RS #0 to #3), and stores received data transmitted from the terminal MPU corresponding to each area.

Furthermore, the RAM 14 has storage areas D, N, MA
and MB included. Here, the storage area D includes areas D ₀ to D ₃ of 1 byte each for each terminal MPU 20A to 20D (RS#0 to RS#3). In these areas _D0 to _D3 , when the corresponding terminal MPU is determined to be abnormal, its terminal number is registered. The storage area N is for each terminal MPU20A to 20D (RS#0
~ #3) Area N ₀ ~ N ₃ of 1 byte each
including. These areas N ₀ to _{N 3} are the corresponding terminals
It is used as a counter to count the number of consecutive errors in the received data from the MPU. The storage area MA is each terminal MPU20A to 20D (RS
1 byte area for each (#0 to #3)
It includes MA ₀ to MA ₃ , and temporarily stores the received data transmitted from the terminal MPU corresponding to each area. Storage area MB is each terminal MPU20A ~
20D (RS #0 to #3) includes areas MB ₀ to _{MB 3} of 1 byte each, and the received data from the terminal MPU corresponding to each area is temporarily stored.

FIG. 7 is a time chart for explaining the operation of an integrated wiring system according to an embodiment of the present invention. Prior to explaining the operation of this embodiment, an outline will be explained with reference to FIG. 7. The master MPU 10 transmits one frame of data for sequentially specifying each terminal MPU 20A to 20D. This one frame data includes destination data SDA, source data SSD, control data, and BCC code. The control data is data for driving and controlling each load (control target) corresponding to the destination terminal MPU, and is, for example, 1-byte data. The BCC code is used for error control, and for example, a vertical/horizontal parity check code is used. Each terminal MPU2
0A to 20D receive one frame of data from the master MPU 10, and if the destination data specifies itself, drive the corresponding load based on the control data.

After the master MPU 10 sequentially transmits one frame of data to a plurality of connected terminal MPUs 20A to 20D (four in the embodiment), the master MPU 10 transmits data to each terminal MPU
A polling signal for sequentially designating 20A to 20D and instructing to transmit operating state detection data is derived. Each of the terminal MPUs 20A to 20D transmits one frame of data including operating state detection data to the master MPU 10 when the polling signal designates itself.

8, 9, and 10 are flowcharts for explaining the operation of an embodiment of the present invention. In particular, FIGS. 8 and 9 show the operation flow on the master side, and FIG. shows the operation flow on the terminal side. Incidentally, FIG. 9 is an operational flow showing details of the subroutine of step (abbreviated as S in the figure) 33 shown in FIG.

Next, the specific operation of this embodiment will be explained with reference to FIGS. 1 to 10.

Initial setting processing operation of RAM 14 First, in step 10, data of "FF" (ie, logic "1" in all 8 bits) is written in hexadecimal notation into areas D ₀ to _{D 3} of RAM 14 . Also, area N ₀ to N ₃ , area MA ₀
~ _MA3 and areas _MB0 ~ _MB3 are written with data ``00'' in hexadecimal notation (that is, logic ``0'' in all 8 bits). Next, in step 11, areas MSW ₀ to
"FF" data is written to MSW ₁₅ in hexadecimal format. Furthermore, data "00" is written in hexadecimal representation in areas MOUT ₀ to MOUT ₄ .

Operation of registering operation switch numbers in the on state In steps 12 to 16, various operation switches (SW0 to SW15) included in the operation means 2A are registered.
An operation is performed in which the numbers of the operating switches that are in the on state are registered in each area of the storage area MSW. That is, in step 12, 0 is set in register K and register J included in the CPU 11. In step 13, it is determined whether the operating switch (initially SWO) corresponding to the value stored in register K is in the on state. If it is determined that the switch is on, proceed to step 14;
Area corresponding to the value of register J (initially 0)
The contents of register K are written to MSW _J. As a result, the number of the switch in the on state is registered. At the same time, the value of register J is incremented by one. In step 15, the value of register K is incremented by one. In step 16, it is determined whether the value of register K has reached the total number of operation switches (for example, 16).
If it is determined that the number is not all, it is determined that the operation of determining whether or not all the operation switches (SW0 to SW15) are in the on state has not been completed, and the process returns to step 13. Note that if it is determined in step 13 that the operation switch specified by the value of register K is not in the on state (off state), the process proceeds to step 14.
The process proceeds to step 15 without performing the above process.
In this way, the operations of steps 13 to 16 are repeated until the operation of determining whether all the operation switches included in the operation means 2A are in the on state is completed.

When it is determined in step 16 that the value of register K has reached the total number of operation switches, the process proceeds to step 17. Step 17
- 26, based on the number of the operation switch in the on state and the terminal number and load number for each operation switch set in the ROM 13,
A load number to be controlled is determined. More specifically, in step 17, register K is set to 0.
is set. At step 18, register J is set to 0. In step 19, the area MSW _K corresponding to the value of register K is
The contents of (ie, the number of the operating switch) are stored in register I. For example, if the operating switch number is 0, the contents of area MSW ₀ are stored in register I. In step 20, the contents of register I are displayed as "FF" in hexadecimal.
It is determined whether or not. In other words, the storage area
It is determined whether the stored contents of the first area MSW ₀ of MSW are the data as initialized. Multiple operation switches (SW0 to SW15)
If any one of these is on, the number of that operation switch is stored in area MSW _K , so the contents of register I will be "FF".
It is determined that this is not the case, and the process proceeds to step 21.

Steps 21 to 24 determine the load number to be turned on.
It is determined whether each byte of data is "FF" or not. That is, in step 21, the ROM
1 byte of data specified in table M(J, I) in Table 13 (however, the value of I corresponds to the number of the operation switch, and the value of J corresponds to the number of bytes of data corresponding to that operation switch). handle)
is read out, and it is determined whether the data is "FF" or not. If the data in the table M(J,I) is not "FF", there is a load to be driven, and the process advances to step 22. In step 22, table M(J,
I) data, for example, M(0,0), the data for turning on load 0 of the terminal MPU20A (RS#0) is read out, and the data is read out from the area MOUT _0.
written to. In step 23, the contents of register J are incremented by one. In this state,
The table to be read next from ROM13 is M(1,
0). In step 24, it is determined whether the value of register J is 4 or not. If it is determined that J is not 4, the process returns to step 21. Then, the operations of steps 21 to 24 are repeated until any of the data in the 4-byte table corresponding to the operation switch (SWO) becomes "FF" or until the value of J becomes 4.

Subsequently, in step 25, register K
1 is added to the value. In step 26, it is determined whether the contents of register K correspond to the total number of operation switches (for example, 16), and if it is determined that the total number is not, the process returns to step 18. If the numbers of the operating switches in the on state are stored in all areas MSW ₀ to MSW ₁₅ , the operations of steps 18 to 26 are repeated a number of times corresponding to the number of operating switches in the on state.

On the other hand, if the number of operation switches in the on state is less than the total number, each _terminal is
After writing data (logic "1") for bit-on operation corresponding to each load included in the MPUs 20A to 20D, it is determined in step 20 that the contents of register I are "FF". Then, proceed to step 27.

Driving the corresponding load In step 27, based on the data of each bit in the area MOUT ₄ , the master MPU 10
The corresponding load is driven.

1 frame data transmission operation Then, in steps 28 to 32, the area
The contents of KMOUT ₀ to MOUT ₃ are transmitted sequentially according to a predetermined transmission format. Specifically, in step 28, register K is set to 0. This is to designate 20A (RS#0) as the terminal MPU to which data should be transmitted first. Next, the process proceeds to step 28a, where it is determined whether the setting value of register K matches the setting contents of area _DK , that is, whether the terminal with terminal number K
It is determined whether the MPU has already been registered as an abnormal terminal. If a match is determined, the process proceeds to step 28b, where the system power circuit of the corresponding terminal is shut down. By this,
The abnormal terminal is disconnected from the master MPU 10.
On the other hand, if no match is determined, the process proceeds to step 29. In step 29, one frame of data to be transmitted to the terminal MPU 20A is edited. For this one frame data, the destination data SDA is #0, and the source data SSA is the master MPU.
#4 represents 10, and the control data is area
are the contents of MOUT ₀ and BCC these data
A code is added. In step 30,
One frame data edited in step 29 is sent to each terminal MPU 20A to 20D via the optical fiber 331 included in each cable 30A to 30D.
sent to.

At this time, each of the terminal MPUs 20A to 20D performs step 51 as shown in FIG.
, it is determined whether the destination data SDA specifies its own terminal number (#K). If destination data SDA is #1,
The CPU 21 included in the terminal MPU 20A determines that it has been designated, and proceeds to step 52. In step 52, the BCC code is judged, and if it is determined that there is no error, the process proceeds to step 53. In step 53,
The received data (ie, the control data stored in area MOUT ₀ ) is stored in the received data storage area 24a of the RAM 24. In step 54, the contents of area 24a are provided to driver 42 via input/output interface 26. Based on the control data, the driver 42 turns on one of the power switches 430 to 435 that corresponds to the load to be driven, thereby driving the load. In step 55, input signals from various sensors connected to the input/output interface 26 as an example of detection targets are read and stored in the transmission data storage area 24b (not shown) included in the RAM 24. Thereafter, in step 56, the CPU 21 determines whether the polling signal designates itself, and waits until its own terminal number (#0) is designated.

On the other hand, on the master MPU 10 side, after transmitting one frame data, 1 is added to the contents of register K in step 31, and the terminal number of the terminal MPU 20B to which next one frame data is to be transmitted is stored in register K. Step 32
At this point, it is determined that the contents of register K are not 4, and the process returns to step 29. Then, the operations of steps 29 to 32 are repeated in the order of the remaining terminal MPUs 20B to 20D, and the other terminals MPUs 20B to 20D perform the operations of steps 51 to 56 shown in FIG. 10 accordingly. As a result, each terminal MPU20B~20
Control data for driving the load corresponding to D is transmitted to each terminal MPU. When one frame data is transmitted to all terminal MPUs 20A to 20D, it is determined in step 32 that the content of register K has become 4, and the process advances to step 33.

Data reception and abnormality control operation The subroutine of step 33 is executed according to the flowchart shown in FIG. That is, in step 101, register K is set to 0. Note that the following explanation will be easily understood if it is considered that the setting value of register K specifies a terminal number. Next, step 1
In step 02, it is determined whether the setting value of register K matches the setting contents of area D _K , that is, whether the terminal MPU with terminal number K has already been registered as an abnormal terminal. At first, the area
_DK is set to hexadecimal ``FF''), so a mismatch is determined. And step 1
Proceed to 03 and enter the terminal number corresponding to the contents of register K (initially #0 specifies terminal MPU20A)
is sent. Accordingly, the terminal MPU20
The CPU 21 of A determines in step 56 (see FIG. 10) that the polling signal designates itself, and proceeds to step 57. In step 57, one frame data (including detection data) stored in the transmission data storage area 24b is transferred to the transmission control circuit 25, the transmission buffer 55a, the optical coupler 56a, the optical fiber 332, the optical coupler 57a, and the reception buffer 58a. It is transmitted to the transmission control circuit 15 via.

Here, 1 transmitted from the terminal MPU20A
In the frame data (see FIG. 7), the destination data SDA is #4, the source data SSD is #0, and the control data is data representing the operating state of the detection target corresponding to the terminal MPU 20A. , with a BCC code added to it.

In response, the CPU 11 performs step 10.
4, one frame data is received from the terminal MPU. Then, proceed to step 105,
It is determined whether or not there is an error in the BCC code included in the received one frame data. BCC
If it is determined that there is no error in the code, the process proceeds to step 106, where only the data portion representing the operating state of the object to be detected out of one frame of received data is written into area MA _K (MA ₀ at first). Then, the process proceeds to step 107, where it is determined whether or not the storage contents of area MA ₀ and area MB ₀ match. Since all 0s are initially set in area MB ₀ for the first time, the contents of both memories are sure to have different values, and the process proceeds to step 110. In this step 110, the area MA ₀
The memory contents of are transferred to area _MB0 . Subsequently, in step 111, 1 is added to the contents of register K. Then, in step 112, it is determined whether the content of register K is 4 or not, in other words, it is determined whether polling signals have been transmitted to all terminals MPU 20A to 20D and received data has been received. Since the content of register K is 1 at the first time, the process returns to step 102 again. The above-described operation is then repeated for each terminal MPU 20B to 20D.

Note that even if the above operations are performed for each terminal MPU 20A to 20D for the first time, none of them pass through step 108, so the area MRCV ₀
~MRCV ₃ is still initially set to hexadecimal ``00''. Therefore, even if the operations in steps 40 and 41 are executed after the operation in step 112, no display or instruction is given on the indicator 2B.

When the routine is executed once again and the operation shown in FIG. 9 is executed again, if it is determined that the contents of area MA _K (the data received this time) match the area MB _K (data received last time), step 108 is executed.
Proceed to. In step 108, the contents of area _MAK are transferred to area _MRCVK . The process then proceeds to step 109, where 0 is set in area MA _K and area N _K. Similar to the previous time, when data reception from each terminal MPU 20A to 20D is completed, the operations of steps 40 and 41 are executed. This time, area MRCV ₀ ~ MRCV ₃
Since the data is stored in , the controlled object 2B is controlled accordingly.

That is, in step 40, the area
Based on the contents of MRCV ₀ , the corresponding indicator lamp included in the controlled object 2B is displayed lit. Also, if the detection targets of terminal MPU20B and 20C are water temperature and gasoline amount,
Each data is area MRCV ₁ , MRCV ₂
Stored in. Therefore, in step 41, the water temperature is instructed to the water temperature meter of the controlled object 2B based on the data stored in the area _MRCV1 . Furthermore, based on the data stored in area MRCV ₂ , the remaining amount of gasoline is indicated to the gasoline amount indicator of control object 2B.

As mentioned above, in this embodiment, each terminal
The controlled object 2B is controlled only when the data received from the MPUs 20A to 20D and the previously received data match. This is caused by the chatter that occurs immediately after the status of the sensors and switches connected to the MPU of each terminal changes.
This is because the data sent from the MPU to the master MPU 10 becomes unreliable. That is, in this embodiment, the time required to execute the routines in FIGS. 8 and 9 for the first time (for example, 20 ms)
is the time required to prevent malfunctions due to chattering.

Next, the operation when it is determined in step 105 that there is an error in the BCC code will be described. Note that such a situation may occur even when the routine is executed for the first time. First, step 11
3, 1 is added to the contents of the corresponding area N _K specified by the set value of register K. The process then proceeds to step 114, where it is determined whether the contents of register N _K are 5 or more. If the contents of register N _K are not 5 or more,
Proceed to step 118 and select the corresponding area MRCV _K.
is set to 0. This ensures that when you subsequently proceed to steps 40 and 41, the corresponding terminal
Displaying or instructing data from the MPU is prohibited. After the operation at step 118, the operations from step 111 described above are repeated.

On the other hand, in step 114, area N _K
If it is determined that the content of
_NK is set to 0), the process proceeds to step 115, and one of the illuminated push button switches 3A to 3D corresponding to the terminal number #K is lit.
Then, the process advances to step 116, and the contents of area K at that time, that is, the terminal number #K is
Transferred to _DK . As a result, the number of the terminal in which the abnormality has occurred is registered. That is, in this embodiment, the BCC received from a certain terminal MPU
If an error occurs in the code five or more times in a row, it is assumed that an abnormality has occurred in the terminal MPU. Subsequently, in step 117, 0 is set in area _NK . Then, the process proceeds to step 118, where 0 is set in area MRCV _K. This prohibits data display or instruction from the corresponding terminal MPU. Thereafter, the operations from step 111 described above are repeated.

Thereafter, if it is determined in step 102 that the corresponding terminal number #K is registered in area _DK as an abnormal terminal, the process proceeds to step 119. In this step 119, switch 3A
It is determined whether or not a corresponding switch among 3D and 3D is turned on. If it is determined that the switch has been turned on, the process proceeds to step 120, where the abnormality warning lamp included in the switch is turned off. Then, the operations from step 111 onwards are repeated again. On the other hand, if it is not determined in step 119 that the corresponding switch is on, the operations from step 111 onwards are directly repeated.

As mentioned above, in this embodiment, a certain terminal
When the terminal number of an MPU is registered as an abnormal terminal, data acquisition from that terminal MPU is prohibited. Due to this, the terminal where the abnormality occurred
It is possible to prevent the control target from being erroneously controlled by the MPU. Further, since the illuminated push button switch corresponding to the terminal registered as having an abnormality is lit, the driver can accurately know the location where the abnormality has occurred, and repair can be facilitated.

In the above-described embodiment, only the data from each terminal MPU is compared as the previous data, but the same can be done for the detection data of the master MPU itself. The operational flow for this will be easily understood by those skilled in the art from the flowchart shown in FIG. 9, so a description thereof will be omitted.

As described above, according to the present invention, when the data transmitted from the terminal control section to the central control section is erroneous for a predetermined number of times or more, it is assumed that an abnormality has occurred in the terminal control device, and the terminal control section In addition to prohibiting data import, a warning is also issued to indicate that an abnormality has occurred in the terminal control unit, making it possible to distinguish between temporary data errors due to noise contamination and data errors due to an abnormality in the terminal control unit. It can be detected separately and accurate error control can be performed. Particularly in automobiles, etc., where there are many noise sources, very effective abnormality control can be performed.

[Brief explanation of drawings]

FIG. 1 is a block diagram schematically showing an embodiment of the present invention. 2A to 2D are diagrams schematically showing an example of a terminal MPU as an example of a terminal control unit and an example of a controlled object connected thereto, and FIG. 2E is an input/output diagram of a master MPU as an example of a central control unit. FIG. 3 is a diagram showing the relationship between a terminal and each controlled object. FIG. 3 is a detailed view of the cable. FIG. 4 is a specific circuit diagram of an embodiment of the present invention. Figure 5 shows ROM13
FIG. 2 is a diagram schematically showing a storage area of . Figure 6 is
3 is a diagram schematically showing a storage area of RAM 14. FIG. FIG. 7 is a time chart for explaining the specific operation of an embodiment of the present invention. 8 to 10 are flowcharts for explaining the operation of an embodiment of the present invention. In particular, FIGS. 8 and 9 show the flowcharts on the master side, and FIG. 10 shows the flowcharts on the terminal side. Showing a flowchart. In the figure, 2A is an operating means, 2B is an indicator,
3A to 3D are illuminated push button switches, 10 is a master MPU (central control unit), 20A to 20D are terminal MPUs (terminal control units), 30A to 30D are cables, 33 is an optical fiber, 40A to 40D are controlled objects/ Indicates the detection target.

Claims (1)

[Scope of Claims] 1. A plurality of various control objects installed in an automobile are grouped into a plurality of groups according to their arrangement positions, and a certain number of control objects included in each group are consolidated and wired for each group. In the system,
A device for intensively detecting operational abnormalities, comprising: a plurality of terminal control units provided for each group; and a device for selecting an operational state of a certain control target from among the plurality of control targets included in each of the terminal control units. an operation means for controlling the operating state of the controlled object to each terminal control unit based on the operation state of the operation means, provided in common in each of the terminal control units; a central control unit that remotely controls the target;
and an alarm means, the central control unit comprising: a data error detection means for detecting that there is an error in the data received from each terminal control unit; and a data error detection means for detecting an error in the data. an error count counting means for counting the number of errors detected for each of the terminal control units; a predetermined number of times detection means for detecting that the count result of the error number counting means has reached a predetermined number of times; and an output of the predetermined number of times detection means. means for driving and controlling the alarm means to issue a warning of an abnormality in the terminal control unit in question; and registering information identifying the terminal control unit in response to the output of the predetermined number of times detection unit. An integrated wiring system for an automobile, comprising: a registration means; and a means for prohibiting transmission of data to a terminal control unit registered in the registration means and prohibiting control based on data received from the terminal control unit. Anomaly detection device.