JPH0374549B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an image processing apparatus having a large capacity image memory, such as a facsimile machine having an editing function, a scanning copying machine, and a word processor capable of handling image data. Today, with the development of semiconductor technology, LSIs for CPUs and other peripheral devices can be obtained at low cost, and are used in a variety of devices.
CPU is now used. Facsimile machines and copiers are no exception, and CPUs and other peripheral devices are frequently used. Also
Facsimile machines and scanning copiers have appeared that can be multifunctional through the use of CPUs, and have functions for enlarging, reducing, rotating, and editing documents and images.

Conventionally, in order to carry out image enlargement processing, as shown in FIG. Memory 2 is required. That is, the image processing circuit 3
acquires original image data 4 from original image memory 1, performs enlargement image processing, and then stores the processed data as image processing data 5 in processed image memory 2.
send to

By the way, image data has a very large amount of information. For example, if an image for one A4 size page is converted into binary data at 12 dots/mm, approximately
The data will be 10M bits. When performing interactive processing, high-speed processing is required, and it is desirable to use a semiconductor memory with a short access time as the image memory, but such a large-capacity semiconductor memory is still expensive.

Therefore, it is desired to reduce the cost of products by reducing the number of expensive, large-capacity semiconductor memories that have been required to date for image processing for enlarging images.

The present invention has been made in view of the above circumstances, and its purpose is to provide image processing that reduces the image memory by half without sacrificing high speed when enlarging an original image stored in the image memory. The goal is to provide equipment.

The present invention will be explained below using examples.

FIG. 2 shows an outline of the present invention. 8
is a line buffer that can store one line of image data, and is provided in the image processing circuit 3. An image processing circuit 3, which is an image processing means, obtains original image data 4 from an image memory 6 via a line buffer 8. The image processing circuit 3, which has performed a predetermined enlargement process on the acquired original image data, returns the image processing data 5 to the original image memory 6 via the line buffer 8. In this way, since the original image data 4 and the image processed data 5 are stored in the same image memory 6, the number of memories for images can be halved. However, unless the image memory 6 used in this embodiment and the conventionally used original image memory 1 and processed image memory 2 have the same capacity, the object of the present invention cannot be achieved. This is because even if you reduce the number of memories, if you increase the memory capacity by that amount, the price will end up being the same. Furthermore, if the absolute amount of information handled by the image processing apparatus (the amount of information of the original image) is reduced because the original image data and processed image data are stored in the same memory, the performance will deteriorate, which is disadvantageous. Therefore, the storage capacity of the image memory 6 is equivalent to that of the conventional original image memory 1 and processed image memory 2, and the original image data and processed image data can be stored within the equivalent storage capacity. There must be. A method for achieving this will be explained in detail later.

FIG. 3 shows a block diagram of the image processing apparatus of the present invention. As described above, the image memory 6 is a semiconductor memory having a capacity equivalent to that of the conventional original image memory 1 and processed image memory 2. 7 is a central processing unit (CPU) which is a control means, 9 is an address path, and 10 is
is a data path, and 11 is a control bus.
The image processing circuit 3 has a function of processing one line of image data in the main scanning direction (arrow m in FIG. 5) of the image memory 6. CPU 7 is image memory 6
The address of the upper processing area is controlled via the address path 9, the image data is controlled to be transferred at high speed between the image memory 6 and the image processing circuit 3 via the data path 10, and the processing of the image processing circuit 3 is controlled. It has bus control authority within the device, such as controlling startup via the control bus 11.

When starting processing, the CPU first sends information on the processing method to the image processing circuit 3 via the control bus 11 and starts the image processing circuit 3.
Next, data for one line in the main scanning direction (arrow m in FIG. 5) of the original image to be processed stored in the image memory 6 is transferred at high speed to the image processing circuit 3 via the data path 10. (generally DMA
transfer). When the image processing circuit 3 completes processing for one line, it enters a processing completion state. The CPU constantly monitors the state of the image processing circuit 3, and upon recognizing the completion state of the processing, transfers one line of processed data to the image memory 6 again.

The above transfer/processing operation will be explained below using FIG. 4. 8 is a line buffer capable of storing one line of toggled image data. 12 is a processing unit that performs image processing such as enlargement and reduction. In the figure, a solid line indicates an ON state, and a broken line indicates an OFF state.

It is assumed that the processing unit 12 is currently processing one line of image data transferred to the line buffer i:a. At this time, the image data to be processed next is transferred to the line buffer ib (i), and at the same time, the image data processed in the previous stage is transferred to the line buffer o:
The processed data stored in b is transferred to the image memory 6 again. When the processing of the image data of the line buffer i:a in the processing section 12 is completed, the switch is switched and the states of the solid line and the broken line in the figure are reversed. When the switch is switched, the image data transferred from the image memory 6 to the line buffer i:b is processed. At the same time, image data to be processed next is transferred to line buffer i:a, and processed data is sent to image memory 6 from line buffer o:a. By repeating the above operations, processing speed can be increased. In other words, if the buffer is not used in a toggle configuration, the total time of data loading time, image processing time, and data transfer time is required, but in this embodiment, while processing the image, Since data is read and data is transferred, the real time corresponds to the image processing time, and is reduced by the sum of the data read time and data transfer time.

Next, the operation of sending the processed data back to the image memory 6 will be explained. In this case, storing processed data in unprocessed lines on the image memory 6 will destroy the original image, so it is necessary to avoid this.

This method will be explained below using the drawings.

In the example shown in FIG. 5, the upper left point of the four edges of the rectangular area of the original image 13 is set as the reference point 15, and the original image 13 is enlarged twice in both the main scanning direction (arrow m) and the sub-scanning direction (arrow s). Processing is shown. The algorithm is based on an interpolation method, and as shown in FIG. 6, the data of one pixel of the original image 13 (for example, 1 in FIG. 6 a) is divided into the main scanning direction (arrow m) and the sub-scanning direction (arrow s). By using each of the two times twice (FIG. 6b), twice as much data is generated.

In the case of enlargement processing, the original image 13 is
In order to prevent the image data from being destroyed, processing is started from line Y ₁ containing image data at the farthest position from reference point 15 and sequentially processed up to line Y _o containing reference point 15. That is, first, the original image 13 is
Sending the Y ₁ line to the image processing circuit 3 produces image data that is twice as long. This is stored in two lines Y ₁ ′ and Y ₂ ′ in the area of the processed image. By doing so, it is possible to obtain a processed image of the line _Y1 that is doubled in both the main scanning direction (arrow m) and the sub-scanning direction (arrow s). Do this sequentially,
The process is repeated for lines Y ₂ , Y _{3 .} . . , and finally the line Y _o of the original image is processed and stored in Y _o ′ _-1 and Y _o ′ of the processed image. In this way, all original image data is processed without being destroyed, and the processed image can be stored in the same image memory as the original image.

As described above, according to the present invention, when enlarging the original image stored in the image memory, the process starts from the image data of the line containing the image data at the farthest position from the reference point in the image memory. , it is possible to realize an image processing device in which the image memory is halved without impairing high speed, which is economical.

[Brief explanation of drawings]

FIG. 1 is a diagram showing the concept of a conventional image processing device.
FIG. 2 is a diagram showing the concept of the image processing device of the present invention;
FIG. 3 is a block diagram of the image processing device of the present invention, FIG. 4 is a diagram showing an embodiment of the line buffer of the image processing circuit of the present invention, and FIG. 5 is an image processing (enlarged FIG. 6 is a diagram illustrating an example of the interpolation method used in FIG. 5. 1: Original image memory, 2: Processed image memory, 3:
Image processing circuit, 4: Original image data, 5: Processed image data, 6: Image memory, 8: Line buffer.

Claims (1)

[Claims] 1. An image processing device having an image memory that stores image data in the main scanning direction and the sub-scanning direction, and an image processing means that processes the image data,
When the image processing means performs an enlargement process for each line of the image data in the main scanning direction, the enlargement process is started from the image data of the line containing the image data at the farthest position from the reference point in the image memory, An image processing apparatus characterized by comprising a control means for sequentially performing enlargement processing up to a line including the reference point and for controlling the enlarged image data to be sequentially stored in the image memory.