JPH0374342B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a load disconnection detection device for a load connected to a circuit.

Conventional configurations and their problems In recent years, system devices have been developed in which electronic devices are equipped with microcomputers to perform complex control. For example, a device self-diagnosis function has become indispensable in recent system devices, and it goes without saying that a circuit load disconnection detection device is also included. A conventional load disconnection detection device will be described below.

FIG. 1 is a block diagram of a system equipped with a conventional load disconnection detection device, where 1 and 2 are amplifiers, 3 is a load disconnection detection device, and 4 is a microcomputer.

Briefly describing the operation of the system shown in Fig. 1, in-phase test signals are output from the outputs of amplifiers 1 and 2, and the determination result is input from the load disconnection detection device 3 to the microcomputer 4. The computer determines whether the load is disconnected.

Fig. 2 is a circuit configuration diagram of a conventional load disconnection detection device, in which 16 and 17 are voltage comparators whose outputs are open collector type, 18 and 19 are loads, 5 is a pull-up resistor, and 6 to 9 are voltage comparators. Feedback resistance, 1
0 and 11 are disconnection detection resistors, 12 and 13 are test signals from the amplifier, 14 is a judgment signal output, and 15 is a pull-up power supply terminal.

The operation of the conventional load disconnection detection device configured as described above will be described below.

In FIG. 2, in-phase test signals are applied from amplifiers 1 and 2 to terminals 12 and 13 when detecting a disconnection in loads 18 and 19. First, loads 18, 19
Consider the case where is normal. When detecting a load disconnection, in-phase test signals are applied from the amplifiers 1 and 2 to the terminals 12 and 13 (the explanation will be given using a rectangular wave, but other waveforms may be used). This signal is applied to voltage comparator 1
If the current flowing to 6 and 17 is ignored, it is divided into disconnection detection resistors 10 and 11 and loads 18 and 19. If disconnection detection resistors 10 and 11 are set to R, loads 18 and 19
When Z is the amplitude of the test signal and E is the amplitude of the test signal, the voltage V across the disconnection detection resistors 10 and 11 is expressed as V=R/R+ZE. This voltage V is the voltage comparator 16,1
A test signal appears at the outputs of voltage comparators 16 and 17 due to the potential difference applied to the inputs of voltage comparators 16 and 17. As described above, the outputs of the voltage comparators 16 and 17 are connected to each other in an open collector format, and the state of the output is determined by the logical product of the voltage comparators 16 and 17. The test signal is in phase and voltage comparator 16,1
7, the outputs of the voltage comparators 16 and 17 exhibit waveforms synchronized with the test signal. A timing diagram showing this state is shown in FIG. In Figure 3, a and b are test signal waveforms (1 in Figure 2).
waveforms of terminals 2 and 13), c is voltage comparator 16,
Waveform of output of 17 (waveform of terminal 14 in Figure 2)
represents. In order to prevent the voltage comparators 16 and 17 from malfunctioning due to noise or the like, the feedback resistors 6 to 9 in FIG. 2 provide positive feedback to stabilize the operation.

Next, consider a case where either of the loads 18 and 19 is disconnected. In FIG. 2, the operation in the case where the load 18 is disconnected will be explained. When the load 18 is disconnected, the test signal applied to the terminal 12 no longer flows toward the load, so the voltage difference across the disconnection detection resistor 10 becomes zero. Therefore, the voltage comparator 16
The voltage difference between the inputs also becomes zero, and the output state of the voltage comparator 16 becomes undefined. On the other hand, the voltage comparator 17 to which the load is connected outputs a signal synchronized with the test signal as described above. However, since the outputs of the two voltage comparators 16 and 17 are connected to each other in an open collector format,
At the same time that voltage comparator 17 becomes H level, voltage comparator 16 also settles to H level. Furthermore, when the output of the voltage comparator 17 changes from the H level to the L level, the voltage comparator 1 whose output has been at the H level until now
6 is also pulled into L level. L level voltage
Assuming E _L , the input voltage of the voltage comparator 16 on the side where the load is disconnected is the test signal voltage (E) on the inverting input side, and the feedback resistor 6, 8 on the non-inverting input side.
are expressed as (E- _EL ) _R1 / _R1 + _{R2 + EL} , respectively _. Here, when the voltage E of the test signal changes from L level to H level, E>
E _L , and the potential on the inverting input side becomes higher, so the output of the voltage comparator 16 always remains stable at the L level. However, the voltage comparator 17 also settles to the L level, and the terminal 14 in FIG. 2 maintains the L level. A timing diagram showing the above state is shown in FIG. In FIG. 4, a indicates the output state of the voltage comparator 16. b indicates the output state of the voltage comparator 17, which remains at the L level after the falling point (point A) of the test signal, and c indicates the waveform of terminal 14 in FIG.

Next, considering the case where both loads 18 and 19 are disconnected, each voltage comparator 1
Since no potential difference occurs between the inputs 6 and 17, the output state becomes undefined and remains at H or L level.

From the above explanation, if the load is disconnected, the output of the voltage comparator will always settle to L or H level, so
By using a microcomputer to judge this change, it is possible to discover a load disconnection.

However, the conventional configuration described above has a problem in that load disconnection cannot be detected when the input offset voltage of the voltage comparator becomes large.

The cause of this problem will be explained below. FIG. 5 shows an equivalent circuit when an offset voltage is included in the voltage comparator, and is obtained by adding an offset voltage 20 to the circuit of FIG. Considering the case of load disconnection in this case, when the terminal 14 is at L level (E _L ), the potential on the non-inverting input side of the voltage comparator 16 is the voltage of the test signal E, the feedback resistor 6, 8 are respectively R ₁ and R ₂ and the offset voltage is _EO , then (E- _EL ) R ₁ /R ₁ +R ₂ + _EL + _EO , and the potential increases by the offset voltage _EO .
When this offset voltage E _O increases, the potential on the non-inverting input side becomes higher than the potential on the inverting input side (voltage E here) and settles to H level. However, the outputs of each voltage comparator are connected to each other in an open collector format, and the voltage comparator 17 to which the load is connected outputs a signal synchronized with the test signal, so the voltage comparator 17 on the load disconnection side 16 is drawn into the collector of the other voltage comparator 17, as shown in the timing diagram of FIG. In Figure 6, a
is voltage comparator 16, b is voltage comparator 17, c is 2
In the waveform at the connection point (terminal 14) of the two voltage comparators 16 and 17, the output should normally settle to H or L level when the load is disconnected, but since the same signal as when the load is normal is output. The problem was that the load was judged to be normal even though it was disconnected.

Purpose of the Invention The present invention solves the above-mentioned conventional problems, and aims to provide a load disconnection detection device that can stably detect load disconnection without being affected by the offset voltage of a voltage comparator. To achieve the above object, the present invention connects a disconnection detection resistor in series with a load whose one end is grounded, and connects the inverting input of a voltage comparator whose output is an open collector type to the connection point. , the other end of the disconnection detection resistor is used as a test signal supply terminal, and that terminal is connected to the non-inverting input of the voltage comparator via the first resistor, and the second resistor is connected from the non-inverting input to the low level of the judgment signal. A load disconnection detection circuit comprising at least two circuits connected to a level reference voltage terminal, an anode of an output diode of a voltage comparator connected, and a cathode connected to the test signal supply terminal, and the output of each circuit is connected. This has the advantage that the state of the input is fixed by the first and second resistors connected to the non-inverting input, and load breakage can be detected without being affected by the input offset voltage of the voltage comparator.

DESCRIPTION OF EMBODIMENTS FIG. 7 shows a circuit configuration of a load disconnection detection device according to an embodiment of the present invention. In FIG. 7, 6 to 8 are resistors for offset voltage cancellation of the voltage comparator, 21 and 22 are test signal pull-in diodes, and 23 is an L level reference power terminal, to which a negative power source lower than the ground potential is supplied. Note that 16 and 17 are voltage comparison supplies, 18 and 19 are loads, 5 is a pull-up resistor, 10 and 11 are disconnection detection resistors, 12 and 13 are test signal terminals, 14 is a judgment signal output, and 15 is a pull-up power supply terminal. , these are the same as the configuration of the conventional example.

The operation of the load disconnection detection device of this embodiment configured as described above will be described below.

First, in the circuit of FIG. 7, the connection point A of the offset voltage canceling resistors 6 to 9 is connected to the non-inverting input side of the respective voltage comparators 16 and 17.
The other ends of the resistors 6 and 7 are connected to an L level reference power supply terminal 23. As mentioned above, this L level reference power supply terminal 23 is supplied with a negative power supply, and if this voltage is E _L , the potential at point A is R ₁ /R ₁ +R ₂ E _L (however, 8 and 9 are _R1 , 6, and ₇ are R2) toward the L-level reference power supply (assuming that the potential of the test signal terminal is zero). Here, the potential at point A is set lower than the inverting input terminal by an offset voltage _EO or more to eliminate the influence of the offset voltage of the voltage comparator. Under these conditions, the circuit operation of this embodiment will be described assuming the same case as the conventional case.

First, consider a case where both loads 18 and 19 are normal. An in-phase test signal is applied to terminals 12 and 13, and disconnection detection resistors 10 and 11 and load 1
8, and 19. When a test signal is applied, the potential difference between the ends of the disconnection detection resistors 10 and 11 is applied to the input terminals of the voltage comparators 16 and 17.
Since the voltage is set higher than the potential difference between the non-inverting input terminal A and the inverting input terminal, which are pulled down to the negative side by , a determination signal synchronized with this test signal is output. Note that diodes 21 and 22 connected between the outputs of the voltage comparators 16 and 17 and the test signal input terminals are used to pull the outputs of the voltage comparators 16 and 17 to L level when the test signal falls.

Next, consider the case where one of the loads is disconnected. Assume that the load 16 shown in FIG. 7 is disconnected. Since the test signal applied to the terminal 12 no longer flows to the load, the potential across the disconnection detection resistor 10 becomes the same as the amplitude of the test signal. In other words, the voltage of the test signal appears on the inverting input side as it is.

On the other hand, the non-inverting input side is pulled down to the L level reference power supply by offset voltage canceling resistors 8 and 6, R ₁ /R ₁ + R ₂ E _L (Resistor 8 is R ₁ , 6 is R ₂ , L level reference power on
Since the _voltage comparator 16
The output of is fixed at L level (assuming that the test signal terminal 12 is zero). voltage comparator 16,
Since the outputs of 17 are connected to each other in an open collector format, if one of them is fixed at L level, the determination signal output becomes L level.

When both loads are disconnected, the operation is the same as when one of the loads is disconnected, and the outputs of the voltage comparators 16 and 17 both become L level, and the determination signal output terminal 14 remains fixed. Therefore, if the state of the output of this judgment signal is judged by a microcomputer, a disconnection of the load can be easily detected.

In addition, in this example, the operation was explained in the case of two loads, but the operating principle remains the same even if multiple of the same circuits are combined, so it is very effective when one of many loads is disconnected. It is a circuit. Furthermore, the output is not limited to the open collector type of a transistor, but the same effect can be obtained with an open drain type of MOS.

Effects of the Invention The present invention connects a disconnection detection resistor in series with a load whose one end is grounded, connects the inverting input of a voltage comparator whose output is an open collector type to the connection point, and connects the other end of the disconnection detection resistor to the connection point of the disconnection detection resistor. As a test signal supply terminal, the terminal is connected to the non-inverting input of the voltage comparator via the first resistor, and the non-inverting input is connected to the second
The resistor is connected to the L-level reference voltage terminal of the judgment signal, the anode of a diode is connected to the output of the voltage comparator, and the cathode is connected to the test signal supply terminal. By connecting the output of the voltage comparator, the potential of the non-inverting input is determined by the first and second resistors, so it is possible to realize load disconnection detection that is not affected by the input offset voltage, and the output is Since they can be connected to each other in an open collector format, it is also possible to determine disconnection of loads in multiple circuits.

[Brief explanation of drawings]

Figure 1 is a system diagram equipped with a load disconnection detection device, Figure 2 is a circuit diagram of a conventional load disconnection detection device,
Figure 3 is a timing waveform diagram of the conventional circuit, Figure 4 is a timing waveform diagram of the conventional circuit when one side is disconnected,
Fig. 5 is a circuit diagram when an offset voltage is applied to the voltage comparator of the conventional circuit, Fig. 6 is a timing waveform diagram of the circuit of Fig. 5, and Fig. 7 is a load disconnection diagram showing an embodiment of the present invention. FIG. 3 is a circuit diagram of a detection device. 6 to 9...Resistance for offset voltage cancellation,
10, 11... Resistor for disconnection detection, 16, 17...
Voltage comparator, 18, 19...Load, 21, 22...
…diode.

Claims (1)

[Claims] 1 Connect a disconnection detection resistor in series with the load whose one end is grounded, connect the inverting input of a voltage comparator whose output is an open collector type to the connection point, and use the other end of the disconnection detection resistor as a test signal supply terminal. A terminal is connected to the non-inverting input of the voltage comparator via a first resistor, a second resistor is connected to the L-level reference voltage terminal of the judgment signal from the non-inverting input, and a diode is connected to the output of the voltage comparator. A load disconnection detection device comprising at least two circuits each having an anode connected to the test signal supply terminal and a cathode connected to the test signal supply terminal, the output of a voltage comparator of each circuit being connected to the output.