JPH0374053U - - Google Patents
Info
- Publication number
- JPH0374053U JPH0374053U JP13321889U JP13321889U JPH0374053U JP H0374053 U JPH0374053 U JP H0374053U JP 13321889 U JP13321889 U JP 13321889U JP 13321889 U JP13321889 U JP 13321889U JP H0374053 U JPH0374053 U JP H0374053U
- Authority
- JP
- Japan
- Prior art keywords
- memory chip
- address
- card
- chip
- redundant
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000007547 defect Effects 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 2
Landscapes
- Techniques For Improving Reliability Of Storages (AREA)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13321889U JPH0374053U (de) | 1989-11-15 | 1989-11-15 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13321889U JPH0374053U (de) | 1989-11-15 | 1989-11-15 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0374053U true JPH0374053U (de) | 1991-07-25 |
Family
ID=31680629
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP13321889U Pending JPH0374053U (de) | 1989-11-15 | 1989-11-15 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0374053U (de) |
-
1989
- 1989-11-15 JP JP13321889U patent/JPH0374053U/ja active Pending
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