JPH0372755A - Multi-protocl switching system - Google Patents

Abstract

PURPOSE:To realize high speed communication with a different communication protocol from each communication path by operating plural communication processing sections independently by plural communication control program. CONSTITUTION:Plural communication lines and plural communication processing sections 32-36 corresponding to each communication line are provided in a communication adaptor 3. Then the communication processing sections 32-36 are operated independently respectively, and a communication control program is replaced into a communication processing section from a host software controlling the communication adaptor 3 and the communication control is implemented through a multi-line by the same or difference communication control program from each communication line. Since the host software and the communication processing section are operated independently, the high speed communication control is attained for each communication line, the communication protocol and the transmission speed are varied simply for each communication line and plural communication protocols are provided in one communication program, then the selection of the communication protocol is simplified.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a communication method, and particularly to a communication system suitable for multi-line communication control.

[Conventional technology]

With faster communication speeds and larger volumes of communication data, the communication control method for information processing devices such as personal computers and workstations is changing so that the system processor controls the line controller and performs all data transmission control and data processing. The system includes a communication adapter, which includes a line controller and a processor dedicated to communication control processing.

The system has changed to one in which a memory or the like is installed to reduce the load on the system processor for communication control processing.

For example, patent application No. 63-1818 filed earlier by the present applicant.
No. 82 ``Communication Adapter Control System and Communication Adapter'' discloses that a communication adapter is provided with a processor dedicated to communication and a shared memory, and data is received and transferred via the shared memory. Additionally, two communication adapters are connected to the system processor to control two different lines, creating a so-called gateway that absorbs differences in protocol conversion and transmission speed between the two lines.

[Problem to be solved by the invention]

However, when controlling multiple lines using the above technology, a communication adapter is required for each line, which not only increases the scale, but also requires a system processor to control each of the adapters, which are distributed over several pieces. There are multiple types of management. Furthermore, it is difficult to exchange information between communication processors in different communication adapters. In particular, when connecting to an 15DN, three channels of, for example, 2B are multiplexed on one line, and the D channel is in charge of call control for the two B channels, so three channels are required. It is difficult to allocate each channel of 2B with one adapter.

Furthermore, the communication line speed of the I5DN is fixed, and it is difficult to communicate with conventional terminals having various transmission speeds via the I5DN.

The purpose of the present invention is to easily connect multiple lines such as 15DN.
It is an object of the present invention to provide a communication control method that performs control at high speed and in response to a partner station.

[Means to solve the problem]

In order to achieve the above purpose, the communication adapter is provided with multiple communication path ports and multiple communication processing units corresponding to the communication paths, and the communication processing units are configured to operate independently, and the upper level software that controls the communication adapter The communication control program can be exchanged from the communication processing unit to the communication processing unit, so that multi-line communication control can be performed using the same or different communication control programs for each communication channel.

Further, a plurality of communication protocols are provided in the communication control program, and one of the communication protocols is designated from the upper level software to perform multi-line communication control.

Further, communication control of multiple lines is performed by automatically selecting one of a plurality of communication protocols based on frames received from a communication path.

Furthermore, a shared memory that can be accessed from both is provided between the communication adapter and the host software, and the communication control program is transferred via the shared memory.

Furthermore, the transmission speed can be changed in the communication processing section, so that the transmission speed can be selected for each communication path from the higher-level software.

[Effect]

Since the host software and communication processing section operate independently, communication can be controlled at high speed for each communication channel, and communication procedures and transmission speeds can be easily changed for each communication channel. Furthermore, since one communication control program has a plurality of communication protocols, communication protocols can be easily switched.

〔Example〕

Hereinafter, one embodiment of the present invention will be described using the drawings.

FIG. 1 is a block diagram showing a configuration example of a multi-line communication control system to which the present invention is adopted. In the figure, 1 is a workstation main body, and this main body 1 is equipped with a communication adapter 3.
The system processor unit 23 controls this. Connected to the communication adapter 3 are an 15DN line 371 for connecting to 15DN that provides a 2B+D basic interface, and a handset 365 for making calls.

The 15DN line 371 can simultaneously use two B channels and one D channel for voice and data communication. In this embodiment, the following two types of channels are considered.

(,) Data communication (D channel) + Data communication (B
channel) + data communication (B channel) (b) data communication (D channel) + data communication (B channel) + voice communication (B channel) In the case of form (a), the handset 365 is not necessarily required.

The communication adapter 3 has three types of functions: a data communication function, a voice communication function, and a call control function.

Data communication uses all channels, including the D channel, B1 channel, and B2 channel, and controls up to the data link layer of layer 2 of the 7-layer model of open system interconnection (○SI). In the D channel, for example, CCI
TT Recommendation 1.441 (LAPD: Link
Access Procedures
Data communication is performed using a packet switching method using eD-channel). In the Bl and B2 channels, for example, HDLC-B A (High Level
Data Link Control Processed
ure (balanced asynchronous balanced mode class) or HDLC-BA, HDLC-UN
(High Level Data Link
Data communication is performed using a circuit switching method based on Control Procedure (unbalanced normal response mode class). Naturally, the D channel, Bl channel, and B2 channel are capable of data communication independently. The transmission rate is 16 Kbps for the D channel. Bl,
Channel speed is 64 Kbps for B2 channel
Although it is fixed, the data transmission speed can be adjusted.

For example, speed matching is performed in accordance with CCITT Recommendations 1.461 and 1.463.

Voice communication is performed by selecting either the B1 channel or the B2 channel. Audio from the handset is 64K
Converts to bps digital audio for communication. Audio can also be recorded and played back using the communication adapter 3. RAMe 312 in FIG. 1 is a memory shared by the system processor unit 23 and the internal processor of the communication adapter 3, and provides an area for inputting and outputting audio. This is called an audio file. If you connect this audio file to the handset,
You can record and play messages locally.

By connecting an audio file to the 15DN, you can record the other party's voice, or play and transmit the contents of the audio file. When recording, use ADPCM (Adaptive
Differential PulseCode
64K audio using
Compress from bps to 32Kbps or 24 Kbps to extend recording time. When playing, expand to 64K.
Return to bps digital audio. Voice can be communicated simultaneously with data communication using different channels.

Call control uses the D channel to connect channels for data communication and voice communication. The control method is, for example, CC
ITT Recommendation 1.441 (LAPD).

1. Follow the procedure in 451.

FIG. 2 shows an example of a network usage pattern to which this embodiment is applied. Work stage? ＼ ・ 9 (WS) 1, 11. Gateway (GW) 13゜1
4 incorporates the communication adapter 3 shown in the embodiment of FIG. 1 and is connected to the I5DNI 5. The host computer 12 complies with, for example, CCITT Recommendation X.

It has 21 conventional public network interfaces. Transmission speed is 9
60 Qbps, which is terminal adapter 10
(For example, Hitachi terminal adapter HN-51
01 series) to the 15DN15. Among these, the host computer 12 and the GWs 13 and 14 do not have handsets. On the other hand, the GWs 13 and 14 constitute a local area network (LAN) with WSI6゜17.18.19, and data is transmitted from the LAN to l5DN15. It has the role of connecting from l5DN15 to LAN. At this time, by packetizing the data and storing and transmitting it, for example, the difference in transmission speed between 10 Mbps LAN and 64 Kbps I5DNI 5 can be absorbed, and the difference in communication procedures between LAN and I5DN15 can be absorbed by protocol conversion. There is.

Each device connected to 15DN15 is Bl.

B2. It has three channels (D) and can communicate with different parties in any combination.

In Figure 2, the following three communication forms are listed.

(a) Interoperability between WSs b) Cluster communication (c) Communication between LANs (a) Interoperability between WSs, between WSI and WSll, B
1 and B2 channels to simultaneously communicate data and voice. Naturally, voice is a real-time communication.

In the cluster communication (b), the host computer 12
This is 1:n communication with multiple WSs via W13. At this time, the GW 13 becomes a terminal control device and controls the WSI 6° 17 that operates as a terminal.

(c) Inter-LAN communication connects GW13 and GW14 to 15D
By connecting through the N network 15, the LAN of the GW 13 and the LAN of the GW 14 are logically made to look like a separate LAN. As a result, for example, WSI 7 can communicate with WSI 9 as if they were on the same LAN.

In GW13, one of the two channels Bl and B2 is used as is at the transmission rate of 64Kbps of l5DN.
Communicate with W14, but the other channel line speed is 64
It is possible to communicate with the computer 12 by adding 9600 bps of data to Kbps.

In Figure 2, the terminal adapter 10. Gateway (G
W) 13.14 does not have a handset, but it is possible to attach one. In a case where the GW 13.14 is installed in a remote location from the host computer 12, it becomes difficult to install and test run additional WSs connected to the LAN, or to investigate the cause of a failure when it occurs. In such a case, if a handset is provided in the terminal adapter 10 and the GW 13.14, maintenance personnel can easily conduct a trial run or investigate the cause of a failure while talking to each other using the handset 1-.

FIG. 3 is a diagram showing an example of a WSI body device,
Here, Hitachi Workstation 2050/
Let's take 32 as an example. The main body 101 has option slots No. 1 to No. 7, and the communication adapter 3 shown in FIG. 1 can be installed in any of the empty slots 106 from No. 1 to No. 5. When mounting, remove the dummy package 111 from that slot and insert it. 1st
The system processor unit 23 in the figure is the CPU package 1
05° Consists of a basic memory package 109 and an optional memory package mounted in the main memory slot 110.

Next, the configuration of the communication adapter 3 shown in the drawing will be explained. The system processor unit 23 includes a CPU 2 that controls the entire main body 1 and the communication adapter 3, and a main memory 21 in which programs and data of the CPU 2 are stored. The system processor section 23 and the communication adapter 3 are connected by a system bus 22. Communication adapter 3 is B1
Alternatively, sub processor units 32 and 33 perform B2 channel data communication, and main processor unit 3 performs B channel voice communication, D channel data communication, D channel call control, etc.
4. LAPD processing unit 35 that performs data link layer level processing for D channel data communication and call control. A line driver 37 that performs multiplexing and demultiplexing of the D channel, B1 channel, and B2 channel. A B channel control section 36 that connects the B1 channel and B2 channel to the sub-processor section 32, 33 and the handset, and performs audio compression/expansion processing. Speed matching section 3
8. System processor section 23. Main processor section 34.
It is composed of a memory sharing section 31 that exchanges data while sharing memory with sub-processor sections 32 and 33.

The system processor section 23 and the memory share section 3 are connected by a system bus 22. Memory share section 31. Main processor section 34. Sub-processor unit 32. The sub-processor units 33 are each connected to a local bus e313 to exchange data. The local bus host 345 of the main processor section 34 has a line driver 37. L.A.P.D.
Processing unit 35. B channel control section 36. A speed matching section 38 is connected, and the main processor section 34 controls them. l
The 2B+D channels of the 5DN line 371 are separated and multiplexed by the line driver 37, of which the D channel is connected to the LAPD processing section 35, and the B1 and B2 channels are connected to the B channel control section 36. The B channel control section 36 controls the Bl and B2 channels to the handset 365 and the main processor section 34 . It is connected to the sub-processor sections 32, 33 and 34 via the speed matching section 38.

Main processor section 34. Sub-processor section 32, 33°LA
The PD processing section 35 and the system processor section 23 each have a CPU, memory, and bus, and can operate independently.

The main processor section 34 includes ROMa342. RAMa34
3. It is composed of a CPU a 341 that executes programs in ROMa 342 and RAMa 343, and a controller micro 344, which are connected to an a-calbus a 345. The ROMa 342 is a read-only memory that stores a program for self-diagnosis of the communication adapter 3 and for loading the program stored in the RAMa 343 from the RAMe 312;
has a capacity of bytes. When the communication adapter 3 is powered on, the CPU a 341 executes the program in the ROM a 342 from the beginning. RAMa 343 is a readable/writable memory that stores programs for processing voice communications and call control procedures, and has a capacity of 128 bytes. Controller Mi 344 uses local bus C313
path control between the local bus 8345 and the CPU a
341 is ROMa342. Performs access control when accessing RAMa 343. ROMa342. RAM
The CPU a341 that executes the a343 is, for example,
It is assumed that a new 8-bit microcomputer manufactured by Hitachi, HD64180S, which operates at 10 MHz is used.

The sub-processor unit 32 is a subordinate processor that operates under the main processor unit 34. The sub-processor unit 32 is R
AMb322. CPUb321. which executes the program in RAMb322. It consists of a controller b324 and a serial controller b323 that transmits and receives data to a line 326 connected to the B1 or B2 channel, which are connected to a local bus C335. RAM
b322 is a readable/writable memory that stores programs for processing HDLC-BA and HDLC-UN, which are B channel data link control procedures;
has a capacity of bytes. The controller b324 performs path control between the local bus C313 and local bus C335, access control when the CPU b321 accesses the RAM b322, and command handshaking for the main processor unit 34 to instruct the sub-processor unit 32 to operate and receive reports. Take control. C that executes RAMb322
The PUb321 and the serial controller b323 are, for example, Hitachi's new 1-chip 8 that operates at 10MIIz.
Bit microcontroller.

Assume that HD64180S is used. The sub-processor section 32 does not have a ROM. Therefore, the main processor section 34
downloads the program to the RAM b322 via the controller b324, and then the CPU b32
1 will be started.

The sub-processor unit 33 is a subordinate processor that operates under the main processor unit 34. The sub-processor unit 33 is R
CPUc331.AMc332, which executes the program of RAMc332. Controller c 334 and line 336 connected to B1 or B2 channel
It consists of a serial controller C333 that transmits and receives data to and from the local bus C335. The RAMc 332 performs HDLC-BA and I-I DLC-U which are B channel data link control procedures.
It is a readable/writable memory that stores a program for processing N, and has a capacity of 32 bytes. The controller c334 controls the path between the local bus C313 and the local bus 0335, and the CPU c331 controls the RA.
Access control when accessing M c 332,
The main processor section 34 performs command handshake control for instructing the sub-processor section 33 to operate and receiving reports. CPU that executes RAM c332
331 and the serial controller C333, for example,
Hitachi's new 1-chip 8-bit microcontroller that operates at 10MHz.

Assume that HD64180S is used. The sub-processor section 33 does not have a ROM. Therefore, the main processor section 34
RAM c 33 via controller 1-roller c 334
2. Download the program, then CP
This will start Uc331.

The LAPD processing unit 35 is a LAPD dedicated processing unit that operates under the main processor unit 34. The LAPD processing unit 35 includes a ROMd 352. CPUd351 executes the program in ROMd352; serial controller C33 sends and receives data to and from the D channel line 372;
355. The ROMd352 is a read-only memory that stores a program for processing LAPD2, which is a D channel data link control procedure. Controller d354 uses local bus C345
and local bus 4355. L.A.P.D.
The processing unit 35 is, for example, μPD72305 manufactured by NEC Corporation.
shall be used.

The B channel control unit 36 controls the ADPCM361°C0DE
C363, a driver 364 for connecting to a handset 365, and a line switching port @362, and is controlled by the main processor unit 34 through a local bus C345. The ADPCM 361 connects Bl and B of the 15DN line 371.
64Kbp from 2 channels or handset 365
You can compress sPCM audio to 32 Kbps or 24 Kbps and record it to RAMe312, or
12 compressed audio to 64Kbps PCM audio,
Bl.

A compression/decompression circuit for sending to the B2 channel or handset 365. CODEC363 is 64
This is a digital-to-analog conversion circuit that converts Kbps P CM audio and analog audio. Line switching circuit 3
62 connects B1 channel 373 and B2 channel 374 to line 3272 line 337 or ADPCM 381 or C
Connect to 0DEC363 or connect to ADPCM361 and C0
This is a line switching circuit for directly connecting DEC363.

ADPCM361 is, for example, μPD77 manufactured by NEC
C30, C0DEC363 is a new HD 4 manufactured by Hitachi.
4.278 shall be used.

The speed matching unit 38 connects the CPU through the local bus C345.
Controlled by a341, line 327, line 326, line 3
Speed matching is performed between the line 37 and the line 336.

The line driver 37 connects C through the local bus C345.
l5 controlled and multiplexed by P U a 341
DN line 371 to D channel 372°B1 channel 3
73. B2 channel 374 is separated, e.g.
It is assumed that μPD982010F manufactured by NEC Corporation is used.

The memory share unit 31 includes RAMe312. It is composed of a controller e311. The RAM e 312 is a readable/writable memory that can be accessed from both the system bus 22 and the local bus C313.
has a capacity of bytes.

The controller e311 performs memory conflict arbitration when the RAM e312 is simultaneously accessed from the system bus 22 and the local bus C313, and the main processor unit 34.
．． Sub-processor unit 32. It performs bus conflict arbitration in response to a request to use the local bus C312 from the sub-processor section 33, and command handshake control for the system processor section 23 to issue operation instructions to the main processor section 34 and receive reports.

FIG. 4 shows the memory storage state of RAMe 312. To start up communication adapter 3, use CPUa that will not be used immediately.
341. This is performed using the transmission/reception buffer areas of the CPU b 321 and cpU c 331.

The system processor section 23 stores the program of the CPU a 341 in the transmission/reception buffer area shown in FIG.
341 to instruct program loading. Loading is done using the ROM a 342 program, and R
After loading the corresponding program into the AMa 343, the storage state shown in FIG. 4 is achieved.

The area used by CPUa341 includes an initial setting block,
There is a transmit buffer and a receive buffer used for D channel data communication, and an audio storage area used for voice communication. CPUb
The areas used in 321 are the initial setting block, B
There are transmit buffers and receive buffers used for channel data communication.

Areas used by the CPUc 331 include an initial setting block, a transmission buffer used for B channel data communication, and a reception buffer. The initial setting block is an area used to first agree on operating conditions between the system processor section 23 and the communication adapter 3. For example, the maximum transmission/reception data length and timeout value set in the system processor section 23, and the transmission conditions set in the adapter. These include the location and size of the bath sofa and reception buffer. Communication control program A
9 communication control program B is CPUb321, CPUc
This program is executed on the RAMe 331 and is kept resident in the RAMe 312. The main processor unit 34 may, as necessary,
By downloading the communication control program to the sub-processor section 32 or 33, the communication control program can be freely exchanged.

The failure logging area is where communication errors and hardware errors that occur within the communication adapter 3 are stored.
CPUa341. Commonly used by CPUb321 and CPUc331.

FIG. 5 shows the memory space of four local buses 325, 335, 313° 345 inside the communication adapter 3 of FIG. 1, and this is seen from the CPU connected to each local bus. It can also be said to represent the memory space location of hardware resources. The thick lines in the figure represent the locations of existing local buses, and what is visible from other local buses is the mapped location as shown in FIG.

The local bus b325 has a 1M byte memory space, and from the lowest part of the memory space, a 32 byte RAM b322 where programs are stored and a controller b32.
4, RAMe 321 is allocated to the topmost part of the memory space. Since the sub-processor section 32 is a subordinate processor that operates under the main processor section 34, the sub-processor section 32 is connected to another sub-processor section 33 or the main processor section 3.
4 hardware resources are not visible.

The local bus C335 has a 1M byte memory space, and from the lowest part of the memory space, a 32-byte RAM c 332 and a controller C334 are stored in the 32-byte part where the program is stored, and a RAM e3 to the highest part of the memory space.
12 is assigned. Since the sub-processor unit 33 is a subordinate processor that operates under the main processor unit 34,
The hardware resources of another sub-processor section 32 and the main processor section 34 cannot be seen from the sub-processor section 33.

The local bus e313 has a 1M byte space, and the controller C311 is assigned to the lowest part of the memory space, and the RAMe 312 is assigned to the highest part of the memory space. In addition, RAMc332. which is a hardware resource of local bus b325 and local bus c335. controller c33
4. RAMb322. In order to make the controller b324 accessible from the local bus 8a345, it is once mapped to the memory space of the local bus e313 as shown in FIG. RAM b322 and controller b324 are
The local bus b325 and local bus o313 have different memory spaces. This address translation is performed by controller b
324 is used. Furthermore, the controller C334 performs address conversion for the RAMc332 and the controller C334.

The local bus mi 345 has a 1M byte memory space, and from the lowest part of the memory space are ROM a 342,
RAM a 343, controller a 344° controller d354. Line driver 37. ADPCM3
61. C0DEC363, controller C311, controller c334. Controller b324. RAMc3
32. RAMb322 and RAMe312 are allocated. Although the memory spaces of the controller C311, RA RAM b322, and controller b324 are different between the local bus e313 and the local bus mi 345, this address conversion is performed by the controller C344.

FIG. 6 is a block diagram showing the configuration of controller C311 in FIG. 1. The controller C311 includes a system bus control unit 3111 that controls the system bus 22, and a local bus e control unit 31 that controls the local bus e313.
13. RAM control unit 3112 that performs memory conflict arbitration when RAM e 3 1 2 is accessed simultaneously from system bus 22 and local bus e 313, activation flag 3
115.

It consists of a startup register 3116, a report flag 3118, a report register 3117, and a local bus e contention arbitration unit 3114. The startup flag 3115 and the startup register 3115 are registers that store flags and operation instruction information indicating whether there is an operation instruction from the system processor section 23 to the main processor section 34, and the report flag 3118 and the report register 3117 are registers that store operation instruction information. 34 to the system processor unit 23, and a register that stores report information. The local bus e contention arbitration unit 3114
The local bus e313 is connected to the main processor section 34. Sub-processor section 32. Bus access contention arbitration for use by the sub-processor unit 33 is performed.

The system bus 22 and local bus e313 are independent asynchronous buses, and it is desired to freely access RAMe312 without being aware of each other. Therefore, the RAM control unit 3112
Then, access rights to RAM e 312 are granted on a first-come, first-served basis, and when one bus is accessing RAM e 312, access from the other bus is made to wait.

Next, using FIG. 6, an explanation will be given of an operation instruction from the system processor unit 23 to the main processor unit 34, taking transmission as an example. The CPU 2 of the system processor unit 23 is RAMe3
After setting transmission data to 12 and setting transmission instruction operation information to the activation register 3116, the activation flag 31 is set to 5. As a result, an interrupt is generated in the CPU a 341 of the main processor unit 34 via the local bus e 313. The CPU a 341 learns from this interrupt that the CPU 2 has started the operation. After that, CPUa3
41 saves the contents of the activation register 3116 into the RAMa 343, resets the activation flag 3115, and then starts data transmission according to the contents of the operation instruction. The startup flag 3115 can be read from the CPU2, and
2 knows that the main processor section 34 can accept the next operation instruction because the startup flag 3115 has been reset.

This is an interface that allows the main processor section 34 to continuously accept operation instructions from the CPU 2 without losing them.

Further, this processing is quickly executed as an interrupt processing asynchronously with data communication.

Next, the reception operation will be explained. CPUa341 is LA
The data received for the PD processing unit 35 is stored in the RAM e 3.
12 to store it. LAPD processing section 3
5 receives the data according to the instructions of the CPU a 341, and when the receiving operation is completed, it notifies the CPU a 341 of the reception by an interrupt. CPUa 341 is LA
After checking the final state of the PD processing unit 35 and confirming that reception was performed normally, the reception report information is set in the report register 3-17 and the report flag 3118 is set. This generates an interrupt to the CPU 2, and the CPU 2 reads the report information in the information register 3117 and resets the report flag 3118. Since the report flag 3118 has been reset, the CPUa 341 knows that the CPU 2 can accept the next report from the main processor section 34.

This is an interface that allows the CPU 2 to continuously accept reports from the CPUa 341 without losing them.

The startup register 3116 is a register that can be read/written by CPU2, and the report register 3117 is a register that can be read/written by CPU2.
This is a register that can be read from/written to from 41. In either case, reading is possible because the CPU on the write side performs a register failure check.

Next, an overview of the operation of the local bus e contention arbitration section 3114 will be explained. Bus use request signal (REQ) and use permission signal (
ACK) is the main processor section 34゜sub processor section 32
．． These are a signal for the sub-processor section 33 to request use of the local bus e313 and a signal for permitting its use. (ADR) is 20 address signals representing LM/<ite space, (DATA) is a data signal consisting of 8 bits,
(AE) is an address enable signal that indicates that (ADR) is enabled, (R/W) is a read/write signal that indicates the read/write direction, and (RDY) is (DA
These signals are ready signals indicating that the main processor section 34.TA) has become valid. Sub-processor section 32. This signal is common to the sub-processor section 33.

FIG. 7 shows an example of a time chart when the main processor section 34 reads and writes to the RAM e312. When the main processor unit 34 turns on the use request signal (REQa) of the local bus e313, the local bus C contention arbitration unit 3114 checks the bus usage status, and if the local bus e313 is in use, waits for the usage to end. , turns on the use permission signal (ACKa) to give the main processor section 34 the right to use the bus. In the main processor section 34, when (ACK'a) is turned on, the (R/W) signal is set in the read direction, and the RAM e to be read is set.
Output the address of 312 to (ADR) and turn on (AE). The local bus e control unit 3113 controls the controller e31 by (ADR) of the local bus e313.
RAMe 312 is constantly monitored to see if it is accessed. Now, (AE), (ADR) and (R/W
), the local bus e control unit 3113 determines that the RAMe 312 has received a read request.
Instructs the Me control unit 3112 to read data from the RAMe 312. When the data is read, the local bus e control unit 3113 outputs it to the (DATA) signal and turns on the (RDY) signal for a predetermined period.

In the main processor section 34, data is extracted from (DATA) at the timing when the (RDY) signal is turned on. The method of termination is the local bus e contention arbitration unit 31.
14 saw (RDY) turn from on to off (AC
As a result, the main processor unit 34 turns off (RE Q a ).

Immediately turn off (R/W), (ADR), and (AE).

(DATA) turns off at the timing when (RDY) turns off. After (RDY) is turned off, the local bus e313 is released after a predetermined time and can accept the next usage request.

The method for writing data from the main processor section 34 to the RAM e 312 also follows a similar procedure. Main processor section 3
4 to local bus e313 use request signal (REQa
), the local bus e contention arbitration unit 3114
Now, check the bus usage status, and if the local bus e313 is in use, wait for it to finish, and then send the usage permission signal (A
CKa) is turned on to give the main processor section 34 the right to use the bus. In the main processor section 34, when (ACKa) turns on (35
ADR), (DATA) and turns on (A E ). The local bus e control unit 3113 controls the controller e311 by (ADR) of the local bus e313.
Alternatively, it constantly monitors whether RAMe 312 is accessed. Now (AE).

When it is determined by (ADH) and (R/W) that there is a write request to RAMe 312, local bus e control unit 3113 sends RAMe to RAMe control unit 3112.
Instructs to write data to 3rd gear 2. local bus e
In the control unit 3113, while data is being written (RDY
) turn on the signal. The method of termination is that the local bus e contention arbitration unit 3114 turns off (ACKa) after seeing (RDY) turn from on to off, and as a result, in the main processor unit 34, (REQa), (R/W) .

Immediately turn off (ADR) and (AE). (DATA
) turns off at the timing when (RDY) turns off. After (RDY) is turned off, the local bus e313 is released at a specified time and can accept the next usage request.

The controller e311 in FIG. 6 has an adapter identification function, a RAMe312 position specification function, and a slot identification function.

The adapter identification function allows multiple adapters of the same type to be installed in one workstation or to be used in combination with different adapters. Assign an identification code to the adapter itself in advance.
This can be read from the system processor section 23.

In FIG. 6, when the controller e311 is mounted on the communication adapter 3, an adapter ID signal 3119 is input from the adapter board to the controller 1-roller e311. C.P.
When U2 makes a request to read the adapter ID through the system bus 22, the system bus control unit 311 sends this adapter ID 3119 signal as is to the CPU2.

In this embodiment, the adapter ID is, for example, "101" in binary.
1” shall be used.

The RAM e position specification function is provided by the R
This allows the AMe 312 to dynamically locate the address visible from the system processor section 23. The system bus control unit 3111 in FIG. 6 has a RAM e pointer. The RAMe pointer is a register representing the head position of RAMe 312 as seen from the system bus 22, and is first set by the system processor unit 23.

After the setting, the system bus control unit 3111 compares the address of the system bus 22 and the RAM e pointer,
When applicable, a read/write request to the RAMe 312 is made to the RAMe control unit 3112.

The slot identification function allows the communication adapter 3 to be inserted into a plurality of slots provided in one workstation regardless of the slot.

In FIG. 6, each slot is provided with a unique slot number 1 to 221 in addition to the signals of the system bus 22.

The system bus control unit 3111 inputs this slot 1 number 221 and changes the addresses of various registers seen from the system processor unit 23 according to the input number.

The registers visible from the system processor unit 23 include the adapter ID, the RAM e pointer, and the activation flag 3115. in FIG. Startup register 3116. Report register 31
17. There is a report flag 3118.

For example, as shown in FIG. 8, the slot number O for the system bus 22 having a memory space of 16 Mbytes is "F30000-F 31 F F" in hexadecimal.
F”, and thereafter allocate 8 bytes for each byte.

FIG. 9 is a block diagram showing the configuration of the controller b324 in FIG. 1. The controller b324 connects the local bus e313'! & local bus control unit 32 to control
41. Local bus b that controls local bus b325
Control unit 3247. Start flag 3243. Startup register 3
244. Report flag 3246. It consists of a report register 3245 and an address translation section 3242. Startup flag 324
The 3° startup register 3244 is a register that stores a flag indicating the presence or absence of an operation instruction from the main processor section 34 to the sub-processor section 32, and operation instruction information, and a report flag 3246. The report register 3245 is the sub-processor unit 3
This is a register that stores a flag indicating a report from 2 to the main processor unit 34 and report information.

The address translation unit 3242 performs address translation to the local bus b325 shown in FIG. 5 when accessing the RAM b322 from the local bus e313. Since only access from the local bus e313 to the local bus 325 is allowed, the arrow is unidirectional.

Next, an operation instruction from the main processor section 34 to the sub-processor section 32 will be explained using FIG. 9, taking transmission as an example. The CPUa 341 of the main processor section 34 sets the transmission data in the RAMe 312 and the transmission instruction operation information in the activation register 3244, and then sets the activation flag 3243. As a result, an interrupt is generated in the CPU b321 of the sub-processor section 32 via the local bus b325.

This interrupt causes CPUb321 to interrupt CPUa341.
I learned that the operation had started. After that, CPUb
321 stores the contents of the startup register 3244 in RAMb322.
After resetting the activation flag 3243, data transmission is started according to the contents of the operation instruction. The activation flag 3243 can be read from the CPU a 341, and the CPU a 341 knows that the sub-processor unit 32 can accept the next operation instruction because the activation flag 3243 has been reset.

This is an interface that allows the sub-processor unit 32 to continuously accept operation instructions from the CPUa 341 without losing them.

Further, this processing is quickly executed as an interrupt processing asynchronously with data communication.

Next, the reception operation will be explained. The CPU b321 sends the received data to the serial controller b323 in RA.
Instruct Me312 to store it. The serial controller 1-roller b 323 receives the data according to the instructions of the \°42° CPU b 321, and when the receiving operation is completed, it notifies the CPU b 321 of the reception by an interrupt. The CPU b 321 checks the termination status of the serial controller b 323 and, when it confirms that reception has been performed normally, sets reception report information in the report register 3245 and sets a report flag 3246. This causes an interrupt to the CPUa341, and the CPU
U a 341 reads the report information in report register 3245 and resets report flag 3246 .

Since the report flag 3246 is reset, the CPUb 321 transmits the next report from the sub-processor section 32 to the CPUa.
I know that 341 is acceptable.

This is an interface that allows the CPUa 341 to continuously accept reports from the CPUb 321 without losing them.

The startup register 3244 is a register that can be read/written from the CPUa 341, and the report register 3245 is a register that can be read/written from the CPUa 341.
This is a register that can be read/written from the PUb321. In either case, reading is possible because the CPU on the write side performs a register failure check.

Signal 3248 is connected to controller b 324 and controller C.
Controller 1 to Controller ID for identifying 334. Controller b324 and controller 334 are the same circuit, and are identified by controller 1 to roller ID 3248. The local bus C control unit 3241 uses the controller 1-roller ID 3248 to determine whether a write/read request has been made from the local bus C 313 to the sub-processor unit 32. The address conversion unit 3242 performs address conversion as shown in FIG. 5 using the controller ID 3248. Note that the controller ID 3248 can also be read by the program of the sub-processor section 32 through the local bus b control section 3247.

FIG. 10 is a block diagram showing the configuration of controller C334 in FIG. 1. The controller C334 is a local bus e control unit 334 that controls the local bus C313.
1. Local bus C control unit 3347° startup flag 3343. which controls local bus C335. Startup register 33
44. Report flag 3346. Report register 3345. It consists of an address conversion section 3342. Start flag 3343 The start register 3344 is a register that stores a flag indicating the presence or absence of an operation instruction from the main processor section 34 to the sub processor section 33, and operation instruction information.
6. The report register 3345 is a register that stores a flag indicating a report from the sub-processor section 33 to the main processor section 34 and report information.

When accessing RAMc332 from local bus C313, address conversion unit 3342 performs address conversion to local bus C335 shown in FIG. 5. Since only access from local bus C313 to local bus C335 is allowed, the arrow is unidirectional.

Next, using FIG. 10, an explanation will be given of an operation instruction from the main processor section 34 to the sub-processor section 33, taking transmission as an example. The CPU a341 of the main processor section 34 is RAMe3
After setting the transmission data in 12 and setting the transmission instruction operation information in the activation register 3344, the activation flag 3343 is set. As a result, an interrupt is generated in the CPU c 331 of the sub-processor section 33 via the local bus C335. In the CPUc331, this interrupt causes the CPU to
It is learned from U a 341 that the operation has been activated.

Thereafter, the CPUc 331 saves the contents of the activation register 3344 into the RAMc 332, resets the activation flag 3343, and then starts data transmission according to the contents of the operation instruction. The startup flag 3343 can be read from the CPUa 341, and the CPUa 341 reads the startup flag 334.
3 has been reset, it is known that the sub-processor section 33 can accept the next operation instruction.

This is an interface that allows the sub-processor unit 33 to continuously accept operation instructions from the CPUa 341 without losing them.

°45.

Further, this processing is quickly executed as an interrupt processing asynchronously with data communication.

Next, the reception operation will be explained. The CPU c331 sends the received data to the serial controller c333 as RA.
Instruct Me312 to store it. The serial controller c333 receives data according to instructions from the CPUc331, and when the receiving operation is completed, the serial controller c333
31 is notified by an interrupt that there has been a reception. C.P.
The U c 331 checks the termination status of the serial controller c 333 , and when it confirms that the reception has been performed normally, sets the reception report information in the report register 3345 and sets the report flag 3346 . This allows CPUa 3
41, the CPU a 341 reads the report information in the report register 3345 and sets the report flag 3.
CPUc331 that resets 346 reports flag 33
46 is reset, the next sub-processor section 33
The CPUa 341 learns that it can accept the report from the CPU a 341 .

This is an interface that allows the CPUa 341 to continuously accept reports from the CPUc 331 without losing them.

Startup register 3344 is read from CPUa341/
Writable register, report register 3345 is CP
This is a register that can be read/written from Uc331. In either case, reading is possible because the CPU on the write side performs a register failure check.

Signal 3348 is connected to controller b 324 and controller c.
This is a controller ID for identifying the controller.334. Controller b324 and controller 1-roller 334 are the same circuit, and are identified by controller ID 3348. The local bus C control unit 3341 uses the controller 1 to roller ID 3348 to determine whether a write/read request has been received from the local bus e313 to the sub-processor unit 33. The address conversion unit 3342 uses the controller ID 3348 to perform address conversion as shown in FIG. Note that the controller 3348 can be read by the program of the sub-processor section 33 through the local bus C control section 33.

FIG. 11 is a block diagram showing the configuration of the controller 1-roller arm 344 of FIG. 1. The controller 344 is a local bus e control section 34 that controls the local bus e313.
41. Local bus C that controls local bus a345
Control unit 3443° Address conversion unit 3442. It consists of an interrupt control section 3444. The address conversion unit 3442
P U a341 is the controller e311. RAMc3
32° controller c 334, RAM b 3
22. When accessing the controller b324, address translation to the local bus e313 shown in FIG. 5 is performed. Since it is a unidirectional access from the CPUa 341, the arrow is unidirectional. The interrupt control unit 3444 receives an interrupt signal INT8 from the activation flag 3115 in the controller e311, an interrupt signal INTb from the activation flag 3243 in the controller b324, and an interrupt signal I from the activation flag 3343 in the controller c334.
NTc.

Transmission/reception from CPU U d 351 (im end 7 interrupt signal, change notification interrupt signal from line driver 37, CPU a 341 included) Existing DMA +C
6 of the ADPCM end interrupt signal from the command ffl+
control two interrupts. ADPC in interrupt signal
The M end interrupt is used for registering and playing audio.
The DMA control unit built into the PUa341 and the ADPCM361 are used in combination. The CPUa 341 sets the 47 recording/playback time to the DMA control unit by pi 1 to number, and the DMA control unit and AD
Start up PCM361. During recording, the DMA control unit transfers compressed audio from ADPCM361 to RAMe31.
2, and at the time of playback, the compressed audio in RAMe 312 is transferred to ADPCM 361. In either case, an ADPCM end interrupt signal is generated to the CPUa 341 when the transfer is completed. In this way, audio input and output can be performed automatically without using a program.

The six interrupt signals are handled by the interrupt control section 3444°49
.

0 and when either signal is turned on, an interrupt is generated to the CPU a 341 via the local bus mi 345. The CPU a 341 that receives the interrupt reads the interrupt cause from the interrupt control unit 3444 through the local bus a control unit 3443, and processes the generated interrupt. When a plurality of interrupts occur simultaneously, they are prioritized by CPU a 34↓, and interrupts with lower priority are masked by the mask register of the interrupt control unit 3444 and made to wait.

FIG. 2 is a block diagram showing the configuration of the line switching circuit 362 in FIG. 1. The line switching circuit 362
621. It consists of a Bl channel selection circuit 3622 and a B2 channel selection circuit 3623. Register 3621 is B1
This register stores channel and B2 channel switching information, and is set by the CPU a 341 via the local bus mirror 345. The register 3621 is an 8-bit register, and the register information is divided into 4 bits each and sent to the B1 channel selection circuit 3622. It is input to the B2 channel selection circuit 3623. The B1 channel selection circuit 3622 selects the B1 channel 373 separated by the line driver 37 from the serial controller C according to the contents of the register 3621.
33 line 326. Connect to one or more of the line 336 of the serial controller C333, C0DEC363, and ADPCM361. B2 channel selection circuit 36
Similarly, in 23, the B2 channel 374 separated by the line driver 37 is connected to the line 3271, line 337, GODEC 363, and ADP according to the contents of the register 3621.
Connect to one or more of CM361. The line connected by the B1 channel selection circuit 3622 and the line connected by the B2 channel selection circuit 3623 are logically summed. The B1 or B2 channel can be connected to handset 365 and also recorded to RAMe 312 at the same time. In this case, register 362 is "11000" in binary.
000" or "00001100". When recording and playing locally with the handset Y1-365 and RAMe312, set the register 3621.
As above, "11000000" or "00" in binary
001100” and set line driver 3.
7 to open the Bl channel 373 or B2 channel 374 and disconnect it from the 15DN line 371.

FIG. 19 is a block diagram showing the configuration of the speed matching section 38 of FIG. 1. The speed matching unit 38 includes a ROM 381 and a matching processing unit 388, and the matching processing unit 388 includes a ROM access control unit 382. Upper interface control unit 383
A transmission speed conversion unit A384 and a reception speed conversion unit A385 that perform speed matching between the two lines 337 and 336. It consists of a transmission speed conversion section B586 and a reception speed conversion section B587 that perform speed matching between the lines 327 and 326. Here, the flow of data from this communication adapter in the 15DN direction will be referred to as transmission, and the flow in the opposite direction will be referred to as reception.

Next, an outline of the speed matching method shown in FIG. I9 will be explained. Rate matching is based on CCl'rT Recommendation 1.463. I.

The conversion procedure is performed in accordance with the speed matching specifications stipulated in 461. Transmission and reception data of the B1 channel and B2 channel are subject to speed matching, and speed conversion is performed independently for each. Conversion speed is 600bps, 1200bps
. . . From the main processor section 34 in FIG.
87 is instructed. Speed conversion is conversion 1. Conversion 2 is performed in two steps. However, conversion 1 is not performed at 32K bps or higher. In conversion 1, ■SDN's 64. Performs conversion between Kbps serial data and intermediate speed data. The transfer speed of the intermediate speed data is finally matched and the sub-processor unit 32.33
The speed matching of the data is determined by the matching speed of the serial data. For example, if the matching speed or conversion speed is 48
In the case of 00 bps, the intermediate speed is 8 Kbps. This is achieved by thinning the 64 Kbps I5DN serial data to 178 bits. In conversion 2, the intermediate speed data converted in conversion 1 and speed matched serial data are converted. The conversion is performed using the conversion format stored in the ROM 381. The conversion format differs depending on the matching speed, and for example, in the case of 4-800 bps, it is as shown in FIG. 20. Intermediate speed data from bit number 1 of octet number O to octet number O bit number 2...octet number O bit number 8......octet number 9 bit number 8
The 80 bits are arranged in the order of , and conversion is performed using these 80 bits as one frame. In the frame structure shown in Figure 20, octet number O (all bit values are O) and octet numbers 1 to 9
The 17 bits with bit number 1 (bit value 1) are frame synchronization bits, and a frame is recognized when the bit pattern as shown in FIG. 20 is obtained. E1 to E in Figure 20
7 bit 1 is a bit for checking the matching speed.

For example, in the case of 4800bps, from E-engineer "011111"
” The D bit in Fig. 20 is speed-matched serial data, which is output in the order of I)xtI)a...D48.In other words, the transmission speed of l5DN is 64
Kbps, but the intermediate speed is 8Kbps, which is 1/8
It is decelerated to s, and this is from one frame of 8o bits.
It is thinned out to 48 bits from D□ to D48 and finally becomes 480 bits.
The speed will be 0 bps. The 8 bits S bit and X bit in FIG. 20 are status bits used to transmit line control information. For example, CCITT Recommendation ■, 24
When communicating with a terminal that has an interface, 81
The bit becomes a data set ready signal which is 24 circuits 107 for transmission, and 24 circuits 107 for reception.
This becomes the data terminal ready signal for circuit 108. This status bit can also be processed by the sub processor units 32 and 33 together with the speed matching serial data, but here, the main processor unit 3 which is controlling the communication adapter 3 in an integrated manner
Processing is performed in step 4. The transmission status bits of the Bl channel and the B2 channel are both sent from the main processor unit 34 to the rate matching unit 38 via the local bus mi 345, and the rate matching unit 38 receives the Bl channel.

Conversely, the B2 channel reception status bits are sent to the main processor unit 34 via the local bus mi 345.

Next, a specific method of speed matching will be explained using FIG. 19.

The two transmission speed conversion sections 384 and 386 have the same configuration, and the two reception speed conversion sections 385 and 387 also have the same configuration. Further, the transmission speed conversion section and the reception speed conversion section use the same conversion method except that the data direction is reversed.

Here, the reception speed converter A385 will be explained as a representative.

The reception speed converter A385 includes a speed register, a status register, a first converter, a second converter, and a ROM address generator. The speed register is a register that stores the conversion speed, and the main processor section 34 is connected to the upper interface control section 3.
83 to set the speed value. The status register is a register that stores status bits extracted from the received frame, and this value is reported to the main processor section 34 via the upper interface control section 383 as necessary. The engraver converter thins out the received signal from the line 337 according to the value of the speed register and creates intermediate speed data.
This is output to the second conversion section. The second converter creates a frame from the intermediate data according to the value of the speed register,
In order to process each bit within the frame according to the contents of the ROM 381, the octet number and bit number are sequentially sent to the ROM address generator. The ROM address generation section determines a ROM address based on the speed information from the speed register, the Offterra 1-number and bit number from the second conversion section, and sends this to the ROM access control section 382.

The ROM access control unit 382 reads this ROM address position information from the ROM 381. Read R
The OM information is passed to the second converter through the ROM address generator. The second converter converts the status bit into the status register according to the ROM information and converts the data pin into the status register.
- is output to line 336.

The upper level interface control section 383 in FIG. 19 controls the reception and delivery of data between the main processor section 34 and each speed conversion section 384 to 387 through the local bus host 345. The data from the main processor section 34 includes speed information and reception status information, and the data is sent from the main processor section 34 as necessary.

The speed information is sent to one of the speed registers of the four speed converters 384 to 387, and the transmission status information is sent to the speed register of the four speed converters A384. Send to one of the B586 status registers. The data sent to the main processor section 34 includes reception status information, and the main processor section 34 sends the reception speed conversion section A385. Read from one of the B587 status registers.

The ROM access control unit 382 has four speed conversion units 384
ROM is read in response to a request from ~387.

The transmission signal and reception signal of the line 337 and the transmission signal and reception signal of the line 327 are all synchronized with a bit timing of 64 Kbps, and the four speed converters also operate with this bit timing. Therefore, from the speed converter
A ROM access request to the OM access unit 382 also occurs at the same time.

On the other hand, the readout position of the ROM is determined by the four speed converters 384.
~387, each different. Therefore, the ROM access control unit reads out the ROM381 in a time-sharing manner, and
Once the M data is complete, it is sent to the speed converter.

The ROM 381 stores the processing contents of each bit in the frame structure shown in FIG. 21st
The figure shows an example of ROM contents.

The ROM has a capacity of 2 bytes, which is divided into four speed converters, and further divided into four parts depending on the conversion speed. This unit area becomes one frame structure data. The reason why two or more conversion speeds are written in one area is because the frames have the same structure except for the intermediate speeds. There is a capacity of 16 octets x 8 bits in the working area. The data is in units of 1 byte, and each byte describes the processing content of the Ebit. For example, for transmission data, ■speed matching data, ■transmission status data.

■Either the fixed data of "rho" or II 17+.

For received data, select and write either ``speed matching data'' or ``reception status data''.

As explained above, since the speed conversion is performed using the ROM, the frame structure can be easily changed by simply converting the ROM. In addition, in the example shown in Figure 21, each speed converter has conversion rule data, but it is also possible to combine the data into one according to the conversion speed, and in this way, the capacity of the ROM can be reduced. It can be held down.

Further, the transmission speed of the received data can be known by determining the E-focus after creating a frame structure as shown in FIG. 20 in the reception speed conversion section. If the speed conversion section is operated at this recognized transmission speed, the main processor section 34
It is also possible to perform speed matching automatically without any instructions from the driver.

FIG. 13 is a diagram showing an example of implementation of the communication adapter 3 of FIG. 1. Communication adapter 3 is 335 nm+X100
It is housed in a board 50 with a size of +nm. Xt in the diagram
all is a 19.6608 MHz crystal oscillator,
The controller e311 shapes the waveform and the CPU a3
41, CP U b 321, CP U, c
Output to three CPUs of 331. Xta12 is 16
It is a crystal oscillator of ゜384M) Iz, and the waveform is shaped by the controller Mi 344, and the frequency is divided by 2 to 8.192-\°61.

MHz clock to ADPCM361 and CPUd35
Output to 1. Note that 1 chip CPUd 351 is LA
Should I remove the circuit of the PD processing section 35? It is housed in a T1 chip. XtA 3 is a 12.288M Ilz crystal oscillator and is directly connected to line driver 37. The horizontal or vertical rectangular component is a module type pull-up resistor for driving the circuit. The relay connects the communication adapter 3 to l5 when the communication adapter 3 is de-energized.
This is for disconnecting the DN line 371. The two pulse lances are used to couple the DC components of the transmitted signal and the received signal with AC. anonymous I
C is a multiplexer circuit for supplying part of the address signals of the system bus 22 and the local bus e313 to the RAM e 312, and a circuit for directly connecting part of the address signals of the local bus e313 and the local bus 345. . This communication adapter 3 includes a line connector 52 for connecting an l5DN line 371 and a handset 365.
There is a handset connector 53 for connecting to the Works 2 and a body connector 51 for connecting to the Chee John 1 body. When the communication adapter 3 is inserted into an empty slot of the workstation 1, the communication adapter 3 is electrically and logically connected to the system processor section 23 through the main body connector.

FIG. 14 is a flowchart 1- showing an example of the operation when the communication adapter 3 is started up. When the power is turned on to the communication adapter 3, the CPU a341 of the main processor section 34 loads the ROM
Execute the program a342 from address O. On the other hand, when the power is turned on, controller b324. Controller 1 to roller c334 are connected to local bus b325. local bus c3
In order to continue issuing resets to CPUb3
21. Both CPUcs 331 are in a stopped state. C.P.
In step A1, the Ua 341 reads all memory registers that can be accessed from the CPU a 341.
A write check is performed, and in step A2, the check result is reported to the CPU 2 through the controller C334.
In step A3, the CPU 2 waits for startup. CPU2
When the instruction to load the program comes from CP,
U a 34.1 is RAM e in step A4.
312 to the RAM a 343, and when the loading is finished, in step A5, a loading completion report is returned to the CPU 2 and the program jumps to the loaded program in the RAM a 343. R
In the AMa343 program, in step A6, CP
The Ua 341 is placed in a state where it can accept interrupts, and in step A7 becomes an interrupt holding state.

FIG. 15(,) is a flowchart of interrupt processing from the CPU 2. All activations of the CPTJa34 from the CPU 2 are received by an interrupt INTE.

When the CPU a 341 receives the "CPUb program loading start" from the CPU 2, in step 47 it loads the specified communication control program A or B into the RAMe 31.
2 to the RAM b322, and after the transfer is completed, in step B2, the controller 1-roller b324 is transferred to the local bus b32.
Instruct to cancel reset 1 to 5. This allows the CPU
b321 executes the program in RAM b332 from address O.

When loading is finished and CPUb 321 is started,
In step B3, the CPU a 341 reports to the CPU 2 that the program loading has been completed, and
After exiting the interrupt processing, the process returns to step 47 and waits for the next interrupt.

When the CPU a 341 receives the "CPUc program loading" activation from the CPU 2, in step B5,
The instructed communication control program A or B is stored in RAM e.
312 to the RAMc 332, and after the transfer is completed, in step B6, the local bus c is transferred to the controller C 334.
Instructs to cancel the reset of 335. As a result, C.P.
Uc 331 executes the program in RAM c 332 from address O.

When the loading is finished and the CPU c 331 is started, the CPU a 341 in step B7
2 that the program loading has been completed, exits from the interrupt processing, and returns to step A7.
Wait for next interrupt.

As described above, the sub-processor section 32 and the sub-processor section 33 can execute either A or B of the communication control program on the RAM e 312. 16th
The figure shows the loading process.

In this embodiment, the communication control program is stored in RAM e.
312 to RAMb322 or RAM a332
Since this method is adopted, two communication control programs A and B can be executed by two sub-processors 32 and 33, respectively.For example, one communication control program A can be executed by two sub-processors 32 and 33, respectively. It is also possible to have both sections 32 and 33 execute the process.

CPUa341 sends “CI) U b” from cpu2
When the sub-processor section 32 is activated, in step B4, the sub-processor section 32
``Send'' is activated, exits from the interrupt processing, returns to step A7, and waits for the next interrupt. The transmission data is stored in the CPUb transmission buffer of RAMe312. The transmission completion report to the CPU 2 is performed during the lNTb interrupt process.

CPUa 341 is CI) U 2 to “CPU c
When the "transmission" activation is received, in step B8, the sub-processor section 33 is activated to "transmit", the interrupt process is exited, and the process returns to the original step A7 to wait for the next interrupt.The transmission data is stored in the RAM e 312. It is stored in the transmission buffer for CPUc.The transmission completion report to CPU2 is sent by lNT.
This is done during c-interrupt processing.

When the CPU a 341 receives a "call setup" activation from the CPU 2, CCITT Recommendation I is executed in step C1.

451, and performs call control processing in accordance with Step B12.
Then, the LAPD processing section 35 is activated for "call setting", the interrupt processing is exited, the process returns to step A7, and the next interrupt is waited for. Detailed information for call setup is available in RAMe31.
2 is stored in the transmission buffer for CPUa. CPU
The completion of call setup is reported to INTd interrupt processing.

When the CPUa 341 receives the activation of "II D channel Paqueso 1-Transmission" from the CPU2, in step B12, the LA
The PD processing unit 35 is activated to send a packet, exits the interrupt processing, returns to step A7, and waits for the next interrupt. The transmission data is sent to the CPU of RAM e 312.
It is stored in the transmission buffer for a. The D channel packet transmission completion report to the CPU 2 is performed during the INTd interrupt processing.

When the CPUa 341 receives "line driver activation" from the CPU 2, in step B12, the line driver 37 receives l5D.
Instruct to activate the N line, and proceed to step B12.
Then, it reports the completion of line driver activation to CI) U2, exits the interrupt processing, returns to step A7, and waits for the next interrupt.

The line driver 37 makes the 15DN line available for use according to the 15DN layer 1 protocol.

When the CPU a 341 receives "C0DEC" activation from the CPU 2, it sets the operation mode to the C0DEC 363 in step B14, reports the completion to the CPU 2 in step B15, exits the interrupt processing, and returns to the original step A.
Return to step 7 and wait for the next interrupt. The operation mode information to the C0DEC363 is sent to the CPU of the RAM e312.
It is stored in the initial setting block for a.

CPU a 34.1 receives “ADPCM” from CPU2
When the activation is received, in step B16, the ADPCM361
Then, the operation mode is set in the DMA control section built in the CPUa 341, and the interrupt processing is exited and the process returns to step A7 to wait for the next interrupt. The operation mode information is
When controller 2 starts up, it is stored in the startup register 3116 in controller 1 to controller e311. The ADPCM completion report to the CPU 2 is performed during interrupt processing from the DMA control unit built into the cpu a 341.

When the CPUa 341 receives the activation of "line switching" from the CPU 2, it sets switching information in the line switching circuit 362 in step B17, reports the completion to the CPU 2 in step B18, exits the interrupt processing, and returns to the original step A7. Return and wait for the next interrupt. Line switching information is RAMe312
It is passed in the startup register 3116 of .

Step 1319. B20. B21 is a process for the speed matching unit 38, in which the CPU a
341 sets conversion speed information in step B19 and overconfidence status information in step B20 in the speed matching unit 38. The information to be set is the startup register 3 of RAMe312.
Passed at 116. In step B21, the speed matching unit 38
Read the reception status information from the report register 31
17 to CPU2. When the processing is finished, the process returns to step A7 and waits for the next interrupt.

FIG. 15(b) is a flowchart 1 for processing an interrupt from the sub-processor unit 32.

When the CPU a 341 receives the "transmission complete" activation from the CPU b 321, it reports the transmission completion to the CPU 2 in step C1, exits the interrupt process, returns to step A7, and waits for the next interrupt.

When the CPU a 341 receives a "reception" report from the CPU b 321, it reports the reception to the CPU 2 in step C2, exits the interrupt processing, and returns to the original step A.
Return to step 7 and wait for the next interrupt.

The received data is stored in the CPUb reception buffer of RAMe312. Detailed reception information such as data position and data length is sent to the report register 324 of the controller b324.
5, it is copied to the report register 3117 of the controller e3↓1 and notified to the CPU2.

FIG. 15(,) is a flowchart of interrupt processing from the sub-processor unit 33.

When the CPUa 341 receives the "transmission complete" activation from the CPUc, it reports the transmission completion to the CPU 2 in step F2, exits the interrupt processing, returns to step A7, and waits for the next interrupt.

When the CPU a 341 receives a "reception" report from the CPU c 331, it reports the reception to the CPU 2 in step F2, exits the interrupt processing, and returns to the original step A.
Return to step 7 and wait for the next interrupt.

The received data is stored in the CPU c reception buffer of RAMe 312. Detailed reception information such as data position and data length is sent to the report register 3 of the controller c334.
345, and this is stored in the controller e31↓
is copied to the report register 3117 and notified to the CPU 2.

FIG. 15(d) is a flowchart of interrupt processing from the LAPD processing section 35.

When the CPU a 341 receives a report from the LAPD processing unit 35 that the master paget transmission is complete, in step F2, the CPU
It reports the completion of D channel packet transmission to U2, exits the interrupt processing, returns to step A7, and waits for the next interrupt.

When the CPUa 341 receives a "reception" report from the LAPD processing unit 35, it reports the reception to the CPU 2 in step F2, exits the interrupt processing, and returns to step A7.
Return to and wait for the next interrupt. Received data is in RAM
e 312 is stored in the reception buffer for CPU a. Detailed reception information such as data position and data length is sent to the CP using the report register 3117 of the controller e311.
Notify U2.

When the CPUa 341 receives the report 2'Call setting complete'' from the LAPD processing unit 35, it reports call setting completion to the CPU2 in step F3, exits the interrupt processing, returns to step A7, and starts the next interrupt. Wait - When the CPUa 341 receives the "incoming call" report from the LAPD processing unit 35, in step F4, CCI 1'T recommendation, 1
．． 451, and performs call control processing in accordance with step F5.
Then, the CPU 2 is notified of the incoming call, exits the interrupt processing, returns to step A7, and waits for the next interrupt. The detailed information of the incoming call is stored in the CPU of RAM e 312.
It is stored in the receive buffer for a.

FIG. 15(e) is a flowchart of interrupt processing from the line driver 37. The line driver 37 is l5DN
Generates an interrupt when the line becomes inactive or goes out of synchronization. When the CPU a 341 receives an interrupt from the line driver 37, in step F1, the RAM
The contents of the line failure are logged in the failure logging area of e312, and in step F2, the fact that there is a failure in the line is reported to CPU2, and the process exits the interrupt processing and returns to step A7.
Return to and wait for the next interrupt.

FIG. 15(f) is a flowchart of interrupt processing from the @DMA control section within the CPUa341.

When the CPUa341 receives an interrupt from the DMA control section built into the CPUa341, in step F2, the CPU2
It reports that the DPCM operation has ended, exits the interrupt processing, returns to step A7, and waits for the next interrupt.

Next, CPUb321. The operation of the CPUc331 will be explained.

It is assumed that the CPU b 321 and the CPU c 331 execute the same program. An example of the structure of the communication control program is shown in FIG. The program is HDLC-BA
There are two protocols, HDLC-UN and HDLC-UN, and one must be selected and used. The selection may be made automatically based on an instruction from the system processor unit 23 and a frame received from the line.

FIG. 18 shows an operation flowchart of the communication control program. Here, CPUb321 is taken as an example, and C
It is assumed that activation from the PUa 341 is performed by flag sensing without using an interrupt. First, step I-
In step I1, the serial controller b323 is initialized to prepare for reception, and in step I-I2, the CPU a34
1 to ``Protocol 7''selection'' is checked. If there is activation, in step H3, the specified HDLC-BA, HD
Select one of LC-UN, and in step H4, select C
A selection completion report is returned to the PUa341, and in step H5,
Branches to either BA or UN. BA at step H5
When the process branches to step H6, it is checked whether or not there is a "send" activation from the CPUa 341. If there is activation, in step H7, HD L and C-B A perform transmission processing, and in step H8, CPU a 341
A transmission end report is made at , and the process returns to step H6. If there is no activation from CP or Ua341 in step H6,
The reception status is checked in step H9, and if data is received from the line, reception processing is performed by the HDLC-BA in step H6O, and in step H1l, the CPUa34
1, and returns to step H6. If there is no reception at step H9, continue to step H
Return to 6.

When branching to UN at step H5 in FIG. 18, transmission and reception processing is performed in the flow from step H12 to step H17, but the flow itself is the same as from step H6 to step H1l, only the control procedure becomes HDLC-UN. Since this will be a bit boring, I will omit it here.

If there is no activation from the CPUa341 in step H2 of FIG. 18, check the reception status in step H18,
When there is data from the line, in step H19, the HD
Select either LC-BA or HDLC-UN,
At step H20, the process branches. The selection method examines the control field in the received frame and selects the asynchronous balanced mode (S
ABM: binary "11111100" or binary "111"
10100"), HD L C-B A, and normal response mode (SNRM: binary "11001001" or binary "11000001"), I-ID.
It becomes LC-UN.

Regarding the operation of CPUd351, refer to NEC's μP D.
Since 72305 is used, the explanation is omitted here.

6 In the above embodiment, the sub-processor unit 32. ．． ROM on 33
Although not used, the ROM can also be added to the size of the ROM while keeping the configuration of the embodiment.

In the engraving embodiment, the secondary processor section 32. The sub-processor units 33 each have RAMb322. RAM c 3
32, and the program is downloaded from the main processor section 34 to this RAM.
RAMb 322. If a ROM in which a transmission control procedure program is written is used instead of the RAMc 332, the procedure for downloading the program can be omitted.

Sub-processor unit 32. The package shown in FIG. 13 can be made even smaller by rewriting the entire sub-processor section 33 into a 1-chip microcomputer, or by adding the speed matching section 38 and making it a 1-chip microcomputer. At this time, as in this embodiment,
The program may be downloaded to the RAM b 322 and RAMc 332, or a ROM in which the above program is pre-written may be used instead of these RAMs.

In the embodiment shown in FIG. 1, the sub-processor units 32 and 33 are
Since it does not have M, it is stopped in a reset state when the power is turned on, and cannot move until the main processor section 34 downloads the program. Therefore,
The ROM a 34-2 in the main processor section 34 is made usable by the sub-processor sections 32 and 33. First, R
Divide the memory space of OM a342 into three parts. Specifically, the ROM in the local bus C memory space in FIG.
A is divided into three parts, two of which are mapped to the local bus C memory space and the lowest part of the local bus C memory space, and RAMb and RAMc are located above them. This is the address conversion section 3242. of controller 1 to roller b324 in FIG. Address conversion section 3342 of controller c334 in Figure 10, controller a344 in Figure 11
The address mapping content of the address translation unit 3442 of the sub-processor unit 32. which is prohibited in this embodiment is changed.
33 to the hardware resources of the main processor section 34. ml controller c334. Modify controller 1-rollami 344. In this way, the sub-processor sections 32 and 33 can run the program in the ROM a 342 at the same time as the power is turned on, and can perform self-diagnosis or run the program by itself.
It can be loaded into M. Further, even if hardware including the ROM fails, failure analysis can be performed using the ROM.

In the embodiment shown in FIG. 1, if the LAPD processing unit 35 is removed, it becomes possible to control multiple lines other than the 15DN, and by adding a sub-processor unit, control of multiple lines becomes possible.

Furthermore, in the embodiment shown in FIG. 1, if the LAPD processing unit 35 and line driver 37 are removed, two lines can be directly connected and controlled, and if a sub-processor unit is added, multiple lines can be controlled using a single board. This is possible with a communication adapter. For example, the second
At GW13 and 14 in the figure, LAN side communication $Il#
If this is processed by the subprocessor shown in Figure 1, the communication data from the LAN can be sent directly to the engineering SDN via the shared memory RAMe312, which reduces the load on the system processor and eliminates data movement. To improve.

In Figure 1, local bus C325 and local bus C335
The controller 1-roller b 324 and controller C 334 can be combined into one bus. in this case,
Since two CPUs operate on the same bus, the performance is somewhat degraded compared to the embodiment shown in Fig. 1, but for example, RAMb3
22, I-I DLC-BA processing program, R
If you load the I-I DLC-UN processing program into the AMC 332 in advance, the HDLC
-BA and HDLC-UN can be operated simultaneously by two CPUs, and if necessary, HDLC-UN of RAMb322 can be operated simultaneously.
One LC-BA program can also be shared and used by two CPUs. In this way, the transmission controller Jf
There is no need to download a program from RAMe 312 every time t is changed, and there is no need to keep a subprocessor program resident in RAMe 312.

〔Effect of the invention〕

As described above, according to the present invention, since a plurality of communication control programs operate independently, high-speed communication can be achieved using different communication procedures for each communication channel. At this time, the data transmission progress can be adjusted according to the other party's month. Furthermore, since one communication control program has a plurality of communication protocols, conversion of protocols becomes fast and easy.

[Brief explanation of drawings]

Fig. 1 is a block configuration diagram of a workstation showing an embodiment of the present invention, Fig. 2 is a network configuration diagram using this embodiment, Fig. 3 is a layout diagram of the workstation housing, and Fig. 4 is a concrete diagram. Diagram showing the storage state of memory, No. 5
The figure shows the memory space of the local bus. Figures 6, 9, 10, 11, 12 and 19 are
Figure 7 is a local bus time chart, Figure 8 is a memory map corresponding to slots, Figure 13 is a communication adapter implementation diagram, Figure 14 is a detailed configuration diagram of the representative block shown in the figure.
FIG. 15 is a flowchart showing an example of the operation of the communication adapter, FIG. 16 is a diagram showing an example of loading the communication control program, FIG. 17 is a configuration diagram of the communication control program, and FIG. 18 is an operation flowchart of the communication control program. FIG. 20 is a structural diagram of a frame used for speed matching, and FIG. 21 is a diagram showing the contents of a ROM for progress matching. l...Workstation, 23...System processor unit, 3...Communication adapter, 34...Main processor unit, 32.33...Sub processor unit, 35...LAPD processing unit, 36...・N channel control unit, 37 ・Line driver, 3
8... Speed matching section. Akira 7 Eye Yuuko 595-

Claims (1)

[Scope of Claims] 1. A communication adapter which is a multi-protocol switching system in a multi-line communication control system and has a plurality of communication processing sections that can operate independently to support a plurality of communication channels, and the communication processing section. and means for inputting a communication control program for controlling a communication path, and the same or different communication control program is replaced for each communication path from higher-level software that controls the communication adapter. 2. Claim 1, wherein the communication control program includes a plurality of communication protocols and a communication protocol switching means, and selects the communication protocol from the host software.
Multi-protocol switching method described. 3. The multi-protocol switching system according to claim 2, wherein the communication protocol switching means automatically selects the communication protocol based on a received frame from the communication path. 4. A multi-protocol switching system in a multi-line communication control system, which includes a communication adapter having a plurality of communication processing units that can operate independently to support multiple communication channels, and a communication processing unit that controls the communication channels. A means for inputting a communication control program to be executed and a transmission speed control means for controlling the transmission speed of the communication path are provided, and the same or different communication control program can be replaced for each communication path from upper software that controls the communication adapter. Features multi-protocol switching method. 5. The multi-protocol switching system according to claim 4, wherein the communication control program has a plurality of communication protocols and a communication protocol switching means, and selects the communication protocol and transmission rate from the higher-level software. 6. The multi-protocol switching system according to claim 5, wherein the communication protocol switching means automatically selects the communication protocol and transmission rate based on a received frame from the communication path. 7. A memory shared between the host software and the communication adapter is added, and the communication control program is passed to the communication adapter using the shared memory. 5, or the multi-protocol switching method described in 6. 8. Claims 1, 2, 3, 4, 5, 6, wherein the communication adapter has means for multiplexing communication channels, and the multiplexed communication channels are controlled by the communication control program.
, or the multi-protocol switching method described in 7. 9. A protocol processor for multi-line communication control, which includes a plurality of communication protocols and is capable of automatically switching the communication protocols based on instructions from a system using these or frames received from a communication path. Characteristic protocol processor. 10. A protocol processor for multi-line communication control, which includes a plurality of communication protocols and a transmission rate converter, and automatically converts the communication protocols based on instructions from the system using these or frames received from the communication path. and a transmission rate conversion section. 11. A transmission rate control method for variably controlling the transmission rate of a communication channel, comprising a transmission rate control unit and means for storing rate matching data for each transmission rate, the transmission rate control unit Reading speed matching data corresponding to the transmission speed of the communication data of the communication channel and the transmission speed to be converted from the storage means, and deleting and inserting the communication data from the input side communication channel according to the information of the read speed matching data. A transmission speed control method characterized by controlling the transmission speed of an outgoing communication path. 12. A transmission rate control method for variably controlling the transmission rate of a communication channel, comprising a transmission rate control unit and means for storing reception rate matching data and sending rate matching data for each transmission rate, The speed control unit reads out reception speed matching data corresponding to the transmission speed of communication data on the input communication path from the storage means, and adjusts the communication data from the input communication path according to the information of the read reception speed adjustment data. The transmission speed control section creates intermediate speed communication data by deleting and inserting the . A transmission rate control method characterized in that the transmission rate of an outgoing communication channel is controlled by deleting and inserting intermediate rate communication data according to information of transmission rate matching data. 13. The transmission speed control unit detects the transmission speed of communication data on the input side communication path from the received frame from the input side communication path, and corresponds to the detected transmission speed of communication data on the input side communication path. 13. The transmission rate control method according to claim 12, further comprising reading out reception rate matching data from said storage means.