JPH0371715B2 - - Google Patents

Description

[Detailed Description of the Invention] [Summary] The present invention relates to a curved tube (CRT).
CRT controller (CRTC) that exclusively controls
In a two-split screen display system using a CRTC that can control not only the CRT but also the liquid crystal panel (LCD) using the The present invention relates to a cursor display method in which a cursor is displayed twice per scan.

In a CRT device using the raster scan method, the raster is scanned from the upper left to the lower right of the screen, approximately 200 lines at a time, and the VRAM address corresponding to the pixel position of each scanned screen is determined per screen scan. It is designed to be accessed only once. On the other hand, due to the characteristics of LCD panels, if raster scan is not performed once every 100 lines, the characters will become very thin. The system is divided into 100 upper and lower lines and displays two lines at once.

The present invention applies an offset to the VRAM address output by the CRTC so that two corresponding pixels in the upper and lower half areas of the screen are simultaneously displayed for each scan of the screen by the CRTC. VRAM corresponding to pixel location
Generates an address and prints a character pattern twice in each of the upper and lower halves of the screen per scan of the screen.
To provide a cursor display method in which the pulse output position of a cursor display signal is offset so that the cursor is also displayed twice per one screen scan in a two-screen display method using CRTC generated on an LCD panel. i.e.
Latch the memory address when the CRTC outputs the cursor display signal, compare the memory address with the offset address, and when they are equal, forcefully output the cursor display signal to display the cursor twice. That's what I do. Here, when controlling the screen by dividing it into two using CRTC, the screen will be rewritten twice during one period of the vertical synchronization signal output by CRTC, and the characters will be rewritten twice during one cycle of the vertical synchronization signal output by the CRTC. However, according to the present invention, the pulse position of the cursor display signal output by the CRTC is offset so that the cursor is hit twice during one period of the vertical synchronization signal, and the character is displayed twice in between. Not only that, but the cursor is also prevented from becoming too dim.

[Industrial application field]

The present invention divides the screen of the LCD panel into upper and lower halves so that it can also control the LCD panel using the CRTC that controls the CRT, and displays characters simultaneously in each area during one scan of the screen. Applicable to the two-split display method. By applying an offset to the output pulse position of the cursor display signal output by the CRTC and displaying the cursor once in each area of the screen during one cycle of the vertical synchronization signal output by the CRTC, the cursor is struck twice. This shows the cursor display method using a CRT controller.

[Conventional technology]

A raster scan type CRT display device decodes commands from the CPU interface section and keyboard section, and also processes received data.
Data stored in the VRAM memory section and data read from the memory section are sent via the interface.
It has a control section that can transfer data to the CPU and also perform editing control of the display screen. The VRAM memory stores display data for one screen, reads the display data sequentially from this memory, converts character codes into character patterns, and generates video signals for forming characters. Therefore, in order to drive the deflection circuit of the display section, it is necessary to generate horizontal and vertical synchronizing signals in the synchronizing signal generating section. Therefore, the CRTC
It has an address generation section that can randomly access VRAM addresses, and also has a function of generating the horizontal and vertical synchronization signals. In addition, in the raster scan method, one set of deflection circuits for each of the X and Y axes is used to perform high-speed horizontal scanning similar to a television, and the CRT's electron beam is controlled by video signals to display characters, etc. Therefore, horizontal scanning has the function of scanning from the upper left corner of the screen to the lower right corner at once. On the other hand, in LCD devices,
Due to the characteristics of liquid crystal panels, there is a limit to the number of lines that can be displayed, and while CRTC allows horizontal scanning of up to about 200 lines, the limit for LCD panels is about 100 lines. Therefore,
Conventionally, it was inappropriate to scan an LCD panel using a CRTC, which controls scanning about 200 lines at a time. Furthermore, if the cursor display signal output from the CRTC is used to directly control the LCD cursor, the cursor will appear only once in each period of the vertical synchronization signal output from the CRTC, and therefore the cursor display will be dimmed. There was a problem in that it gave the user a sense of discomfort.

[Problem that the invention seeks to solve]

In order to solve these conventional drawbacks, the present invention latches the memory address at which the CRTC outputs the cursor display signal, compares the memory address with the offset address, and determines whether the addresses are equal. To provide a cursor display method that displays the cursor twice at the same display position for each scan of the screen by forcibly outputting the cursor when the screen is scanned.

[Means for solving problems]

The present invention provides a CRT controller that generates a memory address for a screen memory and outputs vertical and horizontal synchronization signals and a cursor display signal for instructing cursor display, and an offset applied to the memory address output from the CRT controller. offset means; memory address holding means for holding the memory address at the time when the cursor display signal was output;
Comparing means is provided for comparing the memory address held in the memory address holding means and the offset address, and when the offset address and the address held in the memory address holding means match, the cursor display A cursor display method using a CRT controller, characterized in that the cursor is displayed on a liquid crystal panel by generating the signal again and outputting a cursor display signal twice in each period of the vertical synchronization signal outputted by the CRT controller. Configure.

[Effect]

It latches the memory address when the CRTC outputs the cursor display signal, compares the memory address with the offset address, and if the addresses are equal, the half area of the screen where the current cursor is being Forcibly outputs the cursor display signal to the other half area.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 2 is a circuit configuration diagram illustrating a two-screen split screen display method by CRTC to which the cursor display method of the present invention is applied. CRTC1 is a one-chip LSI that generally controls a CRT display device.
Character displays use the same raster scanning method used for television broadcasting as the CRT spot scanning method. CRTC1 is a CRT controller compatible with this raster scan method. Characters or symbols to be displayed are written into the VRAM 4 from the CPU via, for example, a keyboard or an interface.
Then, in synchronization with the horizontal or vertical scanning of the CRT, the address of the VRAM 4 is scanned, and when that address is given to the VRAM 4, the output of the VRAM 4 is sent to the character generator 5.
In addition to this, the brightness data of the dots that make up the characters are read out from there and converted into brightness signals according to the brightness data. This signal is amplified by a video amplifier, and the cathode of the CRT is applied to the grid to modulate the brightness and display the characters or symbols on the display. Therefore, the CRTC1 is a video
A horizontal synchronization signal (HSYNC) 10 and a vertical synchronization signal (VSYNC) 11 are output to generate a memory address MA for accessing RAM, that is, VRAM 4, and also to obtain horizontal and vertical scanning periods for spot scanning. do. The horizontal synchronizing signal 10 is a pulse signal that is output every time the screen is scanned horizontally, and the vertical synchronizing signal 11 is a pulse signal that is output every time one screen is scanned. Further, the CRTC 1 outputs a cursor display signal 14, which is the vertical synchronization signal 1.
This is a pulse signal that is output only once in each period of 1. This pulse signal is a signal that controls the cursor to be displayed at the screen position corresponding to the time when the pulse signal is output. It has already been established that a circuit as shown in Fig. 2 can be added to the output section of the CRTC 1 so that the CRTC 1 suitable for controlling such a CRT can also be used to control a liquid crystal panel, that is, an LCD panel device. Filed by the inventor. This additional circuit divides the screen into two and simultaneously displays characters on the upper and lower halves of the screen during one screen scan, allowing the CRTC1 to control the LCD device as well. This is how it was done. That is, the memory address MA generated from the CRTC1 is input to this additional circuit, and when this memory address MA is an address for accessing a pixel corresponding to the upper or lower half area of the screen, it is input to this additional circuit. An offset address generation circuit 2 is provided for generating an offset address for accessing a corresponding pixel. Further, the additional circuit has a selection circuit 3, into which the memory address MA13 and the offset address 20 are input, and output from the CPU via an interface (not shown). Address signals are input through address bus 30. Then, either the memory address MA13 or the offset address 2
0 or the address 30 from the CPU, and its output 31 is applied to the VRAM as an address signal. Furthermore, the above
The output data from the VRAM 4 is input to the character generator 5, and the signal output from the CRTC 1 is also input to the character generator 5 via the raster address conversion circuit 41. is input to the video control circuit 6. This video control circuit 6 is
Each control signal of the horizontal synchronization signal 10, vertical synchronization signal 11 and display period instruction signal 12 output from the CRTC 1 is input, and when the display period instruction signal 12 is in a logic 1 state, the CRTC 1 selects one screen at the upper left corner of the screen. The character corresponding to the memory address MA and the offset address 20 are controlled to perform spot scan from to the lower right corner.
The two characters corresponding to the characters are outputted to a display device, particularly the LCD panel device 7. Then, while the CRTC1 itself accesses VRAM4 for 1 byte, an offset is forcibly applied so that it can access 2 bytes.

The video control circuit 6 shown in FIG.
The character specified by the memory address MA output from CRTC1 and the character corresponding to the offset address are latched into an internal latch circuit, and each character is sent to the screen on the LCD panel via the panel drive circuit. half one
This makes it possible to simultaneously display a point and a corresponding point in the lower half. The present invention provides a control circuit for controlling cursor display inside the video control circuit 6, and controls the cursor so that the cursor is displayed twice at one point on one half of the screen while the CRTC 1 scans the screen once. This relates to display methods. The control circuit latches the memory address at which the CRTC 1 outputs the cursor display signal 14, compares the memory address with the offset address, and when they are equal, forces the cursor display signal to be output again. It is something.

Next, the control circuit will be explained in detail using FIG. 1. FIG. 1a is a block diagram of the cursor control circuit. In this block diagram, the signal input from the left part is a direct signal output from the CRTC 1 or a signal generated by converting the signal output from the CRTC 1. The cursor display signal 14 from the CRTC 1 is a pulse signal that is output only once in each cycle of the vertical synchronization signal 11 output from the CRTC 1, and the cursor is placed at the position on the screen that corresponds to the time when the pulse signal is output. It will be displayed. Also, memory address MA13 from CRTC1 is sent via selector 3.
This is a memory address that is also given to the VRAM 4 and can specify any position on the screen to display a character.

On the other hand, offset address 20 is an offset address output from offset generation circuit 2 which applies an offset to memory address MA output from CRTC1. Memory address from CRTC1
MA is input to the comparison circuit inside this offset generation circuit 2, and the memory address MA is
The comparison circuit determines whether the memory address for the screen consisting of 640×200 dots corresponds to the address of the upper half screen or the address of the lower half screen, and the memory address MA
specifies the top of the screen, the output of the internal offset value generation circuit is set to the MA address.
An internal judgment circuit instructs to add an offset address value corresponding to the number of characters for 100 lines, and an internal adder circuit outputs the offset address. Furthermore, if the memory address MA specifies one point in the lower half of the screen and specifies an address corresponding to a pixel position within the lower half area, the memory address MA specifies an address corresponding to a pixel position within the lower half area, under the control of the offset value generation circuit. The internal decision circuit issues a subtraction command to the internal adder to perform subtraction. The adder then subtracts the address corresponding to the number of characters for 100 lines from the current address specified by the memory address MA, and outputs it as an offset address. The latch circuit 50
It latches the memory address 13 when the CRTC 1 outputs the cursor display signal 14. Therefore, the trigger input of latch circuit 50 is the latch clock (LATCHCLK), a signal equivalent to cursor display signal 14. The memory address temporarily held by the latch circuit 50 is compared with the offset address 20 by the comparison circuit 51, and if the cursor memory address at the time when the cursor display signal 14 is output is equal to the offset address, then For example, comparator circuit 51 outputs a logic 1 on output line 510 and outputs a new offset cursor signal 60 that has been offset. In order to output this offset cursor signal 60, the output method is different depending on whether the cursor display signal 14 output from the CRTC 1 is output on the upper half of the screen or the lower half. A determination circuit is required to determine whether the current cursor position is in the upper half or lower half of the screen. This cursor up/down determination circuit is constituted by a cursor position generation circuit 61 and a cursor cycle generation circuit 62. Before explaining these circuits, we will use the timing chart in Figure 1b to show the difference in output of the offset cursor signal when the cursor display signal 14 is output in the upper half of the screen and when it is output in the lower half of the screen. Explain that the aspects are different. 1st
The signal indicated by waveform V in the timing chart of FIG. b is a vertical synchronization signal (VSYNC) output from the CRTC 1, and is a pulse signal output once per screen scan. Furthermore, waveform F shown below waveform V is a frame pulse signal,
This signal is a logic 0 when the upper half of the screen is being scanned, and is a logic 1 when the lower half is being scanned. Therefore, this waveform F is CRTC1
The horizontal synchronization signal (HSYNC) output from
It is a signal generated from the output of a counter produced by counting times. In other words, assuming that the entire screen has 200 lines, it rises to logic 1 when the first 100 lines are scanned, and changes from logic 1 to logic 0 when the second half 100 lines are scanned.
It is a signal that goes down. Now, if the current cursor position is at one point in the upper half of the screen, the cursor display signal 14 will be the same as the frame pulse signal F as shown in waveform C, as shown in the upper diagram of FIG. 1b. The pulse waveform is output with a delay of a phase difference T ₁ corresponding to the current cursor position from the falling edge. This cursor display signal C is actually a signal output from the CRTC 1, but a signal obtained by applying an offset to this signal is an offset cursor display signal (OC). That is, in the timing chart shown in the upper part of FIG. 1b, the cursor display signal C is a signal when the cursor is located in the upper half of the screen. Therefore, the offset cursor display signal (OC) is the same with respect to the next rising edge of the frame pulse signal F so as to correspond to the pulse position of the waveform C, that is, the pulse position delayed by _T1 from the falling edge of the frame pulse signal F.
This is a pulse signal that is output after a delay of _T1 . In other words, the offset cursor display signal (OC) is generated when the pulse position is added by the phase difference corresponding to the screen address corresponding to the position of 100 lines on the screen from the pulse position of waveform C.
A pulse is output as . Therefore, the newly generated cursor display signal 60 is the OR of waveform C and waveform OC, and the cursor is again displayed at the position corresponding to the pulse position of waveform C in the upper half of the screen. Therefore, the vertical sync signal
The cursor will be displayed twice during one VSYNC cycle. Similarly, the current cursor position is
If the cursor is in the lower half of the screen as shown in the C waveform shown at the bottom of Figure b, that is, the pulse position of the cursor display signal C is the same as the frame pulse signal F.
If the offset cursor display signal OC is output at a time delayed by _T2 from the rising edge of the frame pulse signal F, the pulse position of the offset cursor display signal OC is not the pulse signal outputted at the same time _T2 delayed from the falling edge of the frame pulse signal F. must not. Therefore, the offset is generated by subtracting the phase difference of 100 lines, rather than adding the phase difference of 100 lines as the screen address. Therefore, the manner in which the offset cursor display signal OC is generated differs depending on whether the cursor display signal C is output in the upper half of the screen or the lower half of the screen.

Taking these differences into consideration, the cursor up/down determination circuit will be described in detail. The cursor cycle generation circuit 62 in FIG. Signal VSYNC
11, and then input the cursor position generation circuit 61.
The 3 bits of the raster address are input. The detailed structure of each block of the cursor control circuit shown in FIG. 1a is shown in FIG. 1c. In the circuit diagram of FIG. 1c, M ₅₈ and M ₅₉ are the latch circuit 50 of FIG. 1a, and M ₆₀ , M ₆₁ ,
The _M62 IC corresponds to the comparator circuit 51 in FIG. 1a. That is, _M58 and _M59 are D-type flip-flops, and memory address buses _MA0 to M59 are D-type flip-flops.
The 11 bits up to MA ₁₀ are latched by the cursor display signal (CURDISPDLY), and each output bit is directly input to the A input side of the comparator circuits M ₆₀ to _{M 62} . Further, the offset address is input to the B input of the comparison circuit. Therefore, the memory address at the time when the cursor display signal 14 is output is latched in _M58 and _M59 , and the memory address and offset address are compared by the comparison circuits _M60 , _M61 , and _M62 . . If the memory address and offset address are equal, the A=B output of _M60 will be a logic 1. This A=B signal is generated by the cursor position generation circuit 61.
is input to the 4D input terminal of the D type register M113. That is, the signal A=B is set in the flip-flop of each bit of the IC M113 along with the three bits of the raster address {RA0, RA1, RA3} at the rising edge of the CRTCSIDE signal. This cursor position generation circuit 6
1 is the output of the cursor cycle generation circuit 62, which will be described later.
Gating is performed by an _M28 AND circuit, and the gating conditions are determined by the 3-bit raster addresses RA0, RA1, RA2 and the A=B signal output from the comparison circuit 51. That is, the logic circuit in the output section of the cursor position generation circuit 61 receives the output of the cursor period generation circuit 62.
The conditions for dataing the output of _M28 are RA0, 1,
It is determined if the respective logics of 2 are 0, 1, 0 or 1, 0, 0. In other words, the cursor is displayed when the raster address is address 1 or 2 among the raster addresses 0 to 7 and the memory address is equal to the offset address, so under this condition the output of the cursor cycle generation circuit is It will be gated to the output of the _M28 AND circuit. The cursor cycle generation circuit 62 generates a VSYNCDLY signal, which is almost equivalent to the vertical cycle signal from the CRTC1, and a horizontal synchronization signal HSYNC.
A signal SCRSEL equivalent to the frame pulse signal F generated by counting 100 times is input, and an offset cursor signal OC (see FIG. 1b) is output. That is, the cursor display signal (CURDISPDLY) is input to the clock of the upper D-type flip-flop _M63 when the SCRSEL signal is a logic ₀ , and when the SCRSEL signal is a positive logic 1. Sometimes it is input to the clock of the lower flip-flop _M63 . It is also a D-type flip-flop.
M ₁₁₅ uses the SCRSEL signal itself as a horizontal synchronization signal
When HSYNC=0, logic 1 is set, and when the set signal is positive logic 1, the lower flip-flop _M63 becomes non-cleared. The non-cleared state of the upper _M63 data flip-flop is the vertical synchronization signal (VSYNCDLY).
This is when the logic is 1. Now, if the flip-flop is in a non-clear state, the SCRSEL signal is logic 0.
Assume that That is, when the upper half of the screen is specified. In this case the and gate
M ₁₁ , since the output of M ₁₁₄ below is logic 0, M ₁₁₅ ,
No clock is input to the lower _M63 flip-flop, and a cursor display signal (CURDISPDLY) is input only to the upper _M63 D-type flip-flop. Then, when this cursor display signal is input, a clock is input and _M63 enters the set state. 1st
As shown in Figure b, when there is a pulse of the cursor display signal C, the VSYNC signal is logic 0.
However, at this time, VSYNCDLY is logic 1, causing the D-type flip-flop _M63 to be in a non-cleared state, and _M63 to be in a set state. Therefore, _M63 becomes 0, and a frame pulse signal is sent to terminal 1 of _M21 .
SCRSEL becomes logic 1 and is output. In other words, the cursor displayed at the top of the screen is also displayed at the bottom of the screen.
A pulse is generated at the output of the AND gate of _M28 via _M65 . From this state, when the SCRSEL signal, that is, the frame pulse signal F becomes logic 1 and the scanning moves to the lower half of the screen, the lower flip-flop of D type flip-flop _M63
A pulse is input to the clock input of the _M115 flip-flop. That is, when the cursor display signal (CURDISPDLY) is output, those flip-flops are set. At this time, HSYNC is logic 0, that is, while the screen is being scanned horizontally, the clear signal of _M115 is logic 1.
Since it does not enter, M ₁₁₅ is in a non-cleared state.
Therefore, when the SCRSEL signal becomes logic 1,
Since _M115 is in the set state, the Q output becomes 1,
The lower M ₆₃ is in a non-clear state. If the cursor display signal C becomes logic 1 in this state,
Since the SCRSEL signal is 1, the lower _M63 is in the set state. That is, the output becomes logic 0,
The output of terminal 4 of _M21 becomes a pulse and is outputted via inverter 65 when the SCRSEL signal changes to logic 0. This means that the cursor displayed at the bottom of the screen will be displayed again at a corresponding point at the bottom of the screen. That is, the cursor cycle generating circuit 62 generates the offset cursor display signal OC from the cursor display signal of waveform C as shown in FIG. 1b. _M116 is a selection circuit which outputs the cursor display signal C directly or outputs an offset cursor display signal to this cursor display signal.
each OC is selected by the CRTCCLK signal,
The cursor display signal C and the offset cursor display OC signal are always output twice during one period of the vertical synchronization signal via the D-type flip-flop _M113 . Therefore, in the present invention, CRTC1 is used as a cursor display signal.
Latch the memory address when outputting OC,
The memory address and offset address are compared, and if they are equal, a cursor is output, and the cursor is displayed twice during each period of the vertical synchronization signal output by the CRTC1.

Hereinafter, the embodiment of the present invention will be described as a memory address.
Taking as an example the case where MA is 4 bits, that is, 16 addresses, a more specific explanation will be given in comparison with a case where the present invention is not implemented.

For example, FIG. 3 is a (display) diagram showing the display position of the cursor when the present invention is not implemented, and FIG. 4 is a diagram showing the memory address MA corresponding to the upper half of the screen.
This is a diagram showing the display position of the cursor when CURDISP is output while CRTC is outputting. Figure 5 shows the memory address corresponding to the lower half of the screen.
FIG. 7 is a diagram showing a display position when CURDISP is output while CRTC is outputting MA. In each figure, a and b indicate the memory address of the CRTC, and c and d indicate the corresponding scanning position on the screen.
~ indicates the display position on the screen corresponding to the memory address '~', ▼ indicates a, b indicates that the occurrence occurred while CURDISP was accessing that address,
c and d indicate that the cursor is displayed at that position.

As shown in FIG. 3a, when the present invention is not implemented, when memory addresses .about. are sequentially output from the CRTC, an offset value of +8 is added to these addresses to create an offset address. Therefore, while the CRTC outputs the address of ~, the information of the address ~ is read from the memory using the memory address and the offset memory address. Therefore, on the screen, as shown in c, positions '-' and '-' on the screen are simultaneously scanned.

On the other hand, when the CRTC is outputting address ~, the offset value becomes -8. For example, MA
When , the offset address is .
Therefore, as in c and d, the upper and lower sides of the screen are simultaneously scanned.

However, since CURDISP is output only once while CRTC outputs MA~, MA is
When it is displayed like c, MA is ~
When , it is not displayed as shown in d.

On the other hand, a case where the present invention is implemented is shown.

In Figure 4, when MA is ~
When CURDISP occurs, MA is ~
Suppose that CURDISP occurs in Therefore, at this time, the cursor is displayed at position 'c'.
When MA becomes ~, the offset address becomes ~. In the present invention, when the held MA=offset address, CURDISP is generated again. Therefore, when MA=, the offset address becomes, which is the same as the retained MA, so
CURDISP is output when the MA of CRTC becomes . Therefore, even when the CRTC outputs the address ~ as b, the cursor is displayed at the position d.

In addition, in FIG. 5 showing another example of implementing the present invention, when MA is ~, CURDISP
If this occurs, CURDISP is generated with MA= as shown in a. MA= is held and a cursor is displayed on the screen at a position as shown in c. When MA reaches , it returns to b again. Next, when MA becomes, the offset address becomes. Since this is the same as MA= held, CURDISP is generated at this time. Therefore, the cursor is displayed again at the position d.

〔Effect of the invention〕

In this way, in the present invention, the CRTC is used to generate a cursor display signal and an offset cursor display signal once each in each period of the vertical synchronization signal output from the CRTC, and a new cursor display signal is generated as the OR logic of these signals. Since the configuration is configured to generate
The effect is that the display is displayed on the LCD panel without becoming dim, and does not give the user a sense of discomfort.

[Brief explanation of drawings]

FIG. 1a is a cursor control circuit diagram according to a method of applying an offset to the cursor display signal of the CRTC of the present invention, FIG. 1b is a timing chart of the cursor control circuit of the present invention, and FIG. 1c is a diagram of the cursor control circuit of the present invention. Detailed circuit diagram of the control circuit,
Figure 2 is a circuit configuration diagram according to the CRTC two-screen display system, Figure 3 is a display diagram showing the cursor display position when the present invention is not implemented, and Figure 4 is the memory address MA corresponding to the upper half of the screen. CRTC
A display diagram showing the display position of the cursor when CURDISP is output while is outputting, Figure 5 shows the memory address MA corresponding to the lower half of the screen.
FIG. 7 is a display diagram showing the display position when CURDISP is output while CRTC is output. DESCRIPTION OF SYMBOLS 1... CRTC, 2... Offset address generation circuit, 3... Selection circuit, 4... VRAM, 5... Character generator, 6... Video control circuit, 7...
LCD panel device, 8...timing generation circuit, 9
...Selection circuit, 10...Horizontal synchronization signal, 11...Vertical synchronization signal, 12...Display period instruction signal, 13...Memory address (MA), 14...Cursor display signal, 50...Latch circuit, 51...Comparison circuit, 60
...Offset cursor signal, 61...Cursor position generation circuit, 62...Cursor cycle generation circuit, V...
VSYNC, F...Frame pulse signal, C...Cursor display signal, OC...Offset cursor display signal, _M58 , _M59 ...Latch circuit,
_M60 , _M61 , _M62 ...Comparison circuit, _M113 ...Register,
_M28 ...AND circuit, _M63 , _M115 ...flip-flop, _M116 ...selection circuit.

Claims (1)

[Claims] 1. Generates a memory address for the screen memory, and outputs vertical and horizontal synchronization signals and a cursor display signal for instructing cursor display.
a CRT controller; an offset means for applying an offset to the memory address output from the CRT controller; a memory address holding means for holding the memory address at the time when the cursor display signal is output; and the memory address holding means. Comparing means for comparing the memory address held in the memory address holding means and the offset address is provided, and when the offset address and the address held in the memory address holding means match, the cursor display signal is generated again. A cursor display method using a CRT controller, characterized in that a cursor display signal is output twice in each cycle of a vertical synchronization signal outputted by the CRT controller to display a cursor on a liquid crystal panel.