JPH0371637A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To realize simultaneously the formation of contact holes and a flattening of the surface of a substrate and to contrive an increase in the integration of an element and the improvement of the yield of the manufacture of the element by a method wherein after the film thickness of an insulating film at contact parts is formed thin and the film thickness of the insulating film on the substrate surface part other than the contact parts is formed thick, a heat treatment is performed and the insulating film is flowed. CONSTITUTION:An impurity is prevented from being diffused from second and third insulating films 12 and 16 containing the impurity into a semiconductor substrate by a first insulating film 10. Moreover, after a prescribed region of the film 12 is etched, the film 16 is formed to form an insulating film having a partially different film thickness and the film thickness of the insulating film on nozzles in contact parts is made thin. When a heat-treat process is performed on this insulating film, the part of a thick film thickness is fluidized and a flat surface is obtained. On the other hand, the film thickness of the part of a thin film thickness is hardly charged even after the heat treatment. Thereby, fine contact holes can be formed by the following etching process in a self-alignment manner and as the substrate surface other than the contact parts is formed flatly, the generation of a short circuit and a disconnection can be prevented at the time of formation of a second wiring pattern.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a method for manufacturing a semiconductor device that is effective for forming fine contacts between wiring and a substrate in the case of high integration of ultra-LSIs and the like.

(Prior Art) As dynamic random access memories (DRAMs) become highly integrated, the spacing between word lines becomes finer, and it is necessary to make the contacts between bit lines and diffusion layers finer. Therefore,
Conventionally, various methods of forming contacts between bit lines and diffusion layers in a self-aligned manner have been studied. For example, the method shown in Fig. 2 described in the Proceedings of the 35th Japan Society of Applied Physics 28P-V-14 has been studied. be. In FIG. 2, 102 is a silicon (Si) substrate, 103, 105.107.108.10
9.118 is a silicon oxide film (Sin, film), 104 is an n0 diffusion layer, and 106.112 is a polysilicon film (Pol).
y S j film), 110 is a silicon nitride film (Si3N,
membrane), 114 is a boron phosphorus glass membrane (BPSG membrane),
116 is a resist film pattern, 120 is a contact hole, and 122 is a W polycide wiring.

Next, the manufacturing process of the above conventional example will be explained.

As shown in FIG. 2(A), a phosphorus-doped PolySi film pattern 106 (
106A to 106C) and n” diffusion layer 104 (104A
~104D) is formed, and a thermal oxide film (Su
n, film) 109 (109A to 1090), S i N
4 membranes 110. After sequentially forming the PolySi film 112, a 14-stroke film pattern 116 is deposited on the BPSG film 11 (FIG. 2(B)). Next, as shown in FIG. 2(C), predetermined areas of the BPS'G film 114 and the PolySi film 112 are covered with a resist film pattern 116 (116A,
116B) as a mask. After that, heat treatment is performed in a steam atmosphere, and the BPSG film 11 is
4A, 11413) and oxidizes the PolySi film 112 (112A, 112B). Then, Si3N film 110 and SiO2 film 10 film 09 were etched in predetermined areas.

As shown in FIG. 2(E), contact hole 120 (1
20A, 120B) are formed in a self-aligned manner. Here, the Poly Si film 112 serves as an etching stopper when etching the BPSG film 11, and then the remaining Poly Si film 112 (112A, 1
12B) by oxidizing the W polycide wiring 1
22 is prevented from occurring.

(Problems to be Solved by the Invention) However, the above conventional manufacturing method has the following problems.

(1) Short circuits of the W polycide wiring 122 are likely to occur.
In other words, Po1y Si[112(112A, 112B
) to oxidize Sio, film 118 (118A, 118
B), the PolySi film 112 (1
12A, 112B) remain without being completely oxidized, W
A short circuit occurs in the polycide wiring 112. Especially at the bottom corner of the stepped part, Po1. The oxidation rate of the ySi film is extremely slow, and oxidation residues are likely to occur.

(2) PolySi film 112 (112A, 112
The oxidation step B) affects the MOS transistor characteristics. In other words, the PolySi film 112 (112A, 1
In order to sufficiently oxidize 12B), long-term or high-temperature heat treatment is required, and the demand for lowering the manufacturing process temperature accompanying miniaturization of elements cannot be fully met.

The present invention solves these conventional problems,
It is an object of the present invention to provide a method for manufacturing a semiconductor device that has an excellent manufacturing yield and enables high integration of elements.

(Means for Solving the Problems) In order to achieve the above object, the present invention includes a step of forming a first insulating film on a semiconductor substrate on which a first wiring pattern is formed, and a step of forming a first insulating film on a semiconductor substrate on which a first wiring pattern is formed. A step of forming a second insulating film containing an impurity on top with a thickness of 1/2 of a predetermined film thickness, a step of etching a desired region of the second insulating film containing the impurity, and a step of etching the impurity on the entire surface. a step of forming a third insulating film with the same thickness as the second insulating film; a heat treatment step of fluidizing the second and third insulating films; The method includes a step of etching an insulating film to form a connection hole between the first wiring patterns, and a step of forming a second wiring pattern and connecting the semiconductor substrate and the second wiring in the connection hole. This is the manufacturing method.

(for production) Therefore, the present invention has the following effects.

(1) The first insulating film prevents impurities from diffusing into the semiconductor substrate from the second and third insulating films.

(2) By etching a predetermined region of the second insulating film and then forming the third insulating film, an insulating film having partially different thicknesses can be formed. When the heat treatment process is performed, the thicker portions of the film flow and a flat surface is obtained. On the other hand, since the thin film thickness hardly changes even after heat treatment, fine contact holes can be formed in a self-aligned manner in the next etching process.

(3) In the heat treatment process, since the surface of the substrate outside the contact portion is flat, short circuits and disconnections can be prevented when forming the second wiring pattern.

(Embodiment) FIG. 1 shows a manufacturing process of a semiconductor device according to an embodiment of the present invention, and shows a contact formation process between a DRAM bit line and a cell diffusion layer.

In Figure 1, 2 is the SL board, 3, 5, 7, 8 are 5i
n2 film, 4 is n0 diffusion layer, 6 is PolySi film (first
wiring pattern), 10 is a SiO□ film (first insulating film)
, 12 is a BPSG film (second insulating film), 14 is a resist film pattern, 16 is a BPSG film (third insulating film), 17
18 is a BPSG film, 18 is a contact hole, and 20 is a W polycide wiring (second wiring pattern).

Next, the manufacturing process of the above embodiment will be explained.

As shown in FIG. 1(A), a Sin
, film 3 (3A, 3B), n which becomes the source/drain region
+ Diffusion layer 4 (4A to 4D), gate oxide film 5 (5A
~5G), Po1y Si wiring 6 (6A
~6C) and chemical vapor deposition method (CV D method)-5in, film 7
(7A to 7C) and 8 (8A to 8F) were formed on a P-type Si substrate 2 as a semiconductor substrate, a film 10 of 50 Bm of Sin was deposited as a first insulating film by low pressure CVD method,
Next, BPS is deposited as a second insulating film by atmospheric pressure CVD.
150 Bm of G film 12 is deposited. First, as shown in FIG. 1B, a resist film pattern 14 (14A, 14B) as an etching mask material is formed, and the BPSG film 12 is dry etched. At this time, the size of the contact portion is determined by the spacing between the Po1y Si wirings 6 (6A, 6B), and the opening area of the resist film pattern can be made larger compared to the contact area, so that it is possible to prevent mask misalignment. Contact openings can also be formed at predetermined positions. After that, the resist film pattern 14 (
14A, 14B) As shown in FIG. 1(C), B as the third insulating film is
Deposit 150 tv+ of P S G11116. At this time, the BP of the etched part in FIG. 1(B)
The thickness of the SG film is 150 Bm, whereas the thickness of the unetched portion is 300 N+m. This point is one of the extremely important points of the present invention. When heat treatment is performed at 900°C in an N2 atmosphere, a BPSG film with a thickness of 300 Bm is formed as shown in Figure 1 (D). It flows and a flat surface is obtained. On the other hand, there is no significant change in the thickness of the 150 nm thick BPSG film. Therefore, it is possible to flatten the substrate while leaving the level difference in the contact portion. Next, by dry etching the substrate surface, the BPSG film 17 is etched, as shown in FIG. 1(E).
A fine contact hole 18 is formed in a self-aligned manner as shown in FIG.
(18A, 18B) are PolySi wiring 6 (6A,
6B) is formed between. At this time, B at the contact part
Since the PSG film is thin, contact holes can be easily formed even if the overetching rate is reduced.

This becomes possible only when the shape of the PSGS upper film is obtained as shown in the construction drawing CD). Therefore, an etching stopper film is not necessary.6 Next, low pressure CVD
After depositing a PolySi film of 90n+m by a sputtering method, a W silicide film of 00n@ was deposited by a sputtering method to form a W polycide film 20 that will become a bit line as shown in FIG. 1(F). The expansion layer is connected in contact hole 18 .

Furthermore, since the substrate surface is flattened on the BPSG film 17 at this time, short circuits and disconnections of the W polycide wiring do not occur.

In addition, in the above embodiment, Sio,
Although an example using a film has been described, Si, N, and films may also be used. In addition, as a method for forming Sin and film IO, reduced pressure C
Although the VD method was used, normal pressure CVD method or plasma CV
Method D may also be used.

Similarly, although the normal pressure CVD method was used as a method for forming the BPSG film, a low pressure CVD method or a plasma CVD method may be used.

Further, although dry etching was used in the step of etching the BPSG film 12, a combination of dry etching and wet etching may be used.

Furthermore, a phosphorus glass (PSG) film or arsenic glass (AsSG) may be used instead of the BPSG film.

(Effects of the Invention) As is clear from the above examples, the present invention has the following effects.

(1) Formation of contact holes and planarization of the substrate surface can be achieved at the same time by making the BPSG film thinner in the contact area and thicker in other parts, and then heat-treated to cause the BPSG film to flow.

(2) Since the size of the contact is determined by the spacing between the word lines (Poly Si wiring), fine contacts can be formed in a self-aligned manner.

(3) Since the substrate surface is flattened by the BPSG film, short circuits and disconnections do not occur during formation of bit lines (W polycide wiring).

(4) In the etching process during contact formation, the overetching rate can be reduced because the BPSG film in the contact area is thin, and the substrate can be prevented from being excessively etched even without an etching stopper film. .

(5) By forming a Sin film between the BPSG film and the substrate, it is possible to prevent boron and phosphorus from diffusing into the substrate.

(6) Since the Po1y Si film is not used as an etching stopper, there is no problem of wiring short circuits due to the remaining Po1y Si film.Also, there is no need to oxidize the Po1y Si film, so the heat treatment time for BPSG is shortened. It is well suited for miniaturization of elements.

As described above, since fine contact holes can be formed in a self-aligned manner and the substrate surface can be flattened, higher integration of elements and improvement in manufacturing yield can be achieved.

[Brief explanation of drawings]

1 is a process sectional view of a method for manufacturing a semiconductor device according to an embodiment of the present invention, and FIG. 2 is a process sectional view of a conventional method for manufacturing a semiconductor device. 2.102...SL board + 3.5, 7, 8, 1
03, 105.107.108.109.118...
SiO2 film, 4, LO4-n” diffusion layer, 6,
106...PolySi film (first wiring pattern),
10...S io, film (first insulating film), 12.
...BPSG film (second insulating film), 14.116...
・Resist film pattern, 16...BPSG film (third
(insulating film), 17.114...BPSG film, 18
...Contact hole, 20.122...W polycide wiring (second wiring pattern), 110...S
i, N, film, 112...PolySi film.

Claims (1)

[Claims] a step of forming a first insulating film on a semiconductor substrate on which a first wiring pattern is formed; a step of forming a second insulating film containing impurities on the first insulating film; and a step of forming a second insulating film containing impurities on the first insulating film; etching a desired region of the second insulating film;
a step of forming a third insulating film containing impurities over the entire surface; a heat treatment step of fluidizing the second and third insulating films; etching the first to third insulating films in desired regions; A semiconductor characterized by comprising a step of forming a connection hole between first wiring patterns, and a step of forming a second wiring pattern and connecting the semiconductor substrate and the second wiring in the connection hole. Method of manufacturing the device.