JPH036978A - Picture processor - Google Patents

Abstract

PURPOSE:To decrease number of line memories and to make the circuit small by providing a compensation means compensating dropout of a picture signal with a delay means in the case of writing a picture signal to a storage means and a processing means using the delay means to apply other processing when the picture signal is read from the storage means. CONSTITUTION:A dropout detection circuit 54 detects dropout from an output of an equalizer 28 to control switches 40, 56 by the result of detection. That is, at production of the dropout, the switch 40 is thrown to the position of the output of a memory 46, the signal is replaced with a preceding line signal and the switch 56 is thrown to the position of the output side of a horizontal synchronizing separator circuit 52 to select a horizontal synchronizing signal from the output signal of the memory 46. Moreover, the switch 56 is thrown to the position of the output of a horizontal synchronizing separator circuit 50. A PLL circuit 58 forms the operating clock of the memories 44, 46, and A/D converters 27, 38 and the write clock of the memory 48 according to the horizontal synchronizing signal selected by the switch 56.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an image processing apparatus, and more specifically to an image processing apparatus that reproduces still image signals recorded on a recording medium such as a magnetic disk.

[Prior Art] A still image recording and reproducing system using a small magnetic disk called a still video floppy disk as an image recording medium is known. This system can record 50 field images and 25 frame images on one magnetic disk. The image reproducing device used in this still image recording and reproducing system uses a -
A circuit configuration using a FIFO memory is known as an image memory device for storing images. That is, basically, a signal reproduced from a magnetic disk is demodulated and de-emphasized, and then converted into a digital signal and temporarily stored in an image memory consisting of a FIFO memory. Then, the data stored in the image memory is read out in the order in which it was written, subjected to processing such as dropout compensation and time axis correction, and then converted back to an analog signal and output as a video signal.

In the FIFO memory, write addresses and read addresses are automatically generated, so there is no need to provide a complicated address control circuit like in a general RAM, and there is an advantage that the circuit configuration can be simplified.

[Problems to be Solved by the Invention] When reproducing image signals recorded on a recording medium such as a magnetic disk, a dropout compensation circuit is essential.

Furthermore, for color difference signals, a vertical phase compensation circuit is also required. Since these circuits generally use line memories, conventional image reproduction devices use a FIFO image memory for one field and several line memories as a whole. In addition to image memory, many lines and
The use of memory increases manufacturing costs and is a factor that hinders miniaturization of circuits.

Such problems occur not only in devices that use magnetic disks, but also in devices that have a function to compensate for loss of video signals when they occur.

Therefore, an object of the present invention is to provide an image processing device with reduced line memory.

[Means for Solving the Problems] An image processing apparatus according to the present invention includes a storage means for storing an input image signal, and a delay means for compensating for dropout of the image signal when writing the image signal to the storage means. It is characterized by comprising a compensation means and a processing means that performs another processing using the delay means when reading the image signal from the storage means. In addition, the input luminance signal is
Dropout compensation means for compensating for dropouts by a delay means having a delay time corresponding to a horizontal scanning period, a luminance signal compensated for dropouts by the dropout compensation means, and an input color signal manually inputted together with the input luminance signal are temporarily stored. It is characterized by comprising a storage means and means for supplying the color signal read out from the storage means to the delay means for processing.

[Operation] With the above means, the delay means of the dropout compensation means can be used for another process. Therefore, there is no need to provide a dedicated delay means for the separate processing, and the circuit can be miniaturized.

[Example] Hereinafter, the present invention will be described in detail with reference to the drawings.

FIG. 1 shows a block diagram of an embodiment of the present invention. The magnetic disk 10 is rotated by a spindle motor 12, and the motor 12 is controlled to a constant rotational speed by a servo circuit 14. The output of the magnetic head 16 is amplified by a preamplifier 18.

An LPF (low-pass filter) 20 separates color difference components from the small RF output of the preamplifier 18, a demodulation circuit 22 demodulates them to baseband, an LPF 24 removes extra band components, and a de-emphasis circuit 26 de-emphasizes the components. . In this embodiment, the output of the de-emphasis circuit 26 is a color difference line sequential signal in which the signal R-Y and the signal B-Y alternate every horizontal scanning period. A/D converter 27
converts this color difference line sequential signal into a digital signal at a sampling frequency of 2f, c.

On the other hand, the equalizer 28 raises the high frequency range of the small RF output of the preamplifier 18 in order to improve the inversion phenomenon, and the HPF (bypass filter) 30 removes the low frequency color difference signal component in order to extract the luminance component. Demodulation circuit 32 is HPF30
After further improving the inversion by limiting the amplitude of the output, the output is demodulated to the baseband. The LPF 34 band-limits the output of the demodulation circuit 32, and the de-emphasis circuit 36 performs de-emphasis processing. The output of the circuit 36 is a so-called luminance signal. The A/D converter 38 has a sampling frequency of 4
The fsC converts the output of the circuit 36 into a digital signal.

The digital luminance signal at the output of the A/D converter 38 is passed through a switch 40, a 0.5H line memory 44 and a 0.5H line memory 46 to the FIF
The data is input to the O memory 48. The output of line memory 46 is fed back to switch 40, so that switch 40 and memories 44,46 form a cyclic compensation circuit for dropouts. WRES of the memory 48 is a write reset terminal, Mlin, M2in are data input terminals, WCKI, WCK2 are write clock input terminals, M
lout, M2out are data output terminals, RCKI,
RCK2 is a read clock input terminal, and RRES is a read reset terminal.

The horizontal synchronization separation circuit 50 separates the horizontal synchronization signal from the output of the circuit 36, and the horizontal synchronization separation circuit 52 separates the horizontal synchronization signal from the output of the circuit 36, and the horizontal synchronization separation circuit 52 separates the horizontal synchronization signal from the output of the circuit 36.
Detects and separates the horizontal synchronization signal from the A dropout detection circuit 54 detects a dropout from the output of the equalizer 28, and based on the detection result, switches 40.
56. That is, when a dropout occurs, the switch 40 is connected to the output side of the memory 46 to replace the signal from the previous line, and the switch 56 is connected to the output side of the horizontal sync separation circuit 52 to replace the output of the memory 46. Select the horizontal sync signal from the signal.

Note that the switch 56 is normally connected to the output side of the horizontal synchronization separation circuit 50.

PLL circuit 58 forms an operating clock for A/D converters 27, 38 and memories 44, 46, and a write clock for memory 48 in accordance with the horizontal synchronizing signal selected by switch 56 as described above.

Note that the switch 42 is a changeover switch for using the memories 44 and 46 for processing signals read out from the memory 48, and the switch 60 is a changeover switch for using the memories 44 and 46 for processing signals read out from the memory 48.
．． This is a switch for switching the operating clock source to 46. During dropout compensation, switch 60 is set to P
It is connected to the output side of the LL circuit 58, and the memories 44 and 46 are driven by a clock having a frequency of 4tsc.

In this way, the line-sequential color difference signal and the luminance signal delayed by IH and dropout compensated are frozen in the memory 48.

The line-sequential color difference signal output from the memory 48 is applied to a step correction circuit 62 and a CID detection circuit 64. C.I.D.
The detection circuit 64 detects whether the current line sequential color difference signal is the R-Y signal or the B-Y signal, and outputs the synchronizing signal generating circuit (SSG).
66 controls the level difference correction circuit 62 according to the detection result, and adjusts the pedestal level of each color difference signal. The signal adjusted by the step correction circuit 62 is input to the memory 44 via the switch 42. At this time, the switch 60 is connected to the output side of the synchronization signal generation circuit 66, and the memory 44
．． 46 is driven at a frequency of 2fsC. Therefore, at this time, the memories 44 and 46 each function as an IH line memory.

Adder 68 connects the input signal to memory 44 and memory 46.
and the output of and average it. By selecting the output of the adder 68 and the signal delayed by 0.5H by the memory 44 for each line, the switch 70 separates the line-sequential color difference signal into the R-Y signal' and the B-Y signal, and converts it into a digital signal. - The encoder 72 converts it into an NTSC signal. encoder 7
The output of No. 2 is converted into an analog signal by the D/A converter 74, band-limited by the LPF 76, amplified by the amplifier 78, and output from the C output terminal.

Furthermore, the luminance signal output from the memory 48 is converted into an analog signal by a D/A converter 80, band-limited by an LPF 82, amplified by an amplifier 84, and output from a luminance output terminal.

The synchronization signal generation circuit 66 generates a synchronization signal for controlling various parts of the circuit other than those described above under the control of the system control circuit 86.

In FIG. 1, the luminance signal delayed by IH is frozen in the memory 48 by the memories 44 and 46, but the input signal of the memory 44 may be frozen in the memory 48. That is, the input of the memory 44, rather than the output of the memory 46, is connected to the data input terminal Mlin of the memory 48. In this case, when reading from the memory 48, an IH time difference may be provided between the reset for reading the luminance signal and the reset for reading the color difference signal.

According to this embodiment, since the PLL circuit 58 operates stably even when a long-term dropout occurs, the video signal can be stably frozen.

Although field playback of an NTSC signal has been described as an example, it goes without saying that the present invention is also applicable to the PAL system and frame playback. In addition, horizontal synchronization separation circuit P52
can also be constructed by incorporating it into the synchronization signal generation circuit 66. In addition, in this embodiment, the line memory for compensating for dropout when writing to the FIFO memory 48 is
Although the present invention is used for interpolation processing of line-sequential color difference signals when reading from the IFO memory, the present invention is not limited to this, and can also be used for skew compensation and vertical edge enhancement processing.

Furthermore, although the description has been made in the case of processing a reproduced signal from a recording medium, the present invention is not limited to this, and can also be applied to processing of a transmitted signal. Although other memory such as RAM may be used instead of the FIFO memory, the effect is great when using the FIFO memory.

[Effects of the Invention] As can be easily understood from the above explanation, the present invention can reduce the number of lines and memories, reduce the size of the circuit, and
Manufacturing costs can be reduced.

[Brief explanation of the drawing]

FIG. 1 shows a block diagram of an embodiment of the present invention.

Claims (1)

[Scope of Claims] (1) A storage means for storing an input image signal, a compensating means for compensating for dropout of the image signal by a delay means when writing the image signal to the storage means, and an image signal from the storage means. 1. An image processing device comprising processing means for performing another processing using the delay means when reading a signal. (2) The image processing device according to claim (1), wherein the other processing is interpolation processing. (3) Dropout compensation means for compensating for dropouts of the input luminance signal by a delay means with a delay time corresponding to one horizontal scanning period, and inputting the luminance signal dropout compensated by the dropout compensation means and the input luminance signal together. 1. An image processing apparatus comprising: storage means for temporarily storing an input color signal; and means for supplying the color signal read out from the storage means to the delay means for processing. (4) The image processing device according to claim (3), wherein the input luminance signal and the input color signal are signals reproduced from a recording medium. (5) The image processing device according to claim (3), wherein the color signal is a line sequential color difference signal.