JPH036862A - Gate turn-off thyristor - Google Patents

Abstract

PURPOSE:To obtain a high di/dt strength GTO thrystor which is not broken down by a sharp current rise by a method wherein a part of a first conductivity type high resistance base layer is exposed on the surface of an anode side and a second gate electrode having a MOS structure is provided on the surface of a part of a second conductivity type base layer between the exposed part of the first conductivity type base layer and a first conductivity type emitter layer. CONSTITUTION:A part of a p<->-type high resistance base layer 3 is exposed on the surface of an anode side. A second gate electrode 11 is formed on the surface of a part of an n-type base layer 2 between the exposed part of the layer 3 and a p-type emitter layer 1 with a gate insulating film 10 between. At the time of turn-on, a bias voltage positive against the potential of a cathode 7 is applied to a first gate electrode 8 and, at the same time, a bias voltage negative against the potential of a cathode 9 is applied to the second gate electrode 11. With this constitution, electrons are injected from an n-type emitter layer 5 and, at the same time, holes are injected from the p-type emitter layer 1 through the surface channel of an n-type base layer 2 under the second gate electrode 11. By injecting electrons and holes as described above, a current can be raised sharply at the time of turn-off.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Field of Industrial Application) The present invention relates to a gate turn-off thyristor (GTO).

(Prior Art) A GTO is a thyristor that can be turned on as well as turned off using a gate electrode.

FIG. 8 shows the structure of a conventional general cyrisk. n-type emitter layer 21. N-type buffer layer 22. High resistance n-type base layer 23. p-type base layer 24 and n-type emitter layer 25
are stacked in this order to form a pnpn structure. n
Although only two mold emitter layers 25 are shown in the figure, they are usually divided into a large number of parts, and cathode electrodes 27 are formed on these. A gate electrode 28 is provided on the surface of the p-type base layer 24 surrounding the nu emitter layer 25. Two anode electrodes are formed in the n-type emitter layer 21.

The pn junction surface exposed on the cathode side is covered with an insulating film 26.

In such a GTO, at turn-on, electrons are injected from the n-type emitter layer 25, holes are injected from the n-type emitter layer 21 in response, and both of these are injected into the p-type base layer 24.
The main junction between the n-type base layer 22 and the n-type base layer 22 is forward biased. At this time, it takes a certain amount of time for the injected carriers to accumulate, which causes problems such as a delay in turn-on and insufficient tolerance for d j/d. On the other hand, at turn-off, p
After the main junction between the type base layer 24 and the n-type base layer 22 is restored and a depletion layer is formed there, a large amount of residual carriers exist in the n-type base layer 23, and this is a so-called tail current of several tens of μSee. A phenomenon occurs in which the current flows for several hundred microseconds. This not only increases the turn-off time but also increases the switching energy loss during turn-off, leading to the problem of lowering the energy conversion efficiency of the device.

(Problems to be Solved by the Invention) As described above, the conventional GTO has a problem in that di/d is not sufficient in terms of withstand capability and high frequency operation.

An object of the present invention is to provide a GTO that solves these problems.

[Structure of the Invention] (Means for Solving the Problems) The GTO according to the present invention includes a first conductivity type emitter layer, a second conductivity type base layer, a first conductivity type high resistance base layer, and a first conductivity type low resistance base layer. It has a structure in which a base layer and a second conductivity type emitter layer are laminated in this order, and an anode electrode formed on a part of the first conductivity type emitter layer and a part of the second conductivity type base layer, and a second conductivity type emitter layer. Based on the structure having the formed cathode electrode and the first gate electrode formed on the first conductivity type base layer, a part of the first conductivity type high resistance base layer has a portion exposed on the anode side surface, This part and the first
It is characterized in that a second gate electrode of a MOS structure is provided on the surface of a second conductive type base layer sandwiched between conductive type emitter layers.

(Function) In the GTO of the present invention, when turned on, a bias is applied to the second gate electrode to invert the surface of the second conductivity type base layer thereunder to operate the MOS transistor. As a result, a large amount of carriers are injected from the first conductivity type emitter layer into the first conductivity type high resistance base layer through the inversion channel. In addition, carriers are injected from the second conductivity type emitter layer by applying a bias to the first gate electrode, as in the conventional case. As a result of these carrier injections, a fast current rise is possible, and a high di/d can be achieved.

(Example) The present invention will be explained in detail below.

FIG. 1 is a sectional view showing the GTO of the first embodiment.

p-type emitter layer 1. n-type base layer 2, I)-type high resistance base layer 3. A pnpn structure consisting of a p-type high-resistance base layer 4 and an n-type emitter layer 5 is the basic thyristor structure. The p-type high resistance base layer 3 is thicker than the n-type base layer 2 and has a lower impurity concentration. The n-type emitter layer 5 is usually divided into a plurality of pieces, and the exposed surface of the pn junction formed between this and the p-type base layer 4 is covered with an insulating film 6.

The n-type emitter layer 5 includes a cathode electrode 7 and the p-type base layer 4.
A first gate electrode 8 is formed on the p-type emitter layer 1, and an anode electrode 9 is formed on the p-type emitter layer 1, respectively.

Part of the n-type base layer 2 is exposed to the surface through the p-type emitter layer 1, and the anode electrode 9 is also in contact with this exposed n-type base layer 2, forming an anode short-circuit structure. Furthermore, a part of the p-type high-resistance base layer 3 is exposed on the anode side surface, and a gate insulating film 10 is formed on the surface of the n-type base layer 2 in a region sandwiched between this part and the p-type emitter layer 1. A second gate electrode 11 is formed. That is, the second gate electrode 11 constitutes a p-channel MOS transistor having the p-type emitter layer 1 as a source and the p-type high-resistance base layer 3 as a drain.

The operation of the GTO configured in this way will be described next. At turn-on, a positive bias is applied to the first gate electrode 8 with respect to the cathode electrode 7, and at the same time, a negative bias is applied to the second gate electrode 11 with respect to the cathode electrode 9. As a result, electrons are injected from the n-type emitter layer 5, and holes are simultaneously injected from the p-type emitter layer 1 through the surface channel of the n-type base layer 2 below the second gate electrode 11. By injecting electrons and holes in this manner, a steep rise in current at turn-on is possible.

Note that the timing of applying bias to the first gate electrode 8 and the second gate electrode 11 during turn-on may be simultaneous, or one may be delayed appropriately.

At turn-off, the first gate electrode 8 is negatively biased with respect to the cathode electrode 7, and excess carriers in the p-type base layer 3.4 are discharged. At this time, the second gate electrode 11 is set to zero bias with respect to the cathode electrode 9, and the p-channel MO
The S transistor is kept off.

Thus, according to this embodiment, high-speed operation is possible and di
/d can be obtained.

Next, some other embodiments will be described. In the following embodiments, parts corresponding to those in FIG. 1 are designated by the same reference numerals as in FIG. 1, and detailed description thereof will be omitted.

FIG. 2 is a sectional view showing the GTO of the second embodiment.

In this embodiment, in addition to the structure shown in FIG. 1, an n-type layer 12 is provided within the p-type emitter layer 1. The anode electrode 9 is also in contact with this n-type layer 12. The gate insulating film 10 and the second gate electrode 11 are formed on this n-type layer 1.
It has been extended to reach the end of 2. This structure is
A p-channel MOS transistor having a p-type emitter layer 1 as a source and a p-type high-resistance base layer as a drain, and an n-channel MOS transistor having an n-type layer 12 as a drain and an n-type base layer 2 as a source. 2 gate electrode 1
It can be said that they are connected in series with 1 serving as a common gate.

The turn-on operation of this GTO is the same as that of the first embodiment. At the time of turn-off, a negative bias is applied to the first gate electrode 8, and at the same time, a positive bias is applied to the second gate electrode 11. At this time, the n-channel MOS transistor is turned on, that is, the surface of the p-type emitter layer under the second gate electrode 11 is inverted, the n-type base layer 2 and the n-type layer 12 are short-circuited, and the anode electrode 9 is connected to this n-type layer. Because of the contact, the n-type base layer 2 is connected to this n-channel MOS.
It is short-circuited to the anode electrode 9 by the transistor. As a result, residual carriers in the base layer at the time of turn-off are effectively discharged to the anode electrode side, reducing switching loss and enabling high frequency operation.

The n-type base layer 2 is short-circuited to the anode electrode 9 by a normal anode short-circuit structure, so that residual carriers in the n-type layer 2 at turn-off are discharged to the anode electrode 9. However, this short circuit is
In order to ensure sufficient hole injection from the n-type emitter layer 11 at turn-on, the holes are normally distributed over an extremely small area. However, this alone is not sufficient for carrier discharge at turn-off. According to this example,
By introducing an n-channel MOS transistor structure, n
The residual carriers in the n-type base layer 2 can be extremely effectively discharged without reducing the hole injection efficiency from the type emitter layer 1.

FIG. 3 is a sectional view showing the GTO of the third embodiment.

This embodiment is a modification of the embodiment shown in FIG. A third gate voltage $415 is provided on the p-type base layer 4 in a region sandwiched between the n-type emitter layers 5 via the gate insulating film 14. The first gate electrode 8 is also connected to the n-type layer 13 . The structure of this portion constitutes an n-channel MOS transistor in which the n-type emitter layer 5 is the source and the n-type layer 13 is the drain.

The turn-on operation of the GTO in this embodiment is the same as that in the first and second embodiments. At this time, the third gate electrode 1
5 is set to zero bias and the channel below it is closed.

At turn-off, a negative bias is applied to the first gate electrode 8, a positive bias is applied to the second gate electrode 11, and at the same time, a positive bias is applied to the third gate electrode 15. When a positive bias is applied to the third gate electrode 15, the n-channel MOS transistor in this part is turned on, and the n-type emitter layer 5 is short-circuited with the first gate electrode 8 via the n-type layer 13, and eventually It is short-circuited to the p-type base layer 4. This further promotes carrier discharge from the n-type base layer 4.

Therefore, according to this embodiment, the switching speed at turn-off is further improved compared to the second embodiment.

Note that for the embodiment shown in FIG.
Channel MOS transistor structures can be introduced and are also useful.

FIG. 4 is a sectional view showing the GTO of the fourth embodiment.

In this embodiment, an n-channel MOS transistor structure is introduced in place of the n-channel MOS transistor introduced on the cathode side in the embodiment of FIG.

That is, with respect to the structure of the embodiment shown in FIG. 2, an n-type layer 16 is selectively provided within the n-type emitter layer 5, and this
A third gate electrode 18 is formed on the n-type emitter layer 5 in the region sandwiched between the 6 and the n-type base layer 4 via the gate insulating film 17.
is provided. Cathode electrode 7 is connected to n-type layer 16.

The operation of the GTO in this embodiment is also basically the same as that in FIG. At turn-off, the third gate electrode 18 has a third
A negative bias is applied, contrary to the illustrated embodiment. As a result, the n-channel MOS transistor in the third gate electrode 18 section is turned on, the n-type base layer 4 and the n-type emitter layer 5 are short-circuited, and residual carriers in the p-type base layer are effectively discharged. .

Therefore, this embodiment also provides the same effects as the previous embodiment. The p-channel MOS transistor structure on the cathode side of the embodiment shown in FIG. 4 can be similarly applied to the structure of the embodiment shown in FIG.

The present invention is not limited to the above embodiments. For example, in all of the above embodiments, the Brehner type was used, but the present invention can also be applied to a mesa type GTO. For example, FIG. 5 is an example of a mesa-shaped structure based on the structure of FIG. 2. Structures other than those shown in FIG. 2 can also have a mesa structure.

FIG. 6 is a sectional view showing the GTO of the sixth embodiment. This has a lower resistance p-type base layer 19 partially buried in the low resistance base layer 4 of the GTO of the fourth embodiment. In the drawing, parts of one p-type base layer that are separated are connected at other parts. Thereby, the p-type paper resistance base layer can be made to have a lower resistance, and the turn-off performance of the first gate electrode 8 can be further improved.

FIG. 7 is a sectional view showing the GTO of the seventh embodiment.

In this embodiment, one p-type high resistance base layer is embedded in the p-type cavity resistance base layer 3.

In this embodiment, the effect at turn-off is similar to that of the sixth embodiment. In addition, current flows more easily when the device is on, and the on-resistance can be lowered.

Of course, the structure on the anode side of the third to seventh embodiments may be the same as that of the first embodiment.

Further, in the above embodiments, the first conductivity type is the p type and the second conductivity type is the n type, but the present invention also includes a GTO in which the conductivity types are completely reversed.

[Effects of the Invention] As described above, according to the present invention, at turn-on, pn
Carrier injection and MOS by forward biasing the junction
) By utilizing carrier injection by turning on a transistor, a GTO with high di/d resistance that will not be destroyed even in the face of a steep current rise can be obtained. Furthermore, switching loss during turn-off is also effectively reduced.

[Brief explanation of drawings]

FIG. 1 is a sectional view showing the GTO of the first embodiment, FIG. 2 is a sectional view showing the GTO of the second embodiment, FIG. 3 is a sectional view showing the GTO of the third embodiment, and FIG. The figure shows G of the fourth embodiment.
5 is a sectional view showing the GTO of the fifth embodiment, FIG. 6 is a sectional view of the GTO of the sixth embodiment, and FIG. 7 is a sectional view of the GTO of the seventh embodiment. FIG. 8 is a sectional view showing a conventional general GTO. 1...p-type emitter layer, 2...n-type base layer, 3...
...p-type high resistance base layer, 4...p type paper resistance base layer, 5...n type emitter layer, 6...insulating film, 7...
- Cathode electrode, 8... First gate electrode, 9... Anode electrode, 10... Gate insulating film, 11... Second
Gate electrode, 12... n-type layer, 13... n-type layer, 1
4... Gate insulating film, 15... Third gate electrode, 1
6...p type layer, 17... gate insulating film, 18...
Third gate electrode, 19... p-type low resistance buried base layer.

Claims (6)

[Claims] (1) It has a structure in which a first conductivity type emitter layer, a second conductivity type base layer, a first conductivity type high resistance base layer, a first conductivity type low resistance base layer, and a second conductivity type emitter layer are laminated in this order. an anode electrode formed on a portion of the first conductivity type emitter layer and the second conductivity type base layer; a cathode electrode formed on the second conductivity type emitter layer; and a first conductivity type base layer formed on the first conductivity type base layer. In a gate turn-off thyristor having a gate electrode, a part of the first conductivity type high-resistance base layer has a part exposed on the anode side surface, and the second conductivity type base is sandwiched between this part and the first conductivity type emitter layer. A gate turn-off thyristor characterized in that a second gate electrode of a MOS structure is provided on a layer surface. (2) It has a structure in which a first conductivity type emitter layer, a second conductivity type base layer, a first conductivity type high resistance base layer, a first conductivity type low resistance base layer, and a second conductivity type emitter layer are laminated in this order. an anode electrode formed on a portion of the first conductivity type emitter layer and the second conductivity type base layer; a cathode electrode formed on the second conductivity type emitter layer; and a first conductivity type base layer formed on the first conductivity type base layer. In a gate turn-off thyristor having a gate electrode, a part of the first conductivity type high-resistance base layer has a portion exposed on the anode side surface, and a second conductivity type emitter layer is selectively contacted with the anode electrode. A conductivity type layer is formed, and a second gate of the MOS structure is formed across the surfaces of the first conductivity type emitter layer and the second conductivity type base layer sandwiched between the second conductivity type layer and the first conductivity type high resistance base layer. A gate turn-off thyristor characterized by being provided with an electrode. (3) A second conductivity type layer to which the first gate electrode is connected is formed adjacent to the second conductivity type emitter layer on the surface of the first conductivity type low resistance base layer, and the second conductivity type layer and the second conductivity type M on the surface of the first conductivity type low resistance base layer sandwiched between type emitter layers.
3. The gate turn-off thyristor according to claim 1, further comprising a third gate electrode having an OS structure. (4) A first conductivity type layer is formed in the second conductivity type emitter layer to which the cathode electrode selectively contacts, and a first conductivity type layer is formed in the region sandwiched between the first conductivity type layer and the first conductivity type low resistance base layer. 3. The gate turn-off thyristor according to claim 1, wherein a third gate electrode of a MOS structure is provided on the surface of the dual conductivity type emitter layer. (5) The first conductivity type low-resistance base layer further includes a first conductivity type low resistance base layer.
3. The gate turn-off thyristor according to claim 1, wherein a base layer of a conductivity type and having a lower resistance is embedded. (6) The gate turn-off thyristor according to claim 1, wherein the first conductivity type low resistance base layer is not stacked on the first conductivity type high resistance base layer but is partially buried therein.