JPH0368393B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a matrix display device using a pulse train generating circuit and a pulse width changing signal generating circuit.

The brightness of a cathode ray tube (CRT) is 2.5 to 2.5 of the applied voltage.
Although it is proportional to the third power, the brightness of a liquid crystal display is proportional to the effective value of the applied voltage, and the brightness of a plasma display is proportional to the average value of the applied voltage.

On the other hand, human vision is said to be proportional to the 1/3 power or logarithm of luminance. Therefore, when displaying images using a cathode ray tube for television, the voltage applied to the cathode ray tube is applied as is without any correction to the video signal, but the brightness characteristics of the cathode ray tube and visual perception almost cancel each other out, resulting in a difference between the video signal level and visual perception. A good image with a nearly linear relationship can be obtained. On the other hand, in a matrix display panel such as a liquid crystal display or a plasma display panel, linearity cannot be obtained between the video signal level and the visual perception, resulting in an unnatural image in which the white portion is compressed.

Therefore, in order to visually make the luminance gradation of the matrix display panel linear, it is proposed, for example, to specify the pulse width of each luminance modulation panel at unequal intervals, as disclosed in Japanese Patent Laid-Open No. 148918/1983. It has been proposed. In this case, a monostable multivibrator is used to define the pulse width of each brightness modulation pulse at unequal intervals.

Therefore, the circuit configuration is complicated, and
Since it has a time constant circuit for setting the pulse width, it is difficult to make it into a monolithic IC (semiconductor integrated circuit).

Further, it has the disadvantage that the pulse width varies widely and high-quality images cannot be obtained.

Furthermore, for displays with different brightness gradations (liquid crystal, plasma, electroluminescence, etc.), there are many circuit changes, and there is a drawback that mass production is not possible.

SUMMARY OF THE INVENTION An object of the present invention is to provide a matrix display device using a pulse train generation circuit and a pulse width change signal generation circuit, which have a simplified circuit and small variations.

Another object of the present invention is to provide a matrix display device using a pulse train generating circuit and a pulse width changing signal generating circuit with improved versatility.

According to the basic feature of the present invention, by selecting a plurality of arbitrary M-th clock pulses based on the count output signal of each stage of an N-ary counter that counts clock pulses, an irregularly spaced pulse train and an irregularly spaced pulse train are generated. A brightness modulation pulse is formed such that the pulse width signal and the brightness gradation of the matrix display panel are linear.

Hereinafter, this invention will be explained in detail together with examples.

FIG. 1 is a block diagram showing an embodiment in which the present invention is applied to a matrix display device.

The video signal V is linearly amplified by the video amplifier AMP. This amplified video signal A is converted by an A/D converter ADC into a digital video signal DV that is quantized at predetermined level intervals. This digital video signal DV is input to the line memory MEM and is stored as a digital value corresponding to a pixel in one horizontal scanning period.

On the other hand, the video signal V is also input to the synchronization separation circuit SSP, where the synchronization signal SY is extracted.

The scan circuit SC receives the synchronization signal SY and generates a scan electrode drive pulse X to be applied to the scan electrodes of the matrix display panel MXD. This drive pulse X always selects one scanning electrode, and repeatedly switches the selected state sequentially from top to bottom in synchronization with the synchronization signal SY. As will be explained in detail later, the brightness modulation pulse generator PG generates a plurality of brightness modulation pulses BM with different pulse widths (number of gradations) in synchronization with the synchronization signal SY.
occurs. These brightness modulation pulses BM define the brightness B of each pixel of the matrix display panel MXD.

The selection switch MPX is a switch circuit called a multiplexer or selector, and selects one of the luminance signals of one scanning period (parallel video signal PV of the scanning line corresponding to the drive pulse X) stored in the line memory MEM. As a selection signal, one brightness modulation pulse from the brightness modulation pulses BM corresponding to the digital value is selected and applied to the corresponding column electrode (signal electrode) of the matrix display panel MXD. The output signal of the selection switch MPX is called a signal electrode drive pulse Y, and defines the brightness B of the pixel in the matrix display panel MXD.

The parallel video signal PV is updated every scanning line,
In synchronization with this, the selection states of the scanning electrode drive pulses X are also sequentially switched, so that a two-dimensional image is displayed on the matrix display panel MXD.

FIGS. 2 1-5 show input/output characteristic diagrams of each of the above blocks.

As shown in FIG. 2, the video amplifier AMP has linear characteristics, and the input signal V and output signal A are proportional. Figure 2 shows the characteristics of the A/D converter ADC.Since the output signal DV is a digital value, the input/output characteristics become step-like due to quantization errors. The input/output characteristics are approximately linear. In Fig. 2, a luminance modulation pulse generator is shown.
The properties of PG are shown. For the number of gradations 1 to N, the pulse width is set to be nonlinear (unequal intervals) such that luminance proportional to the third power can be obtained.

On the other hand, FIG. 2 shows the relationship between brightness B and human vision I, which is I∝B ^1/3 .

Therefore, as shown in the comprehensive characteristic diagram of FIG. Natural images can be obtained.

FIG. 3 shows a circuit diagram of an embodiment of a pulse train generation circuit used in the luminance modulation pulse generator PG.

T-type flip-flop circuit FF ₁ ~ _{FF 7} and AND
The circuits G ₇ to G ₁₂ constitute a synchronous counter circuit. A clock pulse CP is applied to the T terminal of the first stage flip-flop circuit _FF1 . The output signal Q of this flip-flop circuit _FF1 and the clock pulse
The output signal of the AND circuit _G7 to which CP is applied to the input is transmitted to the input terminal T of the second stage flip-flop circuit _FF2 . Regarding the flip-flop circuits FF ₃ to FF ₇ in the third and subsequent stages, focusing on the third stage flip-flop circuit FF ₃ , the output signal Q of the flip-flop circuit FF ₂ in the previous stage and the output of the AND circuit G ₇ in the previous stage Signals and clock pulses
The output signal of the AND circuit _G8 having CP applied to its input is transmitted to the input terminal T.

In this synchronous counter, unlike the case where T-type flip-flop circuits are connected in series, the counting (frequency division) output signals of each stage are not sequentially delayed.

That is, since the trigger is an AND signal of the inverted output signal of the flip-flop circuit in the previous stage and the output signal and clock pulse of the gate circuit in the previous stage, the trigger signal for each stage is only the delay time of the AND circuit. The delay time for the clock pulse CP as described above is compensated.

In this example, although not particularly limited, T
The type flip-flop circuits FF ₁ to FF ₇ are of the negative edge trigger type.

Each of the output signals Q, from the flip-flop circuits FF ₁ to _{FF 7} in each stage is applied to word lines W ₁ to _{W 14} constituting the MUX ROM, respectively.

Bit lines B ₁ to _{B 14} are configured to be approximately orthogonal to word lines W ₁ to W ₁₄ , and a memory MOSFET (insulated gate field effect transistor), for example, is formed at the intersection marked with an O. When a well-known mask ROM or a synchronous counter circuit is configured using I ² L, wired-AND logic can be used, so a mask ROM is configured in which bit lines and word lines are simply connected. The eyes of the above ROM are
Shown as AND logic.

This ROM forms irregularly spaced pulses, and for example, the bit line _B1 is determined by the following logical formula.

B ₁ =Q ₁ , ₂ , ₃ , ₄ , ₅ , ₆ ...(1) In other words, the second clock pulse CP is obtained from the bit line B ₁ and the fourth clock pulse is obtained from the bit line B ₂ . is obtained.

This can be easily understood from the operational waveform diagram in FIG.

That is, the relationship between the clock pulse CP and the output signals Q ₁ to Q ₆ of the flip-flop circuits FF ₁ to _{FF 6} of each stage is well known, and therefore a description thereof will be omitted. Furthermore, output signals ₁ and ₆ are omitted. Furthermore, in Fig. 3, the outputs Q of FF ₁ to FF ₉ are written as if they were all drawn out one by one (W ₁ to _{W 14} ), but in reality, FF ₁ to _{FF 9} are In the case of the IIL configuration, W ₁ to W ₁₄ are all formed with a number corresponding to the number of bit lines B ₁ to B ₁₄ , and they are
They are connected to mutually separated open collectors in FF ₁ to FF ₇ , and at most only one bit line is connected to one word line.

Therefore, by configuring the ROM as described above, 14 bit line output signals B ₁ to B ₁₄ as shown in the figure can be obtained.

And these bit line output signals B ₁ to B ₁₄ are
By passing through the NOR circuits _G1 to _G5 and the NAND circuit _G6 , the pulse train is applied as a series of pulses to the input terminal D of the D-type flip-flop circuit _FF8 .

A clock pulse CP is applied to the clock input terminal C of the D-type flip-flop circuit _FF8 . And the D-type flip-flop circuit _FF8 is
It is said to be a body-dave-edge trigger type. Therefore, the output Q of the flip-flop circuit _FF8 is a pulse train _Q8 delayed by a half period of the clock pulse CP with respect to the pulse train applied to the input terminal D, as shown in FIG.

This is done because it is possible to prevent variations in the mutual delay times of the bit line output signals B ₁ to B ₁₄ in the ROM.

Thereby, it is possible to form a pulse train signal with irregular intervals defined with high precision. Furthermore, the interval between pulse trains can be set arbitrarily by changing the ROM. In this embodiment, settings are made so that the brightness for the number of gradations as described above for the liquid crystal can be obtained.

Using this pulse train signal and the first clock pulse (or reset release signal) R, a pulse width changing signal generation circuit can be easily achieved.

That is, as shown in FIG. 4, for example, 14 flip-flop circuits (not shown) are simultaneously set at the positive edge of the first clock pulse CP, and the negative edge of the pulse train signal _Q8 is set at the same time.
By resetting the edges one after another, pulse width changing signals BM ₁ to BM ₁₄ are formed and used as the brightness modulation pulses.

In the brightness modulation pulse generation circuit configured as described above, the brightness modulation pulses having a pulse width corresponding to the number of gradations can be formed by processing the pulse signal, so that each pulse width can be set with high accuracy. Especially when using a synchronous counter circuit or when using a D-type flip-flop circuit together with it,
Since variations in delay time in pulse signal processing are minimized, pulse width setting can be performed with extremely high precision.

Furthermore, monolithic ICs can be applied to other display means such as liquid crystal displays or plasma displays with different characteristics by simply changing the ROM.
Coupled with the ease of production, it is possible to improve mass productivity.

The present invention is not limited to the above-mentioned embodiments, but can be applied to, for example, when configuring a pulse width change signal generation circuit.
The bit line outputs _B1 to _B14 of the ROM may be directly used as reset signals for the flip-flop circuit. However, in this case, the number of wires increases, so as mentioned above, after converting the pulse train signal once, the _second
It is desirable that the flip-flop circuits in subsequent stages are reset one after another by the AND of the pulse train signal and the reset output signal of the flip-flop circuit in the previous stage.

Furthermore, the ROM may be of any format, and the gate circuit that converts it into a pulse train can also be replaced with a ROM. Furthermore, a logic gate circuit other than the ROM may be used as a circuit for extracting pulses at irregular intervals.

In addition, when using a liquid crystal in a matrix display device, an AC drive method to prevent a DC component from occurring in the drive signal is known, for example, in Japanese Patent Laid-Open No. 53
It may be anything, such as those described in Publication No. 148918.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 1 to 5 are input/output characteristic diagrams of each block in FIG. 1, and FIG. 3 is a circuit diagram showing an embodiment of the invention. FIG. 4 is a diagram of its operating waveforms.

Claims (1)

[Scope of Claims] 1. A matrix display panel having a scanning electrode and a signal electrode and having a non-linear characteristic between a drive signal and visual luminance, and a matrix display panel having a scanning electrode in synchronization with a video signal. a scanning circuit for selective driving; a pulse width change signal generation circuit for forming a plurality of pulse width modulation signals for defining the gradations of the luminance signal applied to the signal electrodes of the matrix display panel at unequal intervals; and a video signal. a selection circuit that selects one of the pulse width modulation signals and applies it to the signal electrode of the matrix display panel according to the level of the pulse width modulation signal; and an N-adic counter that counts the number of gradations, and receives the output signal of each stage of the N-adic counter, and generates pulses at irregular intervals according to the number of gradations so that the brightness gradation of the matrix display panel visually becomes linear. It has a decoder circuit that selects and outputs the clock pulse, and a plurality of flip-flop circuits corresponding to the number of gradations. A matrix display device characterized in that the pulse width modulation signal is obtained from the flip-flop circuit of each stage by resetting each stage. 2. The matrix display device according to claim 1, wherein the N-ary counter is a synchronous counter. 3. The matrix display device according to claim 1 or 2, wherein the decoder circuit is constituted by a ROM.