JPH036765A - Duplexed connection system for cpu bus - Google Patents

Abstract

PURPOSE:To attain the common use between an inter-CPU communication circuit of a duplexed device and a bus extension circuit of its own system by using a higher rank address to discriminate the connection of its own system from the connection of another system. CONSTITUTION:An address comparator 20 discriminates an access of its own from that of its counter system based on a received address signal. A bus preference control circuit 30 performs the preference control between a bus request signal of its own and that of another system. Then an unused higher rank address is used when an access is given to an another system. Thus the comparator 20 discriminates the access of its own system from that of another system based on an address signal. At the same time, the circuit 30 carries out the bus preference control. Thus the same type of bus extension adaptors and CPU communication adaptors can be used. As a result, the cost of a device is reduced and at the same time the maintenance operation is facilitated.

Description

[Detailed description of the invention] [Summary] A microprocessor is used, and the device configuration consists of a 1-system device and a 2-system device.
Regarding the bus connection method of duplexed equipment consisting of system equipment, the purpose is to make the communication circuit between the CPUs of the redundant equipment and the bus extension circuit within the own system common, and an address that specifies the communication partner is used. An address comparator that distinguishes between own-system access and other-system access, and a bus priority control circuit that prioritizes own-system bus request signals and bus request signals from other systems are provided. It is set as an address to identify access, and when the bus is connected, the address comparator distinguishes between access to the own system and access to other system based on the received address, and the bus priority control circuit performs priority control in case of bus contention. Configure.

[Industrial application field]

The present invention uses a microprocessor and has one device configuration.
This invention relates to a bus connection method for duplex devices consisting of a system device and a dual system device.

In particular, supervisory control equipment that is required to have high reliability has a duplex configuration, each of which is equipped with a microprocessor, and the duplex units communicate with each other between CPUs to monitor each other's status and distribute the load. It is carried out.

An interface circuit for such inter-CPU communication is an inter-CPU communication adapter (hereinafter referred to as CCA).
A bus expansion adapter (hereinafter referred to as BBF) is used for connections within the device.

It is required that a single type of adapter can handle a plurality of types of adapters in order to simplify the device, reduce costs, and facilitate maintenance.

(Prior Art) FIG. 4 is a diagram for explaining the configuration of a conventional device, and FIG. 5 is a diagram for explaining the connection of a BBF in the conventional example.

The conventional example shown in FIG.
This is an example configured of expansion shelves 5A and 6A.

The 1-series basic shelf 3A has CPU (1), CCA
(1), BBFI (1), and the expansion shelf 5A includes BBF2 (1) and various line adapters AD.
It houses P. The 2nd system has the same configuration as the 1st system, and the basic shelf 4A is CPtJ (2), CCA (2),
Consisting of BBFI (2), the expansion shelf 6A is
BF2 (Accommodates 2L and various line adapters ADP.

FIG. 5 is a diagram explaining the connection between BBFI (1,) and BBF2 (1), and shows the connection between the lotus driver and the receiver 11.12.
．． 13.14, BBF consisting of timing control circuit 15
I (1), bus driver, receiver 21.22.
BBF consisting of 23, 24 and timing control circuit 25
I (2) is connected to the bus.

In the above configuration, information is exchanged within the own system using BBF2 (1), BBFI (
This is done by collecting the data in the CPU (1) via the CPU (1).

Information is exchanged with other systems through the own system's CCA (1) and the other system's CCA (2).
(2) is connected and communication between CPUs is performed.

(Problem to be solved by the invention) In the configuration shown in Figure 4 above, BBF is used for connections within the own system.
I, BBF2, and CCAl were used to connect with other systems, and different types of interface circuits were used for each connection partner.

Therefore, the device configuration becomes complicated, and when a failure occurs, it becomes complicated to troubleshoot and resolve the problem, which is also one of the causes of increasing the cost of the device.

The present invention provides a circuit for communication between CPUs of a duplex device,
The purpose is to share the bus extension circuit within the own system.

[Means to solve the problem] FIG. 1 shows a block diagram illustrating the invention in detail.

Reference numeral 20 shown in FIG. 1 is an address comparator that identifies self-system access and remote-system access from the received address signal, and 30 is a bus priority control that prioritizes the own-system bus request signal and the bus request signal from other systems. circuit, 11.12.1
3.14 is a bus driver receiver that sends and receives signals on the bus, and providing such means is a means for solving this problem.

[Function] In the present invention, an upper address that has not been used so far is used as an address when accessing other systems, and the address comparator 20 uses the address signal to
By using a bus priority control circuit 30 that identifies own system access and other system access and performs bus priority control, B
It becomes possible to realize BF1, BBF2 and CCA in the same circuit.

〔Example〕

The gist of the present invention will be specifically explained below with reference to embodiments shown in FIGS. 2 and 3.

FIG. 2 is a diagram for explaining the present invention in detail, and FIG. 3 is a diagram for explaining the configuration of an apparatus in an embodiment of the present invention.

Note that the same reference numerals indicate the same objects throughout the figures.

By using the BBF shown in FIG. 2, the device configuration in the embodiment of the present invention shown in FIG.
FIG. 3 is a diagram illustrating that both are realized by the same circuit.

Figure 2 shows the connection between the BBFs, and the address that specifies the other party to connect to is the address comparator 20 (
1) will be sent. Address comparator 20 (1
) decodes this address, determines whether it is connected to its own system or to another system, and controls the specified bus control line.

Next, when a bus request signal for connecting the bus is sent to the bus priority control circuit 30 (1), the bus priority control circuit 30 (1) determines whether or not it can be used based on the priority of the address to be connected. Timing control circuit 40 (1) controls timing and performs communication via address/data bus.

11 to 14 are bus driver receivers that transmit and receive signals on the bus.

By configuring as described above, CCA, BBFI,
It becomes possible to make the BBF2 have the same configuration.

〔Effect of the invention〕

According to the present invention as described above, by using the upper address as an address for distinguishing between the own system connection and the other system connection, the bus expansion adapter and CPU communication adapter that connect the basic shelf and the expansion shelf can be connected to the same system. This makes it possible to use different types of adapters, reduce the cost of the device, and facilitate maintenance work.

are shown respectively.

[Brief explanation of the drawing]

FIG. 1 is a block diagram explaining the present invention in detail, FIG. 2 is a diagram explaining the present invention in detail, FIG. 3 is a diagram explaining the configuration of an embodiment of the present invention, and FIG. 4 is a conventional diagram. FIG. 5 is a diagram illustrating the configuration of an example device, and FIG. 5 is a diagram illustrating the connection of a conventional BBF. In the figure, 11 to 14. 21 to 24 are bus driver receivers, 20
．． 20 (1), 20 (2) are address comparators, 30.30 (1), 30 (2) are bus priority control circuits, 40 (1), 40 (2) are timing control circuits, ζ
Figure 3 is a diagram explaining the equipment configuration in an embodiment of the present invention.

Claims (1)

[Scope of Claims] In a duplex device using a microprocessor (10) and having a device configuration of a 1-system device (1) and a 2-system device (2), the self-system access is performed from an address specifying a communication partner. and a bus priority control circuit (30) that performs priority control between own system bus request signals and bus request signals from other systems, and distinguishes upper addresses from own system accesses. The address is set as an address for identifying access to other systems, and when the bus is connected, the address comparator (20) identifies access to the own system and access to other systems based on the address received, and the bus priority control circuit (30)
A CPU bus redundant connection system characterized by performing priority control in the event of bus contention.