JPH0367341B2 - - Google Patents

Description

[Detailed Description of the Invention] [Field of Application of the Invention] The present invention relates to a wiring method for a semiconductor integrated circuit,
In particular, the present invention relates to a semiconductor integrated circuit wiring system suitable for reducing the power supply wiring area in a semiconductor integrated circuit.

[Background of the invention]

A conventional wiring system for a semiconductor integrated circuit will be explained with reference to FIGS. 3 to 5, using an example of logic in which four types of timing signals are distributed using four inverter cells for each type.

In FIG. 3, 1 is a logic cell that outputs an inverted signal of an input signal 11 as an output signal 12. In FIG.
When the output signal 12 rises, a current iH flows from the power supply line 13 at a high potential level. Also output signal 1
2 falls, a current iL flows to the power supply line 14 at a low potential level.

In FIG. 4, 2 is a block in which four logic cells 1 are integrated. The input signal 21 is commonly input to the four logic cells 1. Therefore,
The output signals 22 of the logic cell 1 all have the same waveform, and the current iB flowing through the power supply line 23 at this time is 1
This is four times the current flowing through each logic cell. In addition,
In FIG. 4, the power supply line on the low potential side is omitted.

FIG. 5 shows an integrated circuit 3 in which four blocks 2 are arranged on a chip.

An input signal 31 is input to each block 2, and a power supply line 33 is connected to each of the two blocks 2. The power supply line 33 is connected to a power supply terminal 34 of the chip. Now, there are signals on the input signal line 31 that change at different times.
When IN1, IN2, and IN4 are input, currents ic1 and ic2 flowing through the power supply line 33, which are four times the current flowing when one logic cell 1 flows, flow twice. Note that the power supply line on the low potential side is omitted.

Such logic cells are used for timing signal distribution. The timing signal is indispensable for sequential circuits and is used for many memory cells such as flip-flops within a chip. Therefore, a high driving capacity cell is used as the logic cell for timing distribution. For this reason, the current flowing through one timing distribution cell is several to several tens of times higher than that of other general logic cells, and it is necessary to ensure a power line width that can withstand this current. . As a result, the area occupied by the feeder lines in the limited chip area becomes large, making wiring of normal signal lines difficult, and ultimately leading to the need to increase the chip size. .

[Purpose of the invention]

SUMMARY OF THE INVENTION An object of the present invention is to provide a wiring system for a semiconductor integrated circuit that can minimize the area of wiring required for power supply and minimize the chip size.

[Summary of the invention]

The wiring method of the semiconductor integrated circuit of the present invention is based on the characteristics of semiconductor devices, such as CMOS, in which current flows only at the moment when the output signal of the cell changes, and in logic circuits that operate in synchronization with multiple timings, outputs are output at the same time. Focusing on the fact that the number of cells whose signal changes is inversely proportional to the number of timing phases, it is possible to minimize the feed line width by limiting the number of cells connected to the same feed line that change at the same time. This is what I did.

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to FIGS. 1 and 2.

FIG. 2 shows a block 4 in which four high driving capacity cells (hereinafter referred to as cells) 41 for timing distribution are mounted.

A signal line 42 is input to each of the four cells 41, and the output of the cell 41 is distributed via a signal line 43 as an input to a flip-flop (not shown) or the like. Power is supplied to the cell 41 through a power supply line 44
It is done more. Note that the power supply line on the low potential side is omitted.

Now, signals IN1 and IN1 are connected to the input signal line 42, respectively.
If IN2, IN3, and IN4 are input with different phases, OUT1 and IN4 are input to the output signal line 43, respectively.
OUT2, OUT3, and OUT4 signals are output.
At this time, the current flowing through the power supply lines 441 to 444 is
iB1 to iB4, so feeder line 4
4, as shown in iB, only the amount of current flows through one cell 41 at a certain time.

FIG. 1 shows an integrated circuit 5 in which four blocks 4 are arranged. Four input signal lines 51 are input to each block 4, and power is supplied to the two blocks 4 through the same power supply line 52. The power supply line 52 is connected to a power supply terminal 53 of the chip. The input signal is the second
As shown in the figure, IN1, IN2, IN3,
It is IN4. Therefore, if we focus on one block 4, there is only one cell in the block whose output waveform is changing, that is, a cell through which current is flowing, and the power supply lines 521 to 524 have a cell corresponding to one cell 41. Only current flows. Therefore, the feeder line 52
As shown in ic1 and ic2, only two currents flow through the cell 41 at a certain time.

Comparing the above configuration with the conventional example, the amount of current flowing in the power feed line 44 in block 4 and the power feed lines 521 to 524 to each block 4 is 4/1, and the width of the feed line is also 4/1. Similarly, the wire 52 is 2/1
It would be good to have a feed line width of .

As described above, in the embodiments shown in FIGS. 1 and 2, the number of cells that can be switched at the same time in each block is limited to one, so the width of the power supply line within the block can withstand the current flowing through one cell. All you need to do is ensure the width of the power supply line, and the width of the power supply line connected to the power supply terminal of the chip is also
The width of the feeder line is sufficient to withstand the current of two cells, and the proportion of the area occupied by the feeder line required for power feeding can be significantly reduced compared to the conventional method.

In this embodiment, the logic is to distribute four types of signals using four cells per type, but the optimum number of blocks can be determined depending on the number of signal types and the number of cells required for signal distribution. Needless to say, all you need to do is set it up. Further, although the number of power supply terminals is limited to two, it is clear that if the chip has a larger number of terminals, the power supply terminals can be used for each block and the width of the power supply line can be further reduced.

Other embodiments of the present invention are shown in FIGS. 6 and 7. FIG. 6 shows one block 5 in which eight cells 51 are mounted. In the block 5, 2
Two signals IN1 and IN2 are provided and are commonly input to each of the four cells. Power is supplied to each cell 51 through a power supply line 52 . Signal IN1,
By inputting IN2 with a phase shift, output signals OUT1 and OUT are made into a set of four, respectively.
2 is obtained by smoothing the phase. FIG. 7 shows an integrated circuit 6 in which eight blocks 5 of FIG. 6 are arranged. Each block 5 receives two input signals INi, INj (i=1, 3, 5, 7, j=2, 4,
6, 8) are commonly given. That is, in this embodiment, there are eight cells 51 in one block 5.
Even if it is implemented, the power supply line width in the block is
The width of the feeder line may be sufficient to withstand the current flowing individually.

〔Effect of the invention〕

As described above, according to the present invention, the amount of current flowing through the power supply line is equalized with respect to the time axis, so that wiring with a small width of the power supply line is possible. Therefore, the power supply wiring area occupying the chip area can be reduced. Therefore, even higher density integrated circuits can be provided.

[Brief explanation of drawings]

FIG. 1 is a block layout diagram and its waveform diagram in a chip according to an embodiment of the present invention, FIG. 2 is a block diagram and its waveform diagram in FIG. 1, and FIG. 3 is a diagram of the basic logic cell in the prior art. A block diagram and its waveform diagram; FIG. 4 is an intra-block diagram and waveform diagram in the prior art; FIG. 5 is an in-chip block layout diagram and its waveform diagram in the prior art; FIG. 6 is another embodiment of the present invention. The block diagram of
FIG. 7 is a block layout diagram within a chip using the blocks shown in FIG. 6. 1... Cell, 11... Input signal line, 12... Output signal, 13... Power feed line, 14... Power feed line, 2...
... block, 21 ... input signal line, 22 ... output signal line, 23 ... power supply line, 3 ... chip (integrated circuit), 31 ... power supply terminal, 34 ... power supply terminal, 4
... Block, 41 ... Cell, 42 ... Input signal line, 43 ... Output signal, 44 ... Power supply line, 5 ...
Chip (integrated circuit), 51... Input signal line, 52
...Power supply line, 53...Power supply terminal.

Claims (1)

[Claims] 1. In an integrated circuit that includes a plurality of blocks that are aggregates of a plurality of logic cells, the integrated circuit has a plurality of power supply terminals, a first power supply line connected to the power supply terminal, and the first power supply line. a second power supply line that supplies power to the block from the second power supply line; a third intra-block power supply line that connects to the second power supply line; and a fourth power supply line that supplies power from the third power supply line to the logic cells within the block. Multiple logic cells operating at the same time are divided into multiple blocks and multiple blocks including logic cells operating at the same time are connected to different power supply terminals. A wiring method for semiconductor integrated circuits characterized by a block arrangement for power supply.