JPH0367335A - Digital fuzzy circuit - Google Patents

Abstract

PURPOSE:To improve the practical properties of a digital fuzzy circuit by providing a chip switch controller to perform a total arithmetic operation or the independent arithmetic operations between a rule arithmetic-only circuit and a centroid arithmetic-only circuit. CONSTITUTION:A latch 1 latches the input data and switches an input switch circuit 2 to input the input or latch data. A rule arithmetic circuit 4 outputs the member functions which are given with switching actions of a membership function switch circuit 3 and the inference result received via the input of the circuit 2. The inference result is outputted to a prescribed address and an address selection circuit 5 computes the maximum value. Furthermore an input switch circuit 6 inputs the arithmetic result or the input data of the circuit 5 to a centroid arithmetic circuit 7 to compute the centroid value. Then an output switch circuit 8 outputs with switching the centroid value or the inference result of the circuit 4. Under such conditions, a chip switch controller 9 controls the circuits 4, 6 and 8 and can set a mode where the circuits 4, 5 and 7 are all actuated and another mode where these circuits are actuated independently of each other. Thus the practical properties are improved for a digital fuzzy circuit.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a digital fuzzy circuit that performs fuzzy inference, and particularly to a digital fuzzy circuit suitable for integration into an IC (integrated circuit).

[Prior Art] As is well known, fuzzy theory was proposed by Professor L.A. Zadeh of the University of California in 1965, and in 1974 by Mamdani (E.
1. Professor Mamdani demonstrated the possibility of practical use, and various implementation means have been proposed since then.

Typical examples include the following.

For example, Japanese Unexamined Patent Publication No. 192407/1983 describes a train operation control technique that reduces the number of notch fluctuations by software inference. Also, JP-A-61-2
No. 0428 describes an analog fuzzy circuit realized by a current circuit.

Furthermore, recently, fuzzy chips equipped with fuzzy circuits have been announced one after another, as seen in the October 3, 1988 issue of Nikkei Electronics (No. 457). The main types of these are: (1) one chip that outputs the center of gravity after inference from input, and (2) the one in which an inference circuit is constructed by combining two types: a rule calculation chip and a center of gravity calculation chip.

[Problems to be Solved by the Invention] However, since the latter method is configured to perform inference using a clock synchronization method, there is a drawback that the inference speed is limited by the frequency of the clock.

In addition, the above-mentioned method (2) had the drawback that the mass production effect was impaired and the unit cost of the chip was increased because two types of chips for calculating the rules and the chip for calculating the center of gravity were prepared separately.

In order to eliminate these drawbacks, we simplified the fuzzy center of gravity calculation circuit and configured it to switch membership functions in a time-sharing manner, thereby reducing the circuit scale and combining the rule calculation chip and the center of gravity calculation chip. A digital fuzzy circuit that can be integrated into one chip has been considered by the present inventors.

An overview of this digital fuzzy circuit will be explained with reference to FIGS. 15 and 16. Figure 15 shows fuzzy rule 1 that allows membership functions to be set using parameters.
This is an example of application to a time-division digital fuzzy circuit in which multiple fuzzy rules are inferred by switching parameters in clock synchronization.

In FIG. 15, 51 and 52 are antecedent membership function definition circuits, 53 is a minimum value calculation circuit, 54 is an area calculation circuit, 55 is an address selection MAX section, 56 is a center of gravity calculation section,
57 is a shift operation unit, 58 is a latch group that distributes the input variables of two systems to the antecedent membership function definition circuits 51 and 52, 5 is a sequence controller that generates timing signals for time division control, etc., and 60 is each rule. A memory group 61 stores the definition harameter of the antecedent membership function and the consequent membership function for each.
This is an address decoder that specifies the address of .

FIG. 16 shows an example of the address selection MAX section 55 of the time division type digital fuzzy circuit shown in FIG. 15. However, here, the inferences of the fuzzy rules that are inferred one after another in clock synchronization are provided in the order of the output addresses of each consequent membership function (for example, in the order of O to 6).

The cycle pulse is a pulse output from five sequence controllers each time one fuzzy inference ends. That is, when performing six fuzzy inferences, for example, one pulse is output for six clocks. This cycle pulse causes the address latch unit 72 and shift calculation unit (maximum value calculation unit) 75o, 75+, '7
Each output of 52 is reset and ready for the next inference operation.

The zero determination unit 71 is a circuit that outputs an output when the input area is not “0”, and the address latch unit 72 is a circuit that holds the address when the area first becomes not “0” until a cycle pulse is input. It is.

Here, the output of the first address whose area is no longer ``O'' is selected as S, and up to three addresses counting from the first address whose area is no longer ``○'' are S. -82
(Since the fuzzy rules are arranged in the order of the output addresses, the first address whose area is no longer 0 becomes the minimum address with an output area.)

In this way, since the areas other than the above three addresses are "0", there is no effect no matter where in So''''Sz they are allocated.

In this digital fuzzy circuit, input data A and B are latched by a latch group 58, and a circuit for one fuzzy rule that can set membership functions with parameters is used to switch parameters in synchronization with the clock, resulting in multiple Perform fuzzy rule inference. The address selection MAX circuit 55 finds an address for which the inference result is not zero, and performs maximum value calculation on three addresses including that address. The center of gravity calculation circuit 56 calculates the center of gravity for the output address, and the shift calculation circuit 57 corrects the position of the entire center of gravity and outputs it from the chip as a center of gravity value.

Now, when considering incorporating a chip equipped with a digital fuzzy circuit configured as described above into a product, if the product is a mass-produced product, it may be configured as a dedicated chip, but if it is not a mass-produced product, The dedicated chip would be expensive and impractical. Considering these points, when making a fuzzy circuit into a chip, it is desirable that the chip be configured as a general-purpose chip that can also have other functions, rather than as a dedicated chip.

This invention was made in view of these circumstances,
Despite its simple configuration, it can be used as a complete fuzzy inference circuit, a circuit dedicated to rule calculation, or a circuit dedicated to center of gravity calculation, and when configured as an IC chip, the number of bins can be reduced. [Means for Solving the Problems] The digital fuzzy circuit of the present invention has a latch means for latching input data, data latched by the latch means, or the input data. A first input switching circuit that switches which data is input; an inference result is obtained from the data that is switched and input by the first input switching circuit, and the membership function that is switched and given by the membership function switching circuit. A rule calculation circuit to output, a maximum value calculation that outputs the inference results output by this rule calculation circuit to a predetermined address and calculates the maximum value of the inference results for each address, and the calculation result of this maximum value calculation unit or the input. a second input switching circuit that switches which of the data is input; a center of gravity calculation circuit that calculates the center of gravity based on the data that is switched and input by the second input switching circuit; a center of gravity value calculated by the center of gravity calculation circuit; an output switching circuit that switches which of the inference results output by the rule computing circuit to output; and controlling switching of the first and second input switching circuits and the output switching circuit; A first mode in which all of the maximum value calculation unit and the center of gravity calculation circuit are operated, a second mode in which only the rule calculation circuit is operated, or a third mode in which only the center of gravity calculation circuit is operated. It is composed of a control circuit for operation.

[Operation] This invention provides switching circuits at key points of each block constituting the fuzzy inference circuit, and uses control signals from the control circuit to switch between the first mode as a completed fuzzy inference circuit and the first mode as a rule calculation circuit. The circuit configuration is such that it can operate in both the second mode and the third mode as a center-of-gravity calculation circuit, so when integrated into an IC, it can be used as a general-purpose chip rather than a dedicated chip. Since the terminals are shared, it is possible to configure a digital fuzzy circuit with a small number of input/output bins.

[Examples] Examples of the present invention will be described below with reference to the drawings.

FIG. 1 shows a basic block diagram of a digital fuzzy circuit according to the present invention. That is, 1 is a latch that temporarily stores input data, and the output of this latch 1 is supplied to an input switching circuit 2. The input switching circuit 2 controls whether to pass the output of the latch 1 or input data from the outside in response to a control signal from the chip switching controller 9. The output of this input switching circuit 2 is supplied to a rule calculation circuit 4. The rule calculation circuit 4 operates clock asynchronously,
A rule calculation result (inference result) is output based on the membership function supplied from the membership function switching circuit 3 which switches the membership function in synchronization with the clock and the input data from the input switching circuit 2. This inference result is supplied to the address selection circuit 5 and the output switching circuit 8. The address selection circuit outputs the rule calculation result to a predetermined address. The input switching circuit 6 controls whether to pass the output of the address selection circuit 5 or input data from the outside in response to a control signal from the chip switching controller 9. The output of this input switching circuit 6 is supplied to a center of gravity '1fjr calculation circuit 7.

Then, the center of gravity is determined from the output from the input switching circuit 6, and the center of gravity value is supplied to the output switching circuit 8. The output switching circuit 8 is
Depending on the control signal from the chip switching controller 9, it is determined whether the output of the rule calculation circuit 4 is passed through or the center of gravity calculation circuit 7
This controls whether the output of the is passed through. The output of this output switching circuit 8 is output to an external terminal.

Here, in the above configuration, when operating in the first mode as a completed fuzzy inference circuit, the input switching circuit 2 passes the output of the latch 1 by the control signal from the chip switching controller 9, and the input switching circuit 6 passes the output of the address selection circuit 5, and furthermore, the output switching circuit 8
is controlled to pass the output of the center of gravity calculation circuit 7, that is, the center of gravity value, and output it to the outside. In the second mode, in which it operates as a rule calculation circuit, the input switching circuit 2 passes the input data as it is, and the input switching circuit 6 is configured not to perform any meaningful operation in response to the control signal from the chip switching controller 9. Further, the output switching circuit 8 is controlled to pass the output of the rule calculation circuit 4 and output it to the outside. In the third mode, in which it operates as a center-of-gravity calculation circuit, the input switching circuit 2 is controlled by the control signal from the chip switching controller 9 so as not to perform any particularly meaningful operation, and the input switching circuit 6 does not receive input data. The output switching circuit 8 is controlled to pass the output of the center of gravity calculation circuit 7 and output it to the outside. As mentioned above, the first mode is a complete fuzzy inference circuit, and the second mode is a rule calculation circuit.
The circuit configuration is such that it can operate in both the mode and the third mode as a center of gravity calculation circuit.

Now, the time division digital fuzzy circuit shown in FIG. If connected to two centroid calculation units 11, it becomes a digital fuzzy circuit capable of parallel calculation as shown in FIG.

Therefore, when this time-division digital fuzzy circuit is made into a chip, the added value of the chip can be increased by making it capable not only of time-division operation but also of parallel operation using the configuration shown in Figure 2. . In other words, one chip can be used by switching between three modes according to the purpose of use: "time-division fuzzy calculation", "rule part calculation", and "center of gravity calculation". Let's discuss an example.

FIG. 3 shows a reconfiguration of the conventional time-division digital fuzzy circuit shown in FIG. 14, taking into consideration chip design and parallel operation. At this time, a practical problem is the increase in the number of external input/output terminals as a chip, which occurs when the circuit is divided into the rule calculation unit 1o and the center of gravity calculation unit 11 for dual use in parallel calculation. In order to solve this problem, in the circuit shown in FIG. 3, the input switching circuit 22 is added to the time division digital fuzzy circuit shown in FIG.
．． 25 and an output switching circuit 28, some external input/output terminals are assigned to two types of signal lines.

In addition, in order to smoothly perform the switching function of the circuit, an input switching circuit 22, an oven drain output MAX calculation circuit (0, D,
A MAX circuit) 33, a shift address circuit 34, and a chip switching controller 32 are added. The chip switching controller 32 receives a switching signal from the outside and outputs a control signal to the input switching circuits 22, 25, the output switching circuit 28, 06, the DMAX circuit 33, and the shift address circuit 34.
The operation of these circuits is switched according to each mode of the chip.

Here, each chip switching mode according to the purpose of use of the circuit shown in FIG. 3 will be explained. First, the first mode is a mode in which the above circuit is used as a time division digital fuzzy calculation circuit. In this case, the input switching circuit 22 selects the output from the latch group 21 and outputs the output from the rule calculation circuit 23.
The input switching circuit 25 selects the output from the shift calculation circuit 27 in the address selection MAX circuit 24 and supplies it to the center of gravity calculation circuit 26. The shift address circuit 34 is
It is configured as shown in FIG. 4, and includes an address gate circuit 42, an open drain output MIN calculation circuit (
○, D, MIN circuit) 43 and a data select circuit 44 are added. In this first mode, the data select circuit 44 of the shift address circuit 34 selects the output of the address latch section 41 and supplies it to the subtraction circuit 35, so in this case, the circuit shown in FIG. It does the same thing. The output switching circuit 28, as shown in FIG.
X circuit) 46, and Orbtrain output buffer circuit (0
, D, buffer circuit) 45, and in this first mode, all bits of the output of the 0, D, MAX circuit 46 are open (high impedance!! 3), so 0.
D.

The output of the buffer circuit 45, that is, the output of the shift calculation circuit 27, is output to the external output terminal To. The operation of the entire circuit in this first mode is the same as the operation of the time-division digital fuzzy circuit described above, so a description thereof will be omitted here.

Next, the second mode will be explained. This second mode is a mode in which the circuit shown in FIG. 3 is used as a rule calculation circuit. In this second mode, the center of gravity calculation unit 11
is no longer necessary, so the external output terminal T used for outputting the center of gravity value in the first mode. is used by the output switching circuit 28 as an output terminal for the output signal SO of the multiplexer 36. At this time, in the configuration shown in FIG. 6, the output switching circuit 28 receives a control signal from the chip switching controller 32, and the output of the O, D buffer circuit 45 becomes an oven (high impedance state).
The output signal SO of 6 is O, D.

External output terminal T through MAX circuit 46. is output to. Further, output signals SL and S2 of the multiplexer 36 are outputted to external output terminals T1 and T2 through O, D, and MAX circuits 46, respectively.

Above 0. D, MAX circuit 33.46 is patent application 1986-27
It is similar to the MAX calculation circuit shown in 8797, and when the outputs of the O, D, MAX circuits 33 and 46 are connected in common, the maximum value will be output.

Further, the input switching circuit 22 selects inputs A and B that do not pass through the latch group 21 and supplies them to the rule calculation circuit 23. The address gate circuit of the shift address circuit 34 (see FIG. 4) is shown in FIG. 5, and the area serves as input data. Since the operation of this address gate circuit 42 has been described above, its explanation will be omitted. The outputs of the address gate circuit 42 are O and D.

The signal is supplied to the MIN circuit 43. 0. D, MIN circuit 43
is similar to the MIN calculation circuit shown in Japanese Patent Application No. 63-278798, and this Old, MIN circuit 43
If multiple outputs are connected in common, the minimum value will be output.

Further, the data selector circuit 4 of the shift address circuit 34
4 (see FIG. 4) selects the output of the O, D0 MIN circuit 43 and supplies it to the subtraction circuit 35.

If only the necessary circuits are extracted in the second mode and FIG. 3 is re-illustrated, the result will be as shown in FIG. 7.

Next, the third mode will be explained. This third mode is a mode in which the circuit shown in FIG. 3 is used as a center of gravity calculation circuit. In this third mode, the rule calculation unit 10
becomes unnecessary. Therefore, the output switching circuit 28 selects the center of gravity value output from the shift calculation circuit 27 and outputs it to the external output terminal T.

Output to.

The input switching circuit 25 selects inputs A, B and parameter inputs and supplies them to the center of gravity calculation circuit 26. In this third mode, the external input terminals 10% II and I4, which were assigned as inputs A, B and parameter inputs in the Ml and I2 modes, are used as a rule calculation circuit in the second mode. O, D, MA of the circuit shown in Figure 3
They are assigned as input terminals for the output signals So, SL, and S2 from the multiplexer 36 through the X circuits 33 and 46, respectively. If only the necessary circuits are extracted in this third mode and FIG. 3 is redrawn, the result will be as shown in FIG. 8.

Each chip switching mode has been explained above.The first mode performs inference operation independently as a time-division digital fuzzy circuit as described above, but the second mode operates independently as a time-division digital fuzzy circuit. In the third mode, inference operations cannot be performed independently, and a parallel operation structure as shown in FIG. 2 must be used. The second mode (Fig. 7) and the third mode (Fig. 8) are used to
If you configure a parallel computing fuzzy inference circuit as shown in the figure, the ninth
It will look like the figure.

Next, a modification will be explained. In the above configuration, considering reducing the number of external terminals as a chip, it is possible to select an address as shown in the M2O diagram without using the address selection MAX circuit 24 in the rule calculation chip of the parallel calculation fuzzy circuit shown in FIG. MAX circuit 50 as an external circuit (external circuit)
0. in the chip. D, MAX circuit is 33.46
This becomes unnecessary, and the external terminals in FIG. 3 become as shown in FIG. 11, thereby reducing the number of external terminals. At this time, address selection M is shown in FIG.
There is an AX circuit 24a, but this is used only in the first mode and in the second mode. In the third mode, it will not be used at all. Along with this change in circuit, the output switching circuit 28a is also changed as shown in FIG. Since the output switching circuit 28a inputs the output of the rule calculation circuit 23 instead of the output signal SO of the multiplexer 36, O,
D.

The MAX circuit 33 is no longer necessary, and instead, the MAX circuit 33 is replaced by O, D.

Buffer circuits 47 and 48 are provided. Rule calculation circuit 2
When output No. 3 is not selected, all bits of the O, D and buffer circuits 47 in FIG. 12 are in a high impedance state. Further, as shown in FIG. 11, the shift address circuit 34 is also a 414 circuit consisting only of an address latch circuit and a zero determination circuit as shown in FIG. 16. In this case, if only the necessary circuits are extracted and FIG. 3 is redrawn, the result will be as shown in FIG. 13.

Furthermore, if a parallel calculation fuzzy circuit is configured using the circuit shown in FIG. 11 (referred to as the fourth mode), it will be as shown in FIG. 14. Also, the address selection M in FIG.
The AX circuit 50 is as shown in FIG.

As described above, the switching circuits 2.6.8 are provided at key points of each block constituting the fuzzy inference circuit, and the T41 as a completed fuzzy inference circuit is controlled by the control signal from the chip switching controller 9 as a control circuit. The circuit configuration is such that it can operate in either mode, the second mode as a rule calculation circuit, or the third mode as a center of gravity calculation circuit. It can be used not as a chip but as a general-purpose chip, and since input/output terminals are shared by a switching circuit, a digital fuzzy circuit with a small number of input/output pins can be constructed.

[Effects of the Invention] As detailed above, according to the present invention, despite its simple configuration, it can be used as a complete fuzzy inference circuit, a circuit dedicated to rule calculation, or a circuit dedicated to center of gravity calculation. It is possible to provide a digital fuzzy circuit that is usable and can reduce the number of bins when configured as an IC chip.

[Brief explanation of drawings]

1 to 14 show embodiments of the present invention,
Figure 1 is a basic block diagram of a digital fuzzy circuit, Figure 2 is a basic block diagram of a digital fuzzy circuit.
The figure is a block diagram of a digital fuzzy circuit configured to allow parallel operations, Figure 3 is a specific block diagram of the digital fuzzy circuit, Figure 4 is a block diagram showing the configuration of a shift address circuit, and Figure 5 is an address gate circuit. 6 is a block diagram showing the specific configuration of the output switching circuit, FIG. 7 is an explanatory diagram showing only the parts involved when operating in the second mode, and FIG. 8 is a block diagram showing the specific configuration of the output switching circuit. The figure is an explanatory diagram showing only the parts involved when operating in the third mode, FIG. 9 is a block diagram when a parallel operation fuzzy inference circuit is configured using the second and third modes, and FIG. The figure is a block diagram of an address selection MAX circuit when the address selection MAX circuit is configured with an external circuit. Figure 11 is a concrete block diagram of a digital fuzzy circuit when an external address selection MAX circuit is used. Figure 12 is a block diagram showing the configuration of an output switching circuit when an external address selection MAX circuit is used, and Figure 13 is an explanatory diagram showing only the parts involved in the operation when an external address selection MAX circuit is used. , FIG. 14 is a block diagram when a parallel operation fuzzy inference circuit is configured using an external address selection MAX circuit, and FIGS. 15 and 16 show conventional digital fuzzy circuits. The figure is a basic block diagram of a digital fuzzy circuit, and FIG. 16 is a block diagram showing the configuration of an address selection MAX circuit. DESCRIPTION OF SYMBOLS 1... Latch (latch means), 2... Input switching circuit (first input switching circuit), 3... Membership function switching circuit, 4... Rule operation unity, 5... Address selection circuit (maximum value calculation section), 6...input switching circuit (second
(input switching circuit), 7... Center of gravity calculation circuit, 8... Output switching circuit, 9... Chip switching controller (control circuit).

Claims (1)

[Scope of Claims] A latch means for latching input data; a first input switching circuit for switching between inputting either the latched data or the input data to the latch means; and the first input switching circuit. a rule calculation circuit that outputs an inference result from the data that is switched and input by the membership function switching circuit and the membership function that is switched and given by the membership function switching circuit; a maximum value calculation unit that calculates the maximum value of the inference result for each address; a second input switching circuit that switches between inputting the calculation result of the maximum value calculation unit or the input data; a center of gravity calculation circuit that calculates the center of gravity based on data that is switched and inputted by the input switching circuit; and an output that switches between outputting either the center of gravity value calculated by the center of gravity calculation circuit or the inference result output by the rule calculation circuit. a first mode in which all of the rule calculation circuit, the maximum value calculation unit, and the center of gravity calculation circuit are operated by controlling switching of the switching circuit, the first and second input switching circuits, and the output switching circuit; A digital fuzzy circuit comprising: a control circuit that operates in either a second mode that operates only the rule calculation circuit or a third mode that operates only the center of gravity calculation circuit.