JPH0366217U - - Google Patents
Info
- Publication number
- JPH0366217U JPH0366217U JP12633989U JP12633989U JPH0366217U JP H0366217 U JPH0366217 U JP H0366217U JP 12633989 U JP12633989 U JP 12633989U JP 12633989 U JP12633989 U JP 12633989U JP H0366217 U JPH0366217 U JP H0366217U
- Authority
- JP
- Japan
- Prior art keywords
- circuits
- output terminal
- level adjustment
- limiter circuit
- adjustment limiter
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 6
Landscapes
- Tone Control, Compression And Expansion, Limiting Amplitude (AREA)
Description
第１図乃至第６図は本考案の一実施例に係り、
第１図は低レベル信号処理装置の電気的構成を示
すブロツク線図、第２図は第１、第２の増幅回路
の入出力特性図、第３図はレベル調整リミツタ回
路の入出力特性図、第４図は第１、第２の増幅回
路の入出力特性図、第５図は減算回路の入出力特
性図、第６図は第３の増幅回路の入出力特性図で
ある。
４……レベル調整リミツタ回路、５……第１の
増幅回路、６……第２の増幅回路、７……減算回
路。
1 to 6 relate to an embodiment of the present invention,
Fig. 1 is a block diagram showing the electrical configuration of the low-level signal processing device, Fig. 2 is an input/output characteristic diagram of the first and second amplifier circuits, and Fig. 3 is an input/output characteristic diagram of the level adjustment limiter circuit. , FIG. 4 is an input/output characteristic diagram of the first and second amplifier circuits, FIG. 5 is an input/output characteristic diagram of the subtraction circuit, and FIG. 6 is an input/output characteristic diagram of the third amplifier circuit. 4... Level adjustment limiter circuit, 5... First amplifier circuit, 6... Second amplifier circuit, 7... Subtraction circuit.
Claims (1)
ミツタ回路の出力端に接続された入出力特性が互
いに異なる２つの増幅回路又は減衰回路と、これ
ら増幅回路又は減衰回路の各出力端に接続された
減算回路とを備えた低レベル信号処理装置。 A level adjustment limiter circuit, two amplifier circuits or attenuation circuits with different input/output characteristics connected to the output terminal of the level adjustment limiter circuit, and a subtraction circuit connected to each output terminal of these amplifier circuits or attenuation circuits. Low-level signal processing equipment with
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12633989U JPH0366217U (en) | 1989-10-26 | 1989-10-26 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12633989U JPH0366217U (en) | 1989-10-26 | 1989-10-26 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0366217U true JPH0366217U (en) | 1991-06-27 |
Family
ID=31674153
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP12633989U Pending JPH0366217U (en) | 1989-10-26 | 1989-10-26 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0366217U (en) |
-
1989
- 1989-10-26 JP JP12633989U patent/JPH0366217U/ja active Pending
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