JPH0364210A - Multi-channel pulse width modulation signal generator - Google Patents

Abstract

PURPOSE:To decrease the number of composing elements and to reduce the hardware quantity by using an array of CAM cells serving as the storage elements which have the comparing functions and are addressable according to their contents to form each register and each comparator. CONSTITUTION:A comparing register block 150 consists of comparing registers 151-154 which have the comparing functions and map the memories to store the comparison values. A buffer circuit 130 is added to output the data to each comparing register together with a binary counter 200 which performs an increment action every two reference clocks and produces an overflow signal 201, and a buffer circuit 190 which outputs the count value of the counter 200 to the block 150. The registers 151-154 consist of the storage elements (CAM) which are addressable according to their contents. Thus plural comparing registers can be obtained. In such a constitution, both the circuit 190 and the counter 200 can be shared and therefore the hardware quantity is reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a pulse width modulation signal generator, and more particularly to a multi-channel pulse width modulation signal generator built into a single-chip microcomputer.

[Conventional technology]

Currently, single-chip microcomputers are used as system controllers in many types of home appliances. This single-chip microcomputer is used as a system controller in VTRs, CDs, cassette decks, etc., and is used not only to determine manual key force, control indicator display, and control operation sequences, but also to control motors.

In a VTR, a cylinder motor is used to rotate the head.

A DC motor is used as the tape feeding capstan motor because it is small and lightweight, and the phase speed of each motor is controlled. In addition, a loading motor 2, a volume motor that can be adjusted with a remote control, etc.
As the functionality of a system expands, the number of motors used in one system tends to increase. Phase speed control of these DC motors is accomplished by driving the motor by converting the control output of a microcomputer into a digital value or an analog value.

Normally, in consumer systems, it is necessary to minimize the number of component parts to reduce costs, and in systems that include many motors to be controlled, a single-chip microcomputer with a built-in multi-channel digital-to-analog converter is required. is desired.

Conventionally, digital-to-analog converters with built-in single-chip microcomputers include weighted voltage/current source methods, resistor ladder single methods, pulse width modulation methods, etc. Among them, digital-to-analog converters using pulse width modulation methods Since the accuracy can be defined by the resolution (quantization bit number), it is easy to obtain the desired accuracy, and it can be configured with a simple digital synchronization circuit, and it is suitable for IC implementation due to its low power consumption and other reasons. It was used more frequently than other methods.

Typical pulse width modulation signal generators (hereinafter referred to as PWM signal generators) include a pulse generator, a binary counter,
It consists of a register, a comparator using a Nant gate, and an RS flip-flop. After setting the RS flip-flop, the counter starts counting, and the comparator detects that the digital value set in the register matches the counted value. A digital-to-analog converter is known from Japanese Patent Publication No. 48-44823, which generates a PWM signal by resetting an RS flip-flop when it is detected.

However, when configuring a multi-channel PWM circuit, conventional PWM signal generators are configured using random logic such as counters and registers, and simply configuring them requires a large number of transistors.
Since each transistor is also large, it occupies P in the chip.
The proportion of WM signal generators increases. That is, since the amount of hardware increases, a problem arises in that the cost increases.

On the other hand, in the tuner section of a VTR, the channel selection operation is performed by a pulse width modulation D-A converter, which requires a high-precision PWM signal generator with a resolution of 12 bits or more and a repetition frequency of 20 KHz or more. PWM signal generators cannot achieve this performance.

As such a high-precision PWM signal generator, a PWM signal generator with a binary rate multiplier (hereinafter referred to as BRM) is required.

This BWM signal generator with BRM combines a conventional low-resolution, high-repetition-frequency PWM signal generator and a BRM circuit (a circuit that generates a desired analog signal by integrating pulses). It is constructed to obtain high precision, and is
01. It is known from Japanese Patent Application Laid-Open No. 58-121827.

In such a PWM circuit with WM, in addition to the PWM signal generator, registers, counters, and encoders are added, which increases the amount of hardware. As the area increases, the problem of increased costs becomes even more serious.

[Problem to be solved by the invention]

The conventional PWM signal generator described above is composed of random logic such as a binary counter, a conveyor register, a comparator, and an RS flip-flop.The random logic circuit has a large number of constituent transistors, and each transistor is large. Therefore, when it is integrated into an integrated circuit, it occupies a considerable area on a chip, which increases the cost. Furthermore, if a plurality of PWM signal generators were installed on one chip, the amount of hardware would further increase, and the chip area would become larger, resulting in higher costs.

The purpose of the present invention is to solve such problems and to provide a multi-channel PW with a small number of structural elements and a reduced amount of hardware.
An object of the present invention is to provide an M signal generator.

[Means to solve the problem]

The configuration of the present invention includes a pulse generator that outputs a predetermined clock, a counter that counts the output of this pulse generator, a register that stores a comparison value that defines the pulse width of a pulse width modulation signal, and a plurality of these. In a multi-channel pulse width modulation signal generator that outputs a plurality of pulse width modulation signals, each channel includes a comparator that compares a stored value of a register with a count value of the counter, and each of the registers and each comparator is characterized in that it is constructed by an array of CAM cells, which are storage elements that have a comparison function and can be addressed depending on the contents.

Further, in the present invention, the buffer circuit of the counter is BR
It may also include an M encoder.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram showing a first embodiment of the present invention;
3 is a circuit diagram of the CMA storage element and conveyor register block used in FIG. 1, and FIG. 4 is a time chart explaining the operation of FIG. 1. The PWM signal generator of the first embodiment has an internal data bus 10 connected to a central processing unit 101 (hereinafter referred to as CPU) that performs program processing.
0, and outputs a control signal that controls the operation and timing of the PWM signal generator, a register selection signal, and a clock signal, and an operation control section 120 that has a comparison function and stores a comparison value. a conveyor register block 150 consisting of four conveyor registers 151 to 154 memory-mapped to a buffer circuit 130, a binary counter 200 that increments once every two reference clocks and generates an overflow signal 201 upon overflow, and a conveyor register block that buffers the count value of this counter 200 and transfers it to a conveyor register block at timing TB. a second buffer circuit 190 that outputs a count value for 150; and a counter 20;
The coincidence signals 161-164 of each conveyor register 151-154 are set by the overflow signal 201 of 0.
The output signal PWM signals 181 to 18 are reset by
RS flip-flops 171 to 1 that output 4, respectively.
74. This conveyor register 151
154 are comprised of memory elements (hereinafter referred to as CAM) that can be addressed depending on the content.

Since the functions of each conveyor register and RS flip-flop are the same, the conveyor register 151 and RS flip-flop 171 will be explained.

First, to operate the PWM signal generator, CPUl0
The internal data bus 10 is
0, the comparison value and control information are transferred to the conveyor register 151 of the conveyor register block 150 and the operation control unit 120.
and set them respectively. The operation control section 120 generates an operation control signal based on the set operation designation information, and operates the counter and selects the input clock signal CLK.

Next, this PWM signal generation operation will be explained with reference to the timing diagram of FIG. This figure shows the comparison values n-1, n, n
+1 is set in the conveyor register 151, and the counter 2
00 is shown, and in particular, each signal in a count cycle in which a match between a comparison value and a count value is detected by a comparison operation is shown.

The basic timing of the counting operation of the counter 200 is 1
The count-up operation is performed in two reference clock times (hereinafter referred to as a count cycle), and this count cycle is divided into counting and comparison operations of the counter 200 (
One reference clock time is allocated to each of the comparison stage (hereinafter referred to as comparison stage) and the data access of CPU10I (hereinafter referred to as CPU stage). That is, one count cycle is divided into two stages, and one increment is performed in the comparison stage. Note that the reference clock signal is frequency-divided to generate a timing signal TA indicating the CPU stage and a timing signal TB indicating the comparison stage during the high level period.

The CPU 101 sets a comparison value in the conveyor register 151 via the internal data bus 100 by operating the first buffer circuit 130 and activating the selection signal 141 during the high level period of the timing signal TA. This is done by selecting the conveyor register 151 and latching the output of the first buffer circuit 130.

The operation of comparing the count value of the counter 200 and the comparison value set in the conveyor register 151 is performed by transferring the count value of the counter 200 buffered by the second buffer circuit 190 to the conveyor register block 150 during the high level period of the timing signal TB. When a match occurs, the conveyor register 151 outputs a match signal 161.
is output to the RS flip-flop 0 knob 171.

Next, the output signal 181 when the comparison value (n - 1) is set in the conveyor register 151 will be explained.

Here, for convenience of explanation, it is assumed that the counter 200 is an m-bit counter, and the relationship between the comparison value and the counted value is 2''>n. The RS flip-flop 171 is set to reach the n) level. In the comparison stage when the counter 200 counts up and its count value reaches (n-1), the conveyor register 51
It detects that the value and the comparison value match, and outputs a match signal [1]. The output signal 181 becomes low level due to the reset of the RS flip-flop 171 in synchronization with the falling edge of the match signal 161.

By repeating this operation, the duty ratio ((-'
=-) x 100) (%) is output as the output signal 181.

The basic generation operation of the PWM signal when n and (n+1) are set in the conveyor register 51 is the same as when (n-1) is set, and the output timing of the coincidence signal 161 is the count value of the counter 200. It only shifts to n and (n+1) comparison stages. Therefore, the falling timing of the output signal 181 is shifted, and when n is set as the comparison value, the duty ratio ((=) × 100)
(%) PWM signal, if (n+1) is set, the duty ratio ((-7-) x 100) (%
) is obtained. That is, by changing the set value of the conveyor register 51, various PWM signals having a resolution of 1/2'' can be output.

Note that this comparison operation is possible due to the function of the CAM cells forming the conveyor registers 51 to 54, so that four conveyor registers can be compared simultaneously in the comparison stage.
A multi-channel PWM signal generator that generates signals can be constructed.

Next, regarding the memory element (CAM cell) that has a comparison function and is addressable according to the content of storing the comparison value, which constitutes the conveyor register, the 1-bit (CA
This will be explained below with reference to the transistor configuration diagram of the cell (M cell).

The CAM cell consists of 10 transistors Tl, T2,...
. . . It is composed of T10 and can store 1 bit of information. Human output line between true value and negative value, D
, a cell selection signal line S, and a data discrimination output line C. Transistors TI, T2 . T3 and T4 constitute a flip-flop circuit that can be inverted based on input data, and one bit of information is stored depending on the inverted state of this flip-flop circuit. When reading information stored in a cell with this configuration, a cell selection signal is supplied to the cell selection signal line S, and the transistors T5. T6 is made conductive and the data stored in the flip-flop circuit is read out to the data input/output line D.

On the other hand, when writing information to a cell, supply the true value and negative value of the information to be written to the data input/output line D,
A cell selection signal is generated and supplied to the cell selection signal line, and transistors T5. T6 is made conductive and the data to be written is supplied as described above to set the state of the flip-flop circuit to a state corresponding to the data to be written.

If the cell is to store a logic value 1n, the connection point between the transistors Tl and T2 is shifted to a high level, and the transistors T3... Shift the connection point of T4 to low level.

On the other hand, when storing the logical value "0", on the contrary, the connection point between the transistors T1 and T2 is shifted to a low level, and the connection point between the transistors T3 and T4 is shifted to a high level.

Furthermore, the four transistors T7 to TIO, which are moved in series and in parallel between the ground and the data output line C, are for determining the memory contents of the cell.
The on/off state changes depending on D and the memory value of the cell, and this changing state, including the data discrimination output C,
Shown in the table.

Below is the blank space in Table 1. Here, the ground potential state of the data discrimination output C is set to the logic value "0".
, if the state of no conduction is the logical value l'', then when a signal with an inverted logical value is applied to the data input/output line D,
An exclusive OR signal indicating a mismatch between the data input/output signal and the cell storage value is obtained at the data discrimination output C, and the comparison can be determined. When a logic value "0" is applied to both of these data input/output lines D, a logic value "1" equivalent to a match is obtained regardless of the cell memory value, and a comparison judgment with the memory contents is obtained. can be excluded from the scope of

In addition, when a logic value "1" is applied to both the data input/output line and D, the logic value "0" is applied regardless of the cell memory value.
is obtained, and it is possible to unconditionally output a determination result of non-coincidence.

By arranging the CAM cells shown in FIG. 2 in a row and column structure and outputting data discrimination outputs C in parallel, conveyor registers 151 to 154 capable of content discrimination as words are realized.

FIG. 3 is a circuit diagram showing the arrangement of elements in the conveyor register block 150 of FIG. 1 and the configurations of the first buffer circuit 130 and the second buffer circuit 190. In this register block, one row of the CAM cell array corresponds to one conveyor register. Match signal 1.61-16
4 is the same signal as in FIG.

The four transistors T31 to T34 are loads for the data discrimination output C of each data storage cell connected in parallel,
When the discrimination output C in all the cells of the corresponding data is in a non-conductive state, the logic value "1" is set as the coincidence signal 161 to 16.
Generate as 4. Therefore, if a mismatch is determined in any of the cells and a ground potential is output to the discrimination output, a logic value of 0'' is generated in any of the match signals 161 to 164.

The first buffer circuit 130 operates during the high level period of timing TA when the CPUl0I writes and sets data, and transfers the write data via two data input/output lines per column of memory cells. Let's do it. The first buffer circuit 130 includes ten inverters. and 10
It is composed of transistors Tll to T20. The output of the inverter E, ~ creates a signal to be applied as an input data bar signal port to the CAM cell corresponding to each bit, and the output of the inverter E, ~11° is the output of the inverter E, ~
The output of the process is used as an input signal, inverted again, and applied to each CAM cell as an input data signal. In addition, the transistors Tll to T20 transmit input data to CA.
This is a control gate for the timing applied to the M cells, and is turned on during the 1 level period of the timing signal TA to apply the input data signal r and the input data bar signal r to each CAM cell.

Similarly, the buffer circuit 190 buffers the count value of the counter 200 when comparing the stored value and the count value, operates during the high level period of the timing signal TB, and has two data input/output lines per column of memory cells. Outputs the count value for.

The second buffer circuit 190 includes l0 inverters I1
The output of the inverters La to T2 degrees inverts the count signal of the counter 200 corresponding to each bit and sends the input data to each CAM cell. - applied as signal i. Inverters L+~Ls are inverters Ill~I
The count value inverted by 2° is inverted again and applied to each CAM cell as an input data signal. Transistors T21 to T30 are control gates for the timing of applying the count value to the CAM cells, and are turned on during the high level period of the timing signal TB to use the count value as the input data signal and to use the inverted value of the count value as the input data signal. Each C as a signal hundred
Apply to AM cell.

Therefore, during the high level period of the timing signal TA, C
PUl0I becomes the CPU stage that performs data access to the conveyor register, and the master timing signal T
The high level period of B is defined as a comparison stage in which the count value of the counter 200 and the comparison value stored in the conveyor register are compared.

Additionally, as described above, the conveyor register block 150
Since this is arranged in a matrix structure in a plurality of CAM cells, it is possible to simultaneously perform a comparison operation between the comparison value set in each conveyor register and the count value of the counter 200 in the comparison stage.

As described above, in the PWM signal generator, a plurality of conveyor registers can be formed by arranging memory elements (CAM cells) having a comparison function and storing comparison values in a matrix structure. Therefore, by sharing buffer circuits and counters, a multi-channel PW that reduces the amount of hardware
M signal generator can be configured.

FIG. 5 is a block diagram showing a second embodiment of the present invention. This embodiment is a multi-channel PWM signal generator with BRM.
The configuration includes an M encoder 260, a second counter 270, and a pulse control circuit 240.

The second conveyor register block 220 generates a P
This is a register array that stores setting values for adding a BRM pulse to a WM signal, and is composed of the lower parts 221 to 224 of each conveyor register that are memory mapped. This conveyor register 151 and 220 are also the first
Like the conveyor register block 150, it is composed of CAM cells.

The second counter 270 is a binary counter that performs a counting operation in synchronization with the overflow signal of the counter 200, and the ERM encoder 260 encodes the count value of the counter 270 and outputs it to the conveyor register block 220 during the comparison stage. and output it.

The pulse control circuit 240 is connected to the conveyor register block 1
The coincidence signals 161 to 164 of each of the conveyor registers 50, the coincidence signals 221 to 224 of each conveyor register of the conveyor register block 220, and the overflow signal 201 of the counter 200 are input, and the generation of the PWM signal and the expansion control of the pulse width are performed. output signal 251
~254 is generated.

Since the functions of each conveyor register and the control for each signal in the pulse control circuit are the same as those in FIG. 1, the explanation will be given for the case where the number of bits is 4, focusing on the lower order 221 of the conveyor register.

Note that the operation of setting control data for operating the first PWM signal generator with ERM and the generation of operation control signals are the same as in the first embodiment. Therefore, the comparison values for the conveyor register 151 and the conveyor register 221 These settings are performed at the same timing via the internal data bus 100, which has a bus width equal to the sum of the bit widths of both registers, based on the aforementioned operation control signal.

The ERM encoder 260 configures the lower part 221 of the conveyor register in accordance with the count value of the counter 270.
Signals to be applied as the input data signal and the input data bar signal of the M cell are generated, and the correspondence table of the enriched signals is as shown in Table 2.

Table 2 with blank space below In this table, the count value of the counter 270 is expressed from the least significant bit by GO+ C1l C21Css Each bit of the lower 221 of the conveyor register is expressed from the least significant bit by Be, E
It is expressed as 3t, Bt, and Bs.

As shown in FIG. 2, each CAM cell constituting the lower 221 of the conveyor register is operated for each bit by applying "1" to the input data signal and "0" to the input data signal. It can be determined that "1" is stored in the CAM cell.Also, by applying "1" to both the input data signal and the input data signal i, the data stored in the CAM cell can be excluded from comparison. can do.

Therefore, the third pit (lower 221) of the conveyor register) B3
is the count value of the counter 270 1, 3, 5° 7.9, 11,
13 and 15, the second pitch) B2 is the count value 2,
The first bit (Bl) is compared when the count value is 4, 12, and the 0th bit Bo is compared when the count value is 8.

In other words, there is a timing at which the first bit is compared twice. Furthermore, if 1'' is stored in the cell of the corresponding bit, a match signal will be output at the comparison timing.

For example, when 100OB (hereinafter B indicates binary representation), 0100B, 0OIOB, and 0001B are set as the comparison value for the lower 221 bits of the conveyor register, the count value of the second counter 270 and the coincidence signal 231
A timing diagram showing the correspondence relationship of A is shown in FIG.

The logic for generating the coincidence signal 231 in this timing diagram is shown by the following logical equation.

Match signal 231 ” Go・B s + Cr・C0・B2+C2・C
.

・C0・B 1+ C3・C2・C1・C0・B0 Therefore, if multiple bits of the comparison value are logical “1”,
A coincidence signal 231 is outputted by taking the logical sum of the coincidence signals as in the above-mentioned logical formula.

FIG. 7 is a block diagram showing the circuit of BRM encoder 260. This BRM encoder 260 is composed of four inverters 21-23, three Nant gates 24-26, and eight transistors T40-T47. Each signal is here. ~D3 are connected to the input data signal line of the CAM cell, and signals Do~Ds represent signals connected to the input data bar signal r line. The inverter 21 inverts the output signal of the 0th bit of the second counter 270 and D
Output as 3 signals. The Nant gate 24 inputs the inverted signal of the 0th bit and the output signal of the 1st bit, performs an AND operation, and outputs the inverted signal as an i-th signal, and the inverter 22 inverts the output signal of the 1st bit. The Nant gate 25 inputs the inverted signal of the O-th bit, the inverted signal of the first bit, and the output signal of the second bit, performs a logical product, and outputs the inverted signal as a DI multiplied signal. Inverter 23 inverts the second bit output signal. The Nant gate 26 receives the inverted signal of the 0th bit, the inverted signal of the 1st bit, and the inverted signal of the 2nd bit.
Inputs the inverted bit signal and the output signal of the third bit,
The ANDed and inverted signal is output as a DO signal.

Here, the Do to D3 signals are “1” in the CAM cell.
In order to judge the voltage, the power supply voltage V
Connected to DD.

Such a circuit generates each encode signal shown in Table 2.

Further, the transistors T40 to T47 are gates that control the timing of applying an encode signal corresponding to the count value of the second counter 270 to the input data signal line and the input data bar signal r line of each CAM cell. , is on during the high level period of the timing signal TB, and each CAM
Outputs an encoded signal to the cell.

FIG. 8 is a block diagram of the pulse control circuit 240 of FIG. 5. This pulse control circuit 240 is composed of RS flip-flops 30-33, AND gates 34-37, D flip-flops 38-41, and OR gates 42-45.

The RS flip-flops 30-33 are each set in synchronization with the falling edge of the timing signal TB by the overflow signal 201 of the counter 200, and are set in synchronization with the falling edge of the timing signal TB by the coincidence signals 161-164 of the conveyor registers 151-154. Each is reset synchronously.

AND gates 34 to 37 are RS flip-flops 30
~33 output signals and the lower 221 of the conveyor register ~
The coincidence signals 231 to 234 of 224 are inputted, and each logical product is calculated.

The signals are output to blocks 38 to 41, respectively.

D flip-flops 38-41 are AND gates 34-
The output signals of 37 are respectively input, and the previous state of the D input is latched at the falling edge of the timing signal TB and held until the next falling edge. OR gates 42-45 are RS
The output signals of the flip-flops 30 to 33 and the output signals of the D flip-flops 38 to 41 are respectively inputted, and the logical OR thereof is taken to output the output signals 251 to 254, respectively.

Next, refer to the timing diagram of FIG.
Regarding the operation of the M signal generator, the conveyor register 151
A case will be explained in which the setting value of the lower 221 of the n1 conveyor register is 1000B.

The counter 200 increments the count value in synchronization with the falling edge of the timing signal TB indicating the comparison stage.
The count value is incremented in synchronization with the falling edge of the overflow signal 201 of 0.

Note that the hatching in the cycle item in FIG. 9 indicates the comparison stage.

In the comparison stage when the counter 200 counts n, a match between the set value of the conveyor register and the counted value is detected, and during the high level period of the timing signal TB, a match signal 16 is detected.
Outputs 1.

When the count value of the second counter 270 is "0", the output signal 251 becomes high level in synchronization with the falling edge of the overflow signal 201, becomes low level in synchronization with the falling edge of the match signal 161, and the output signal 251 becomes a low level in synchronization with the falling edge of the match signal 161, and the ratio ((=
) X l 00) Outputs a PWM signal of (%).

Next, in the comparison stage where the second counter 270 counts "1" and the count value of the counter 200 is "0",
When a match is detected between the set value of the lower 221 of the conveyor register and the count value of the second counter 270, a match signal A is generated during the high level period (comparison stage) of the timing signal TH.
is output at each comparison stage until the counter 200 overflows.

When the coincidence signal 161 falls due to detection of coincidence between the set value and the count value of the conveyor register 160A in the comparison stage of the count value n'' of the counter 200, the pulse width of the output signal 251 is controlled to be expanded by the coincidence signal 231.

As shown in FIG. 9, when the match signal 231 is at a high level and the output signal Q of the RS flip-flop 30 is at a high level, the output of the AND gate 34 is at a high level, and the D flip-flop 38 is activated at the rising edge of the timing signal TB. The previous state of the D input is latched in synchronization with the falling edge, held until the next falling edge, and output as a Q signal.

Therefore, in the above-mentioned state, when the match signal 161 falls from a high level to a low level in synchronization with the falling edge of the timing signal TB, the RS flip-flop 30 is reset and the Q signal becomes a low level, so that the output of the seventh gate 34 The signal becomes low level. At this time, D
The flip-flop 38 holds the previous state of the D input at a high level until the next falling edge of TE (time indicated by hatching in the output signal 251) and outputs it as a Q signal.

Therefore, when the match signal 231 is at a high level and the match signal 161 changes from a high level to a low level, the high level period of the output signal 251 is extended by one clock of the timing signal TB.

Therefore, if the stored value of the corresponding bit is "1" at each timing determined by the BRM encoder 260, the output signal will be expanded. When the counter 200 is m bits, the first conveyor register value is n, the second counter 270 is 2 bits, and the second conveyor register value is k, the duty ratio ((-) + (call completed)) x 100 (%
) has the same effect as generating the signal 2 2 ×2 as the output signal.

The PWM signal generator with multi-channel BRM of this embodiment uses a conveyor register pro which consists of a comparator and a register by a CAM cell having a comparison function. A multi-channel, high-precision PWM signal generator can be configured by simply adding the elements.

Therefore, it is possible to form a multi-channel PWM signal generator with BRM while minimizing the problem of increased costs due to increased chip area.

FIG. 10 is a block diagram showing a third embodiment of the present invention. The multi-channel PWM signal generator with BRM of this embodiment has a selection circuit 320 and a mode register 300 added to FIGS. 1 and 5, and a single conveyor register block 150a removed from the CAM cell array. The pulse control circuit 310 is different.

In this embodiment, an internal data bus 100 with a bus width of 8 bits is connected to the CPU 101 as well as the memory 102.
A mode register 300 including an operation control unit 110 and an operation control register 111, a buffer circuit 130, a conveyor register 150, a pulse control circuit 310, a selection circuit 320, a buffer circuit 190, a BRM' encoder 260, and a binary It is composed of counters 200 and 270.

The CPU 10I fetches the instructions stored in the memory 102 via the internal bus 100, decodes and executes the fetched instructions, and transfers the setting data to the internal bus 100.
0 to the operation control register 111 and mode register 3.
Transfer and set to 00. The operation control section 110 generates a clear signal and a reference clock signal 127 that control the operation and timing of the PWM signal generator based on the setting data of the operation control register 111 included therein. A frequency-divided CPU stage signal 128 (hereinafter referred to as TA), a CPU stage signal 129 (hereinafter referred to as TB), and six register selection signals 121 to 126 are output.

The mode register 300 is a register with a 3-bit configuration, and is configured to receive a PWM signal (hereinafter, a PWM signal to which no BRM pulse is added will be referred to as a PWM signal) and a BRM signal.

The output of the pulse-added PWM signal is designated, and the control signal 301 corresponding to the second bit to the control signal 303 corresponding to the 2go bit is output to the pulse control circuit 310.

Buffer circuit 130'+! , the setting data placed on the internal data bus 100 by the CPU 101 by executing instructions is TA
is buffered and output to the conveyor register block 150a at the high level timing, and the conveyor register block 150a memory-mapped CA
A conveyor register 151 is connected to a conveyor register 156 from six conveyor registers 151 in an M cell configuration.
~156 stores comparison values, compares the stored comparison values with input data, and generates a match signal 16 when the data match.
Outputs 1 to 166.

The counter 200 receives the count value "
It is cleared to 0'' and performs one increment operation every two clocks of the reference clock signal 127 (hereinafter referred to as a count cycle).It is a binary counter with an m-bit configuration.
A timing signal 211 that becomes high level is generated during a period in which a count value of 2''-1'' is stored.

The counter 270 is an m-bit binary counter that is cleared to a count value "0" by the clear signal 120 and performs one increment operation in synchronization with the overflow of the counter 200.
The count value of the counter 200 is buffered and output to the selection circuit 180 at the timing of the high level of the signal B.

The BRM encoder 260 encodes the count value of the counter 270 at the high level timing of TB, and outputs an m-bit encoded signal to the selection circuit 320.
The selection circuit 320 selects the output value of the buffer circuit 190 while the timing signal 211 is at a low level, and selects the output value of the BRM enhancer 260 while the timing signal 211 is at a high level and outputs it to the conveyor register block 150.

Next, before explaining the operation of this embodiment, combinations of the number of output channels of the PWM signal and the BRM pulse-added PWM signal that can be outputted will be explained with reference to the corresponding diagram in FIG.

The number of output channels for the PWM signal and the BRM pulse added PWM signal is specified by setting the mode register 300. The PWM signal is generated by a coincidence signal output from one conveyor register, and the BRM pulse-added PWM signal is generated by a coincidence signal output from two conveyor registers.

In FIG. 11, a combination of each bit setting value of the mode register 300 and the number of output channels is shown for each match signal pair output by the two conveyor registers in the conveyor register block 150 of this embodiment.

As shown in FIG.
By setting 0'', a maximum of 6 channels of PWM signals can be obtained, and by setting ``111'', a maximum of 3 channels of BRM pulse-added PWM signals can be obtained. Also, by setting any 2 bits to "1", 2 channels of PWM signals and 2 channels of BRM pulse-added PWM signals can be obtained, and by setting any 1 bit to "1", 4 channels of PWM signals can be obtained. A PWM signal and a PWM signal with one channel of BRM pulse added are obtained.

Therefore, by setting the mode register 300, the number of output channels of the PWM signal and the high-resolution or RM pulse-added PWM signal can be specified as an arbitrary combination, increasing versatility in the application of a multi-channel PWM signal generator with BRM.

The CAM cell of this embodiment is the same as that shown in FIG.
By arranging AM cells in a row and column structure and outputting data discrimination outputs C in parallel, a conveyor register 151 to a conveyor register 156 capable of determining content as a word is realized.

FIG. 12 shows the conveyor register block 150 of FIG.
It is an element arrangement diagram in a. B here. Bs corresponds to the Oth bit to the third bit of the conveyor register, and each conveyor register has a 4-bit configuration. In this register block, 1 of the CAM cell array
A row corresponds to one conveyor register, and a match signal of 16
1 to 166 indicate the same signals as in FIG. 10, and six transistors T31 to T36 are used.

Next, since the circuit configuration and operation for generating the PWM signal and the BRM pulse-added PWM signal are the same for each bit of the mode register 300, "0" and "1" are set in the 0th bit. The case where this is set will be explained.

First, the circuit configuration of the pulse control circuit 310 will be explained in the 13th section.
This will be explained using figures. This pulse control circuit 310 is composed of pulse control blocks 311 to 316 and a timing control signal generation block 317. The timing control signal generation block 317 uses the timing signal 201 to generate and output a signal that controls the timing of setting and resetting the main pulse of the PWM signal common to all pulse control blocks. The timing control signal generation block 317 consists of D flip-flops 75 and 76 and an inverter 55, and the D flip-flop 75 receives the timing signal 2.
01 is input, the input signal is latched at the rising edge of TB, and outputted to D-flip and flip-flop 76.
5, the D flip-flop 750 outputs an inverted signal to all pulse control blocks 311 to 316, and the D flip-flop 76 latches the input signal at the rising edge of TA and outputs it to all pulse control blocks.

The pulse control blocks 311 to 313 are circuit blocks with the same configuration that generate a PWM signal or a BRM pulse added PWM signal, and are connected to the inverters 51 to 53 and an OR game.
61, 62, NAND gates 64, 65, AND gate 59, and D flip-flops 71, 72.

The inverter 51 inputs the coincidence signal 161 and outputs an inverted signal to the NAND gate 64, and the OR gate 61
inputs the output of the D flip-flop 72 and the output of the D flip-flop 76, and sends the OR signal to the NAND gate 6.
Output for 4.

The NAND gate 64 inputs the output signal of the OR gate 61, the output signal of the inverter 51, and the output signal of the inverter 55, and outputs an inverted signal of the AND signal to the NAND gate 65. AND gate 59 receives match signal 164
and the output signal of the O-th bit of the mode register 300, and outputs an AND signal to the inverter 52, which inputs the output signal of the AND gate 59,
The inverted signal is output to the OR gate 62, the OR gate 62 inputs the output signal of the inverter 52 and the output signal of the inverter 55, and outputs a logical sum signal to the NAND gate 65-. The NAND gate 65 receives the output of the NAND gate 64 and the output of the OR gate 62, and outputs an inverted signal of the AND signal to the D flip-flop 71.

The D flip-flop 75 receives the output signal of the NAND gate 65, latches the input signal at the rising edge of TB, and outputs it to the D flip-flop 72. The D flip-flop 72 receives the output signal of the D flip-flop 71, latches the input signal at the rising edge of TA, and outputs it to the OR gate 61.

The inverter 53 receives the output signal of the 0th bit of the address register 300 and outputs an inverted signal to the pulse control block 314. Also, the pulse control block 31
4 to 316 are circuit blocks that generate PWM signals, and have the same circuit configuration. The pulse control block 314 includes an inverter 54, 56, an OR gate 63, and a NAN
It is composed of a D gate 66 and D flip-flops 73 and 74.

The inverter 54 inputs the match signal 164 and outputs its inverted signal to the NAND gate 66, and the OR gate 63 inputs the output of the D flip-flop 74 and the output of the D flip-flop 76, and outputs the logical sum signal to the NAND gate. 66. The NAND gate 66 inputs the output signal of the OR gate 63, the output signal of the inverter 54, and the output signal of the inverter 55, and outputs an inverted signal of the AND signal to the inverter 56.
The output signal of the AND gate 66 is inputted, and an inverted signal is outputted to the flip-flop and differential 3.

The D flip-flop 73 inputs the output signal of the inverter 56, latches the input signal at the rising edge of TB, and outputs the D flip-flop 73.
It is output to the flip-flop 74. The D flip-flop, differential 4, inputs the output signal of the D flip-flop 73, latches the input signal at the rising edge of TA, and outputs it to the OR gate 63.

Next, the PWM signal will be explained with reference to the timing diagram of FIG. 14, focusing on the operation of the pulse control circuit 310. In this timing diagram, the Oth bit of the mode register 300 is set to "O", and the conveyor register 151 is set to "O".
13 is a timing chart showing the output operation of the PWM signal when "n"2"'-1" is set, and also shows each signal of the pulse control circuit 310 of FIG. 13.

In particular, the conveyor register 15 configured by CAM cells
1 shows a count cycle in which a match between a comparison value and a count value of the counter 200 is detected by a comparison operation of No. 1.

In order to operate the multi-channel PWM signal generator with BRM of this embodiment, first, the CPU10L is set to the memory 10 in advance.
By fetching, decoding, and executing the instruction stored in 2, the comparison value, control information, and set value are transferred to the conveyor register 151, operation control register 111, and mode register 300 via the internal data bus 100. Set each data. Data setting operations for the operation control register 111 and mode register 300 are performed by the CPU 10.
C at the high level timing of TA by executing instruction 1.
This is done by the PU 101 writing each data via the internal data bus 100.

The operation of setting the comparison value for the conveyor register 151 is as follows:
The CPU 101 operates the buffer circuit 130 at the high level timing of TA to take in the comparison value placed on the internal data bus 100 by executing the instruction of the CPU10I, and at the same time actively tosses the selection signal 121 outputted by the operation control unit 110. This is done by selecting the conveyor register 151 and latching the output of the buffer circuit 130.

The operation control unit 110 controls the operation of the counter and the reference clock signal 12 based on the operation designation information of the operation control register 111.
7 is selected, an operation control signal is generated, and at the same time, the counters 200 and 270 are cleared by the clear signal 120, and then the counting operation of the counter 200 is started.

The comparison operation between the counted value of the counter 200 and the set value of the conveyor register 151 is performed when the selection circuit 320 selects the buffer circuit 190 while the timing signal 201 is at a low level.
This is done by selecting the output value of , and outputting the count value of the counter 200 buffered by the buffer circuit 190 to the conveyor register block 150 at the timing when TB is at high level. If these match, the conveyor register 151 outputs a match signal 161 to the pulse control circuit 310.

That is, the multi-channel BRM pulsed PW of this embodiment
The M signal generator generates a signal from the CPU 1 during each level period of the CPU stage signal 128 and comparison stage signal 129, which are obtained by dividing the count cycle of the counter 200.
The data setting operation of 01 and the counting operation and comparison operation of the counter 200 are performed in a time-division manner.

The output signal 171 when the comparison value "n" is set in the conveyor register 151 will be explained. Here, the value of n'' is assumed to be 0<n<2''-1. mode register 30
Since the Oth bit of 0 is set to “0”, the control signal 303 is at a low level, and therefore the OR gate 631
The output is fixed at high level. When the stored value of the counter 200 is "23-1", the timing signal 201 becomes high level in synchronization with the rising edge of TH. When the timing signal 201 falls, the output of the inverter 55 goes high in synchronization with the rising edge of TB.

Further, since the output signal of the D flip-flop 76 is at a high level in the Tl comparison stage shown in FIG. 14, the output of the OR gate 81 is at a high level. Here, since the output signal of the D flip-flop 75 is low level, the output signal of the inverter 55 is high level, and the match signal 161 is low level, so the output of the NAND gate 64 is low level, as shown in FIG. At the comparison stage of Tl, the output of the NAND gate 65 becomes high level. Therefore, the D flip-flop 71 in the next stage is the T of the comparison stage T1 shown in FIG.
The output signal 17 is latched to a low level at the rising edge of B, and therefore the output signal 17 becomes high level in synchronization with the rising edge of TB of T1 shown in FIG.

Next, when the counter 200 counts up and stores n'', the coincidence signal 161 goes to a low level in synchronization with the rising edge of TB in the comparison stage T2 shown in FIG. .

Therefore, the output of inverter 51 in FIG. 13 becomes low level, and the output of NAND gate 64 becomes low level, so that the output of NAND gate 65 becomes low level. The D flip-flop 71 latches a low level in synchronization with the rising edge of TB at T2 shown in FIG. Therefore, the output signal 171 is T of TD shown in FIG.
It becomes low level in synchronization with the rise of B. By repeating this operation, the duty ratio (('-)X100)(
%) is output as the output signal 171.

Next, a case will be explained in which 0'' is set in the conveyor register 151. In this case, when the timing signal 201 falls in synchronization with the rising edge of TB of T1 shown in FIG. 161 is at a high level, the output of the NAND gate 64 shown in FIG. 13 is fixed at a high level.
Since the output of is fixed at high level, NAND gate 65
The output becomes low level, and the D flip-flop 71 latches the low level in synchronization with the rising edge of TB of T1 shown in FIG.

Therefore, the output signal 171 remains at a low level and does not change.
Outputs a PWM signal with a duty ratio of 0%.

Next, a case where "21-1" is set in the conveyor register 151 will be described. The operation of setting the output signal 1710 in the comparison stage of the TI shown in FIG. 14 is the same as when "n" is set in the conveyor register 151, so a description thereof will be omitted.

In synchronization with the rising edge of TB in the comparison stage T3 shown in FIG. 14, the match signal 181 and timing signal 201 simultaneously go to a low level, and the output of the NAND gate 64 shown in FIG. 13 goes to a high level. Become. Here, since the output of the OR gate 62 is fixed at a high level, the output of the NAND gate 65 becomes a low level, and the D flip-flop 71 latches the low level in synchronization with the rising edge of TB of T3 shown in FIG. Therefore, the output signal 171 becomes low level.

By repeating this operation, the duty ratio ((-L-
L)X100)(%) PWM pulse output signal 171
Output as .

As shown above, by changing the comparison value set in the conveyor register 51, it is possible to output PWM signals having various duty ratios with a resolution of 1.

Also, O of the pulse control block 311 shown in FIG.
The output of the R gate 62 is fixed at a high level because the Oth bit of the mode register 300 is "0" and the control signal 303 is at a low level.

Therefore, the inverter 56 of the pulse control block 314 operates logically the same as the NAND gate 65 of the pulse control block 311. That is, since the control signal 303 is at a low level and one input of the AND gate 60 is always at a high level, the output of the D flip-flop 73 is outputted as the output signal 254. Therefore, the pulse control circuit 314 is activated by the coincidence signal 164.
1, and outputs a PWM pulse as an output signal 254.

Note that the comparison operation of the pulse control circuit 311 is the same for all pulse control circuits, and since the six conveyor registers of the conveyor register block 150 have a CAM cell configuration, they can be compared simultaneously at the comparison stage. It is.

Therefore, by setting "000B" in the mode register 300 and setting different comparison values in each conveyor register, it is possible to simultaneously output up to six channels of PWM signals with different duty ratios.

Next, the operation of outputting the BRM pulse-added PWM signal by setting the 0th bit of the mode register 300 to "1" will be described.

Maf, the BRM encoder 260 is connected to the conveyor register 1
Encode signal output to 54 and counter 200
The correspondence table with the counted values is the same as Table 2. in this case,
Lower 221 of conveyor register is conveyor register 15
4, the match signal 231 may be set as the match signal 164, and each bit of the conveyor register 154 is BQ from the least significant bit.

Bay B2. It is expressed in Bs. Drunkenness, drunkenness, drunkenness.

B6 is the same value or an inverted value, and is an input signal for performing a comparison operation on the data stored in the CAM cell. A combination of these input values allows comparison of each bit of the conveyor register 154. As shown in this table, “Ba 1 ton (0≦n≦3) is “1” “1”
'', the data stored in the conveyor register 154 is excluded from the comparison, and when the value is ``0'', the data stored in the conveyor register 154 is
It is compared whether the stored data of the n-th bit of No. 54 is "l" or not.

Therefore, if multiple bits of the comparison value set in the conveyor register 154 have a logical value of "1", a match signal 164 is output, which is the logical sum of each match signal, as shown in the above-mentioned logical formula. Ru. Next, BRM pulse addition P
The timing for setting and resetting the PWM signal main pulse and the timing for determining whether to add a B'RM pulse when the WM signal is generated will be explained.

FIG. 15 is a circuit diagram of the selection circuit 320 in FIG. 10,
B from the least significant bit. It is shown as a 4-bit configuration represented by ~B. This selection circuit 320 is composed of an inverter 57, 16 AND gates A1 to A1.7, and eight OR gates A20 to A27.

The inverter 57 receives the timing signal 201 and outputs an inverted signal. The eight AND gates (AND game) A10 to A17 input the output of the BRM encoder 260 and the timing signal 201, and send the AND signal for each bit to the eight OR gates (OR game) ADO to A27. and output it. 8 AND gates A1~AIH-!
,, the output of the buffer circuit 190 and the timing signal 201
A 0-reverse signal is input, and an AND signal for each bit is output to eight OR gates A20 to A27.

Next, the selection timing of the selection circuit 320 will be explained.

Here, since the operation for each bit is the same, the explanation will focus only on B3 of the two input values forming the third bit formed by the AND gate AI, AND gate A10, and OR gate A20. When the timing signal 201 is at a high level and TB is at a high level, the output of the AND game) AIO becomes the output value of the BRM encoder 260.

At this time, the output value of the AND gate (AI) becomes a low level because the inverted signal of the timing signal 201 is input, and therefore, the output value of the BRM encoder 260 is outputted as the output of the OR gate A20.

When the timing signal 201 is at a low level and TB is at a high level, the output of the OR gate 20 will be:
The output value of buffer circuit 190 is output. Therefore, according to the timing shown above, the selection circuit 320 selects the BRM
The output value of the encoder 260 or the output value of the buffer circuit 190 is selected, and the output value is transferred to the conveyor register block 150 in a time-sharing manner.
supply for. That is, the counter 200 changes from “on” to “
PW for each comparison stage during the counting period up to 2'''-2''
The M signal main pulse is determined and the counter 200 is “2”.
In the comparison stage that stores the count value of "-1", B
An additional pulse determination is made as to whether or not to add an RM pulse. As a result, the BRM for the main pulse of the PWM signal
Addition control of pulses becomes possible.

Next, the 0th bit of the mode register 300 is set to “1”, and the comparison value of the conveyor register 151 is set to “2”-3.
and set the comparison value of the conveyor register 154 to "0".
The operation of the BRM pulse-added PWM signal when set to "OOOB" and "100OB" will be explained.

FIG. 16 is a timing diagram showing the operation of adding 81M pulses to the PWM signal main pulse, and shows the operation of adding 81M pulses to the PWM signal main pulse.
Each signal is shown at the main pulse determination timing and the additional pulse determination timing when the count value of 0 is "5" and "6".

Mode register 3 is used to determine the main pulse of PWMM.
Since the case where the Oth bit of 00 is set to "0" has been explained, the following will mainly explain the addition control of the BRM pulse.

Here, the BRM pulse-added PWM signal is obtained as the output signal 171 of the pulse control block 311 because the O-th bit of the mode register 300 in FIG. 10 is set to 1"1" and the control signal 303 is at a high level. It will be done.

At this time, the output signal 174 of the pulse control block 314 is fixed at a low level, and output of the PWM signal is prohibited.

In the main pulse determination period of T1 shown in FIG.
The output signal 171 becomes a low level when the count value "O" of the counter 200 is stored, and becomes a low level in synchronization with the rising edge of the coincidence signal 161 output when the count value "812y-3" is stored. During the additional pulse determination period of T2 shown in FIG. 13, the output of the inverter 55 shown in FIG. By being
The output of the inverter 52 becomes high level.

Therefore, the output of the OR gate 62 becomes high level, and N
The output of AND gate 65 becomes low level. Since the D flip-flop 71 latches and outputs a low level during the period T2 shown in FIG. 16, the output signal 171 continues to be low level during the additional pulse determination period.

Next, a case where "1000B" is set in the conveyor register 154 will be explained. Regarding the operation of the output signal 251 during the main pulse determination period of T1, 0000B''
This is the same as setting . In the first half (comparison stage) of the additional pulse determination period T2, the coincidence signal 164 becomes high level. At this time, since the output of the inverter 55 in FIG. 13 is at a low level, the output of the NAND gate 64 is at a high level, and since the control signal 303 is at a high level, the output of the OR gate 62 is at a low level. The output of gate 65 becomes high level. Therefore, the D flip-flop 71 latches a high level during the period T2 shown in FIG. 16, and the output signal 171 becomes a high level. In other words, the timing of adding 81M pulses (when the count value of the counter 270 is “
The PWM signal is stretched by adding 81M pulses corresponding to one output cycle of the counter 200 to the first part of the PWM signal output at the next timing (5"). Therefore, the BRM encoder 260
Conveyor register 15 at each timing determined by
If the corresponding bit of the comparison value set to 4 is "1", the output signal 251 will be expanded.

The counter 200 has m bits, the counter 270 has 2 bits, and the set value of the conveyor register 151 is n.

When the set value of the conveyor register 154 is k, the duty ratio ((-) + (-J)) X1002
It has the same effect as generating a 2×2 (%) PWM signal.

By setting "111" in the mode register 300, up to 3 channels of BRM pulse added PWM
It is possible to output a signal, that is, a highly accurate PWM signal. Therefore, based on the value set in the mode register 300, a high-precision PWM signal and 81M pulses are added.
It becomes possible to output the M signal on any number of channels.

The multi-channel PWM signal generator with BRM pulses of this embodiment has a single CAM cell array constituting a conveyor register block and a selection circuit, and the selection circuit selects the output of the BRM encoder at the timing of determining the addition of 81M pulses. To form a highly versatile multi-channel PWM signal generator with BRM pulses that can simultaneously output a plurality of PWM signals with different resolutions and with any number of channels by supplying them to a single CAM cell array. becomes possible.

〔Effect of the invention〕

As explained above, the present invention provides a conveyor register array in which a PWM signal generating cono comparator conveyor register is configured as an array of memory elements (CAM cells) having a comparison function, thereby increasing the number of constituent elements on one chip. This has the advantage that a multi-channel PWM signal generator can be obtained which reduces the amount of hardware, reduces the amount of hardware, and keeps costs low.

[Brief explanation of drawings]

FIG. 1 is a block diagram of the first embodiment of the present invention, FIG. 2 is a circuit diagram of a CAM cell configuring the conveyor register of FIG. 1, and FIG. 3 is a circuit diagram of the first buffer circuit 130 of FIG. Second
4 is an operation timing diagram of the embodiment of FIG. 1, FIG. 5 is a block diagram of the second embodiment of the present invention, and FIG. Fig. 5 is a timing diagram of the match signal output operation of the conveyor register block, and Fig. 7 is the BRM shown in Fig. 5.
A circuit diagram of the encoder, FIG. 8 is a circuit diagram of the pulse control circuit 6300 of FIG. 5, FIG. 9 is an operation timing diagram of the embodiment of FIG. 5, and FIG. 10 is a block diagram of the third embodiment of the present invention. , FIG. 11 is a diagram showing how the setting values of the mode register 130 in FIG. 10 correspond to the number of output channels of the multi-channel BRM equipped PWM signal generator of this embodiment, and FIG. 12 shows the elements of the conveyor register block 150 in FIG. 10. 13 is a circuit diagram of the pulse control circuit 170 in FIG. 10, FIG. 14 is a timing diagram showing the PWM signal generation operation in FIG. 10, and FIG. 15 is a circuit diagram of the selection circuit 180 in FIG. 10. Figure, 1st
FIG. 6 is a timing diagram showing the generation operation of the BRM pulse-added PWM signal of FIG. 10. ■, ~Eng. , 21~23.51~56.57...
...Inverter, T11-T47...Transistor, 24-26.64-66...Nands gate, 30-33...RS latch, 34-37,
59,60°A1 to A17...and gate,
38~41°71~76...D flip □tub, 42~45°61~63. A20-A27...
...OR gate, 100...Internal data bus,
101...Central processing unit, 102...
Memory, 110... Operation control unit, 111...
...Operation control register, 120...Clear signal, 121-126...Selection signal, 127...
...Reference clock signal, 128...CPU
Stage signal, 129... Comparison stage signal,
130,190°210...Buffer circuit, 1
41-144...Selection signal, 150,220.
...Conveyor register block, 151-156
...Conveyor register, 161-166.23
1-234... Match signal, 171-174...
...RSS flip flow rough, 181-184,2
51~256... Output signal, 200°270.
... Counter, 201 ... Overflow signal, 221 to 224 ... Conveyor register (lower), 240, 310 ... Pulse control circuit, 260 ... ...BRM encoder, 300...
...Mode register, 301-303...Control signal, 320...Selection circuit, 311-316
...Pulse control block, 317...
Timing control signal block.

Claims (2)

[Claims] (1) A pulse generator that outputs a predetermined clock, a counter that counts the output of the pulse generator, and a register that stores a comparison value that defines the pulse width of the pulse width modulation signal;
In a multi-channel pulse width modulation signal generator that outputs a plurality of pulse width modulation signals, each channel is provided with a comparator that compares the stored values of the plurality of registers and the count value of the counter, and A multi-channel pulse width modulation signal generator, characterized in that each comparator is constituted by an array of CAM cells which are memory elements having a comparison function and which are addressable according to their contents. (2) The multi-channel pulse width modulation signal generator according to claim (1), wherein the buffer circuit of the counter includes a binary rate multiplier encoder that performs pulse integration of multiple periods.