JPH0363192U - - Google Patents
Info
- Publication number
- JPH0363192U JPH0363192U JP12418489U JP12418489U JPH0363192U JP H0363192 U JPH0363192 U JP H0363192U JP 12418489 U JP12418489 U JP 12418489U JP 12418489 U JP12418489 U JP 12418489U JP H0363192 U JPH0363192 U JP H0363192U
- Authority
- JP
- Japan
- Prior art keywords
- attribute
- generating means
- data
- generating
- character
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 3
- 230000007274 generation of a signal involved in cell-cell signaling Effects 0.000 description 2
Landscapes
- Digital Computer Display Output (AREA)
Description
第１図は本考案に係る表示制御装置を適用した
システムの一実施例のブロツク図、第２図は第１
図のアトリビユートＲＡＭ制御部の構成例を示す
図、第３図は第１図のアトリビユートラツチ部の
構成例を示す図である。
１……表示制御装置、２……基本信号発生回路
、３……表示装置制御部、４……アドレスカウン
タ、５……マルチプレクサ、６……レシーバ／ド
ライバ部、７……キヤラクタジエネレータ、８…
…コードＲＡＭ、９……コードＲＡＭ制御部、１
０……コードラツチ部、１１……マルチプレクサ
、１２……キヤラクタジエネレータ制御部、１３
……ラツチ回路、１４……パラレル／シリアル交
換部、１５……アトリビユートＲＡＭ、１６……
アトリビユートＲＡＭ制御部、１７……アトリビ
ユートラツチ部、１８……属性付加回路、１９…
…データ変換部、２０……モードレジスタ、３０
……制御信号発生回路、３１……ゲート回路、４
０……ラツチ回路、４１……レジスタ、４２……
マルチプレクサ、５０……マイクロプロセツサユ
ニツト、５１……表示装置。
FIG. 1 is a block diagram of an embodiment of a system to which a display control device according to the present invention is applied, and FIG.
FIG. 3 is a diagram showing an example of the configuration of the attribute RAM control section shown in FIG. 1, and FIG. 3 is a diagram showing an example of the configuration of the attribute latch section shown in FIG. DESCRIPTION OF SYMBOLS 1...Display control device, 2...Basic signal generation circuit, 3...Display device control section, 4...Address counter, 5...Multiplexer, 6...Receiver/driver section, 7...Character generator, 8...
...Code RAM, 9...Code RAM control section, 1
0... Code latch unit, 11... Multiplexer, 12... Character generator control unit, 13
... Latch circuit, 14 ... Parallel/serial exchange section, 15 ... Attribute RAM, 16 ...
Attribute RAM control unit, 17... Attribute latch unit, 18... Attribute addition circuit, 19...
...Data converter, 20...Mode register, 30
... Control signal generation circuit, 31 ... Gate circuit, 4
0...Latch circuit, 41...Register, 42...
Multiplexer, 50...Microprocessor unit, 51...Display device.
Claims (1)
段と、該キヤラクタデータを修飾するアトリビユ
ートデータを発生するアトリビユート発生手段と
を有し、前記アトリビユート発生手段は、アトリ
ビユートデータを記憶する記憶部の読出しを行な
つてアトリビユートデータを発生させるか、前記
記憶部の読出しを停止してある一定のアトリビユ
ートデータを発生させるかをモードに従つて選択
するようになつていることを特徴とする表示制御
装置。 The attribute generating means has a character generating means for generating character data, and an attribute generating means for generating attribute data modifying the character data, and the attribute generating means is configured to read out a storage section that stores the attribute data. According to the mode, it is possible to select whether to generate attribute data by performing the above operation or to generate a certain attribute data by stopping reading of the storage section. Display control device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12418489U JPH0363192U (en) | 1989-10-24 | 1989-10-24 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12418489U JPH0363192U (en) | 1989-10-24 | 1989-10-24 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0363192U true JPH0363192U (en) | 1991-06-20 |
Family
ID=31672122
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP12418489U Pending JPH0363192U (en) | 1989-10-24 | 1989-10-24 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0363192U (en) |
-
1989
- 1989-10-24 JP JP12418489U patent/JPH0363192U/ja active Pending
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