JPH0362960A - Terminal pin for semiconductor chip carrier - Google Patents
Terminal pin for semiconductor chip carrierInfo
- Publication number
- JPH0362960A JPH0362960A JP19883289A JP19883289A JPH0362960A JP H0362960 A JPH0362960 A JP H0362960A JP 19883289 A JP19883289 A JP 19883289A JP 19883289 A JP19883289 A JP 19883289A JP H0362960 A JPH0362960 A JP H0362960A
- Authority
- JP
- Japan
- Prior art keywords
- solder
- terminal pin
- semiconductor chip
- pga
- chip carrier
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 16
- 229910000679 solder Inorganic materials 0.000 claims abstract description 24
- 238000007747 plating Methods 0.000 claims description 10
- 239000010953 base metal Substances 0.000 claims description 2
- 239000000463 material Substances 0.000 abstract description 10
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 abstract description 5
- 229910052802 copper Inorganic materials 0.000 abstract description 5
- 239000010949 copper Substances 0.000 abstract description 5
- 229910045601 alloy Inorganic materials 0.000 abstract description 4
- 239000000956 alloy Substances 0.000 abstract description 4
- 239000003822 epoxy resin Substances 0.000 abstract description 2
- 239000004744 fabric Substances 0.000 abstract description 2
- 229920000647 polyepoxide Polymers 0.000 abstract description 2
- 229910052718 tin Inorganic materials 0.000 abstract 2
- UGKDIUIOSMUOAW-UHFFFAOYSA-N iron nickel Chemical compound [Fe].[Ni] UGKDIUIOSMUOAW-UHFFFAOYSA-N 0.000 abstract 1
- 229910052751 metal Inorganic materials 0.000 abstract 1
- 239000002184 metal Substances 0.000 abstract 1
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 10
- 238000005476 soldering Methods 0.000 description 8
- 229910052759 nickel Inorganic materials 0.000 description 5
- 229910001030 Iron–nickel alloy Inorganic materials 0.000 description 3
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 3
- 239000000969 carrier Substances 0.000 description 3
- 229910000833 kovar Inorganic materials 0.000 description 3
- 238000000034 method Methods 0.000 description 3
- 229910000906 Bronze Inorganic materials 0.000 description 2
- XEEYBQQBJWHFJM-UHFFFAOYSA-N Iron Chemical compound [Fe] XEEYBQQBJWHFJM-UHFFFAOYSA-N 0.000 description 2
- 239000010974 bronze Substances 0.000 description 2
- 230000000052 comparative effect Effects 0.000 description 2
- KUNSUQLRTQLHQQ-UHFFFAOYSA-N copper tin Chemical compound [Cu].[Sn] KUNSUQLRTQLHQQ-UHFFFAOYSA-N 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 229910000881 Cu alloy Inorganic materials 0.000 description 1
- 101100474383 Escherichia coli (strain K12) rpsO gene Proteins 0.000 description 1
- 238000005253 cladding Methods 0.000 description 1
- 238000007598 dipping method Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 238000007654 immersion Methods 0.000 description 1
- 229910052742 iron Inorganic materials 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 230000002265 prevention Effects 0.000 description 1
Landscapes
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
この発明は、半導体素子搭載用の半導体チップキャリア
用端子ピンに関するものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a terminal pin for a semiconductor chip carrier for mounting a semiconductor element.
近年、半導体チップの高機能、高集積化にともなうＩ１
０数の増加に対応してより汎用な半導体チップキャリア
として、プリント配線板のスルホールに端子ピンを挿入
したビングリッドアレイ（以下、ＰＧＡと記述する）が
開発、利用されてきている。In recent years, as semiconductor chips have become more sophisticated and highly integrated, I1
In response to the increase in the number of zeros, a bin grid array (hereinafter referred to as PGA), in which terminal pins are inserted into through holes of a printed wiring board, has been developed and used as a more general-purpose semiconductor chip carrier.
従来、これらのＰＧＡの端子ピンは、銅系合金、鉄−ニ
ッケル系合金を母材とし、その表面に２〜４μ−の厚み
の銅やニッケルの下地メッキ層を形成し、さらに、その
上に１〜１０μ−の半田メッキ層を形成したものが使用
されていた。したがって、端子ピンの酸化防止や半田付
けの濡れ性は良好なものであった。しかしながら、この
端子ピンを使った半導体チップキャリアを高温高湿の雰
囲気下で処理するプレッシャークツカーテスト（以下、
ＰＣＴと記述する）などを行った後に半田付けをおこな
う場合、半田の濡れ性が悪くなり、この半導体チップキ
ャリアの端子ピンをマザーボードのスルホールに挿入し
半田付けで実装した場合に、半田付けが十分確実に行え
ないので導通性と接合強度が低下する問題を生じるので
ある。このことは、半導体チップキャリアが高温高湿の
雰囲気下に放置された場合にも当てはまる現象であり、
特に高信頼性を要求する半導体チップキャリアやマザー
ボードに高密度実装する半導体チップキャリアにおいて
は解決しなければならない問題である。Conventionally, these PGA terminal pins have been made of a copper alloy or iron-nickel alloy as a base material, with a base plating layer of copper or nickel having a thickness of 2 to 4 μm formed on the surface, and then Those with a solder plating layer of 1 to 10 microns were used. Therefore, the oxidation prevention of the terminal pins and the soldering wettability were good. However, there is a pressure test (hereinafter referred to as "pressure tester") in which semiconductor chip carriers using these terminal pins are processed in a high temperature and high humidity atmosphere.
If soldering is performed after soldering (described as PCT), the wettability of the solder will be poor, and if the terminal pins of this semiconductor chip carrier are inserted into the through-holes of the motherboard and mounted by soldering, the soldering may not be sufficient. Since this cannot be done reliably, the problem arises that the conductivity and bonding strength are reduced. This phenomenon also applies when a semiconductor chip carrier is left in a high temperature and high humidity atmosphere.
This is a problem that must be solved especially in semiconductor chip carriers that require high reliability and semiconductor chip carriers that are mounted in high density on motherboards.
半導体チップキャリアの端子ピンを高温高湿の雰囲気下
で処理しても、半田の濡れ性が良好な端子ピンを提供す
ることにある。To provide a terminal pin of a semiconductor chip carrier with good solder wettability even when the terminal pin is processed in a high temperature and high humidity atmosphere.
本発明は、前記課題を解決するために半導体チップキャ
リア用端子ピンにおいて、母材金属の表面に半田メッキ
層が直接形成されてなることを特徴とする半導体チップ
キャリア用端子ピンを提供するもので、母材の表面に直
接施されていた下地メッキの銅やニッケルが半田濡れ性
を阻害することを見出し、本発明に至った。In order to solve the above problems, the present invention provides a terminal pin for a semiconductor chip carrier, characterized in that a solder plating layer is directly formed on the surface of a base metal. discovered that copper and nickel in the base plating directly applied to the surface of the base material inhibited solder wettability, leading to the present invention.
以下この発明について詳しく説明する。This invention will be explained in detail below.
端子ピンの母材としては、銅系合金（リン青ｗ４）鉄−
ニッケル系合金（コバール、４２７０イ）等−ｆｌｌＱ
に使用される合金の線状物、板状物などを加工して用い
ることができる。これらの端子ピン母材にＳ ｎ ／
Ｐ ｂが６３／３７や９０／１０など一般に使用される
半田を用いて半田メッキ処理を直接施しメッキ厚み１〜
１０μ−形成したものである。The base material for the terminal pin is copper-based alloy (phosphor blue W4) iron.
Nickel-based alloys (Kovar, 4270i), etc. - fllQ
It can be used by processing wires, plates, etc. of alloys used in S n /
Pb is directly solder plated using commonly used solder such as 63/37 or 90/10 to achieve a plating thickness of 1~
10 μm.
実施例 １
鉄−ニッケル系合金（コバール）母材で、形状がφ０．
５ｍｍ、長さ５．８ｍｍで、その表面にＳｎ／Ｐｂが
９０／１０の半田メッキを１．５μｍの厚みに施した端
子ピンを１．６Ｍの板厚のガラス布基材エポキシ樹脂両
面銅張り積層板から作られたＰＧＡ用のプリント配線板
のメッキされたスルホールに挿入し、このものをＳ ｎ
／ Ｐ ｂが６３／３７の半田を溶融した半田浴槽を
用い半田浴温度２５０°Ｃ１浸漬時間２秒、引上げ速度
７０ｔｍ／ｓｅｃの条件で半田付けを行い１２０ビンの
ＰＧＡを得た０次に、このＰＧＡを、１７５°Ｃで１２
時間の高温保存処理しさらに、１２１℃で８時間ＰＣＴ
処理した後、半田濡れ性の試験として、Ｓ ｎ ／ Ｐ
ｂが６３７３７の半田を溶融した半田浴槽を用い半田
浴温度２１０’Ｃ，浸漬時間１秒、引上げ速度９０ｍｍ
／ｓｅＣの条件で半田付けを行い、この後に端子ピンの
表面を顕微鏡で観察し、半田に濡れた面積の割合で半田
の濡れ性を評価し、その結果を第１表に示した。Example 1 The base material is iron-nickel alloy (Kovar), and the shape is φ0.
The terminal pin is 5mm long and 5.8mm long, and its surface is plated with 90/10 Sn/Pb solder to a thickness of 1.5μm.The terminal pin is made of glass cloth with a thickness of 1.6M, epoxy resin, and double-sided copper cladding. Insert it into the plated through hole of a PGA printed wiring board made from a laminate board, and insert this into the S n
Soldering was carried out using a solder bath containing melted solder with P b of 63/37 at a solder bath temperature of 250°C, a dipping time of 2 seconds, and a pulling speed of 70 tm/sec to obtain 120 bottles of PGA. This PGA was heated at 175°C for 12
After high temperature storage treatment for 8 hours, PCT at 121℃ for 8 hours.
After processing, as a test of solder wettability, S n / P
Using a solder bath containing melted solder with b of 63737, the solder bath temperature was 210'C, the immersion time was 1 second, and the pulling speed was 90 mm.
Soldering was carried out under the conditions of /secC, after which the surface of the terminal pin was observed under a microscope, and the wettability of the solder was evaluated based on the ratio of the area wetted by the solder.The results are shown in Table 1.
実施例 ２
実施例１の端子ピンの母材をリン青銅に変えた以外は実
施例１と同様に実施し、その結果を第１表に示した。Example 2 The same procedure as in Example 1 was carried out except that the base material of the terminal pin in Example 1 was changed to phosphor bronze, and the results are shown in Table 1.
比較例 １
実施例１の端子ピンの母材の鉄−ニッケル合金（コバー
ル）の表面に下地メッキとして２μ−厚みのニッケルメ
ッキを施したものに変えた以外は実施例１と同様に実施
し、その結果を第１表に示した。Comparative Example 1 The same procedure as in Example 1 was carried out, except that the surface of the iron-nickel alloy (Kovar) of the base material of the terminal pin in Example 1 was replaced with 2μ-thick nickel plating as the base plating. The results are shown in Table 1.
比較例 ２
実施例２の端子ピンの母材のリン青銅の表面に下地メッ
キとして２μｍ厚みのニッケルメッキを施したものに変
えた以外は実施例１と同様に実施し、その結果を第１表
に示した。Comparative Example 2 The same procedure as in Example 1 was conducted except that the surface of the phosphor bronze base material of the terminal pin in Example 2 was coated with 2 μm thick nickel plating as the base plating, and the results are shown in Table 1. It was shown to.
Ｃ以 下 余 白）
第１表
〔発明の効果］
本発明の端子ピンを有する半導体チップキャリアは、高
温高湿の雰囲気下で処理されたり、保存されても、半田
の濡れ性が良好な半導体チップキャリアであることから
、この半導体チップキャリアの端子ピンをマザーボード
のスルホールに挿入し、半田付けによって実装したもの
においても良好な導通性と接合強度がそれぞれ得られる
効果を有するのである。Table 1 [Effects of the Invention] The semiconductor chip carrier having the terminal pins of the present invention is a semiconductor chip carrier with good solder wettability even when processed or stored in a high temperature and high humidity atmosphere. Since it is a chip carrier, it has the effect of providing good conductivity and bonding strength even when the terminal pins of this semiconductor chip carrier are inserted into through-holes on the motherboard and mounted by soldering.
Claims (1)
金属の表面に半田メッキ層が直接形成されてなることを
特徴とする半導体チップキャリア用端子ピン。(1) A terminal pin for a semiconductor chip carrier, characterized in that a solder plating layer is directly formed on the surface of a base metal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19883289A JPH0362960A (en) | 1989-07-31 | 1989-07-31 | Terminal pin for semiconductor chip carrier |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19883289A JPH0362960A (en) | 1989-07-31 | 1989-07-31 | Terminal pin for semiconductor chip carrier |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0362960A true JPH0362960A (en) | 1991-03-19 |
Family
ID=16397661
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP19883289A Pending JPH0362960A (en) | 1989-07-31 | 1989-07-31 | Terminal pin for semiconductor chip carrier |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0362960A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8864536B2 (en) | 2012-05-03 | 2014-10-21 | International Business Machines Corporation | Implementing hybrid molded solder-embedded pin contacts and connectors |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6473654A (en) * | 1987-09-14 | 1989-03-17 | Matsushita Electric Works Ltd | Semiconductor package |
-
1989
- 1989-07-31 JP JP19883289A patent/JPH0362960A/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6473654A (en) * | 1987-09-14 | 1989-03-17 | Matsushita Electric Works Ltd | Semiconductor package |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8864536B2 (en) | 2012-05-03 | 2014-10-21 | International Business Machines Corporation | Implementing hybrid molded solder-embedded pin contacts and connectors |
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