JPH0362362A - Data demodulation circuit - Google Patents

Abstract

PURPOSE:To improve the immunity of crosstalk by detecting a zero cross point from an absolute value differentiated output, slicing a preceding differentiating output to the point at a prescribed level, controlling a gate circuit so as to output a pulse signal as a demodulation signal. CONSTITUTION:An input analog signal is full-wave-rectified and differentiated by a preamplifier circuit 1 an absolute value differentiating circuit 2 and a zero cross detection circuit 3 detects a zero cross point by a change of the absolute value differentiated output signal from the positive to the negative polarity. A level slice circuit 4 slices the differentiating output preceding to the zero cross point at a prescribed level and a gate circuit 5 outputs a pulse signal as a demodulation signal via a FF or the like based on the first zero cross signal between output signals of the circuit 4. The input analog signal is differentiated to suppress the low frequency component of crosstalk or the like and the zero cross point is detected as a cross point with a zero level at a predetermined tilt of the differentiating output signal by the absolute value differentiation. As a result, the effect of crosstalk is avoided and the immunity of crosstalk is enhanced.

Description

[Detailed Description of the Invention] [Summary] This invention relates to a data demodulation circuit that outputs a pulse signal corresponding to the peak point of an input analog signal, such as a reproduction signal of a magnetic disk device, as demodulated data, with improved crosstalk resistance. A data demodulation circuit that outputs a pulse corresponding to the peak point of an input analog signal with the aim of enabling high-density recording includes a pre-circuit for equalizing and amplifying the input analog signal; an absolute value differentiating circuit that differentiates the absolute value of the output signal of the circuit; a zero-crossing detection circuit that detects the zero-crossing point of the output signal of the absolute value differentiating circuit; and a side preceding the zero-crossing point of the output signal of the absolute value differentiating circuit. a level slicing circuit that slices the signal at a constant level, and a gate circuit that outputs a pulse signal as demodulated data based on a detection signal of the first zero crossing point from the zero crossing detection circuit between the output signals of the level slicing circuit. It was configured with the following.

[Industrial application field]

The present invention relates to a data demodulation circuit that outputs a pulse signal corresponding to a peak point of an input analog signal such as a reproduction signal of a magnetic disk device as demodulated data.

As the speed of computer systems increases, the capacity of magnetic disk devices used as external storage devices is increasing, and high-density recording is required in order to increase the size and capacity of external storage devices.

In order to increase the density, it is necessary to improve the recording density in the circumferential direction (BPI; bits per inch) and the recording density in the radial direction (BPI; bits per inch).
It is also necessary to improve TPI (rack per inch). When the radial recording density (TPI) is increased, the spacing between adjacent tracks becomes narrower, which causes a phenomenon in which the signal from the adjacent trunk is superimposed on the reproduced signal of the target track, so-called crosstalk, which significantly degrades the quality of the reproduced signal. As a result, the data error rate deteriorates.

Therefore, in order to achieve high-density recording, there is a need for a drive mechanism such as a magnetic head with less off-track, a magnetic head and recording medium with less crosstalk, and a data demodulation circuit that is less affected by crosstalk. .

[Conventional technology]

The data demodulation circuit in a conventional magnetic disk device is
For example, it has the configuration shown in FIG. 4, where 31 is a differential circuit, 32 is a level slice circuit, 33 is a zero-cross detection circuit, and 34 is a gate circuit. The reproduced signal from the magnetic head of the magnetic disk device is processed by a preamplifier, an automatic gain control amplifier, a waveform equalization circuit, and a waveform equalization circuit (not shown).
The noise component is suppressed by a low-pass filter or the like and has a predetermined amplitude, and then the differentiating circuit 31 and level slice circuit 3
2 is input.

If this input analog signal a is shown in FIG. 5(a), the signal differentiated by the differentiating circuit 31 is
The result is shown in tb) in the figure. Also, level slice circuit 3
2, input analog signal a is sliced at levels Ll, L
Since it is sliced by 2, +d) in Figure 5
An output signal d shown in is obtained. Also, zero cross detection circuit 3
3 detects the zero cross point ZC of the output signal of the differentiating circuit 31, and outputs the detection signal C shown in FIG. 5(C).

In that case, the signal indicated by NS at a position other than the zero-crossing point 2C of the differential output signal will change slightly around the zero level due to noise components, etc. This is a detection signal C that detects a point, and is unnecessary in data demodulation. Therefore, only the detection signal C of the zero crossing point within the period of the output signal d of the level slice circuit 32 is outputted from the gate circuit 34 as a pulse signal e, as shown in FIG. 5(e). .

Therefore, a pulse signal e corresponding to the peak point of the input analog signal is obtained, and demodulated data as shown in the figure can be obtained.

[Problem to be solved by the invention]

The differentiating circuit 31 emphasizes the high frequency range, and since the crosstalk between adjacent tracks has many low frequency components as mentioned above, even if the differentiating circuit 31 differentiates the crosstalk, there will be no crosstalk. There is hardly anything to emphasize.

However, signal components unrelated to the peak point of the input analog signal are transferred to the slice level L1. In the level slice circuit 32 for removing by L2, it is necessary to prevent crosstalk components from being included above the slice level. Therefore, as the crosstalk increases, the slice level Ll increases.

The setting range of L2 has become narrower, which is one of the obstacles to high-density recording.

The present invention aims to improve crosstalk resistance and enable high-density recording.

[Means for Solving the Problems] The data demodulation circuit of the present invention demodulates an analog signal such as a reproduction signal of a magnetic disk device while reducing the influence of crosstalk. explain.

A pre-circuit 1 that equalizes and amplifies an input analog signal, an absolute value differentiator 2 that differentiates the absolute value of the output signal of this pre-circuit 1, and a zero-cross point of the output signal of this absolute value differentiator 2 is detected. a level slicing circuit 4 that slices the output signal of the absolute value differentiating circuit 2 at a constant level on the side preceding the zero-crossing point; and a zero-crossing detection circuit between the output signals of the level slicing circuit 4. The gate circuit 5 outputs a pulse signal as demodulated data based on the detection signal of the first zero crossing point from 3.

[Effect]

The pre-circuit 1 is a pre-amplifier, an automatic gain amplifier.

It includes an equalization circuit, a low-pass filter, etc., and equalizes and amplifies the reproduction signal of the magnetic head, and its output signal is applied to the absolute value differentiator circuit 2. The absolute value differentiating circuit 2 can be realized with a configuration that performs full-wave rectification and differentiation of an analog signal. The zero-crossing detection circuit 3 detects the zero-crossing point of the differential output signal, for example, the zero-crossing point in the process of the differential output signal changing from positive polarity to negative polarity.

The level slice circuit 4 slices the side of the differential output signal preceding the zero-crossing point at a constant level, and detects the zero-crossing point in the process of changing from positive polarity to negative polarity as described above. If so, slice the positive polarity side. The gate circuit 5 outputs a pulse signal based on the detection signal of the first zero crossing point between the output signals of the level slice circuit 4. For example, between the output signals of the level slice circuit 4, By setting and resetting the flip-flop using the output signal, the output signal of the flip-flop becomes “1”.
, "O". Then, a pulse signal can be output at the rising edge of the detection signal at the first zero-crossing point in each section of 1'' and O''.

(Example) Examples of the present invention will be described in detail below with reference to the drawings.

FIG. 2 is a block diagram of an embodiment of the present invention, where 11 is a preamplifier, an automatic gain control amplifier 9, an equalization circuit, a low-pass filter, etc., and 12 is an absolute value circuit using full-wave rectification, etc. 13 is a zero cross detection circuit, and 14 is a level slice circuit. Also 15
, 16 is a flip-flop, 17 is a delay circuit (DL),
18 is an exclusive OR circuit, which constitutes the gate circuit in FIG.

FIG. 3 is an explanatory diagram of the operation. The input analog signal a is equalized and amplified and input to the absolute value differentiating circuit 12. In the case shown in (al) of FIG. 3, when the input analog signal a is differentiated by the absolute value differentiating circuit 12,
The differential output signal shown in is obtained. This differential output signal S is added to the zero cross detection circuit 13 and the level slice circuit 14, and when the zero cross detection circuit 13 detects a zero cross point ZC in the process of changing from positive polarity to negative polarity, for example, The detection signal C is shown in (C) in Figure 3.
It will be as shown below. In this case, as in the conventional example, detection signals of zero-crossing points other than the zero-crossing point zC are obtained due to noise components and the like.

Further, in the level slicing circuit 14, the side of the differential output signal preceding the zero crossing point ZC is sliced at a constant level L. In this case, since the side preceding the zero-crossing point is a differential output signal of positive polarity, it is sliced at the L level in FIG. 3(b). Therefore, its output signal d
is shown in FIG. 3(d).

In the clip-flop 16, the output signal d of the level slice circuit 14 is applied to the clock terminal C, the 0 terminal output signal is applied to the data terminal, and the Q@ child output signal e is applied to the third terminal C.
It is shown in (81) in the figure.

This Q terminal output signal e is applied to the data terminal of the flip-flop 15, and the detection signal C of the zero-cross detection circuit 13 is applied to its clock terminal C, so that the Q@ child output signal f of the flip-flop 15 is The result is shown in FIG. 3(f). That is, between the output signal d of the level slice circuit 14 and the Q@child output signal e of the flip-flop 16,
The first detection signal C of the zero cross detection circuit 13 in that period is detected as the rising and falling timing of the flip-flop 15, and the noise component is removed. That will happen.

The Q terminal output signal f of the flip-flop 15 is directly applied to the exclusive OR circuit 18, and is also applied to the exclusive OR circuit 1 through a delay circuit 17 with a delay time corresponding to the desired pulse width.
8, as shown in (gl) in Figure 3,
Pulse signal g corresponding to the peak point of input analog signal a
can be obtained.

In the present invention, the differential waveform of the input analog signal is used without using the original waveform, and low frequency components such as crosstalk are suppressed. Reduce the influence of talk,
Data can be demodulated. Furthermore, the gate circuit can of course have a configuration other than that of the above-described embodiment.

〔Effect of the invention〕

As explained above, the present invention includes a pre-circuit 1, an absolute value differentiator 2, a zero cross detection circuit 3, a level slice circuit 4, and a gate circuit 5, and provides a differentiated output signal of an analog signal by the absolute value differentiator 2. Based on this, it detects the zero-crossing point, slices the level preceding the zero-crossing point, and outputs a pulse signal as demodulated data using the detection signal of the first zero-crossing point between the sliced output signals. By differentiating the input analog signal, low frequency components such as crosstalk can be suppressed, and by differentiating the absolute value, the zero-crossing point is determined by the slope of the differentiated output signal in a predetermined direction (implemented). In the example, it can be detected as the intersection with the zero level in the downward slope to the right).

Therefore, since it is possible to provide a data demodulation circuit with less influence of crosstalk, the recording density in the radial direction (TP
I) also has the advantage that it becomes possible to demodulate data with fewer errors and that it becomes easier to provide a large-capacity, small-sized magnetic disk device.

[Brief explanation of drawings]

FIG. 1 is an explanatory diagram of the principle of the present invention, FIG. 2 is a block diagram of an embodiment of the present invention, and FIG. 3 is an explanatory diagram of the operation of an embodiment of the present invention.
FIG. 4 is a block diagram of the conventional example, and FIG. 5 is an explanatory diagram of the operation of the conventional example. 1 is a front circuit, 2 is an absolute value differentiating circuit, 3 is a zero cross detection circuit, 4 is a level slice circuit, and 5 is a gate circuit.

Claims (1)

[Claims] In a data demodulation circuit that outputs a pulse corresponding to a peak point of an input analog signal, a pre-circuit (1
), an absolute value differentiating circuit (2) that differentiates the absolute value of the output signal of the pre-circuit (1), and a zero-crossing detection circuit (3) that detects the zero-crossing point of the output signal of the absolute value differentiating circuit (2). ), a level slicing circuit (4) that slices the side preceding the zero-crossing point of the output signal of the absolute value differentiating circuit (2) at a constant level; A data demodulation circuit comprising: a gate circuit (5) that outputs a pulse signal as demodulated data based on a detection signal of the first zero-crossing point from the zero-crossing detection circuit (3).