JPH0361999A - Digital data synthesizer - Google Patents

Abstract

PURPOSE: To provide an address decoder for automatically selecting any search table so as to provide peak efficiency at a specified output frequency by providing an accumulator, which has a register step constituted as a pipeline, for accumulating input data and outputting addresses and a digital/analog(D/A) converter or the like. CONSTITUTION: Phase accumulators 16, 18 and 20 are provided for internally clocking adjustable step increments and the outputs of these phase accumulators 16, 18 and 20 are connected so as to address a memory 72 in which waveform functions are digitally stored. The register steps of the phase accumulators 16, 18 and 20 are composed of pipelines for accelerating the speed. Besides, a synthesizer is provided with plural D/A converters 82, 84 and 86 and all the converters are arranged on a single chip so that delay time to appear inside can be equal. Thus, the address decoder can be provided for automatically selecting any search table so as to generate peak efficiency for the specified output frequency.

Description

[Detailed Description of the Invention] (Industrial Application Field) This invention receives digital information representing a desired frequency,
The present invention relates to a digital data synthesizer (Df) that generates a periodic signal having a preset waveform of a specific frequency at its output.

BACKGROUND OF THE INVENTION Desired waveforms are pre-stored digitally at consecutive addresses in memory. To generate the output signal, the clock provides sampling times, each of which the "phase accumulator" addresses more times. A digital sample value of a desired output waveform is read from each address.

The address where the stored waveform sample value is read out.
The number of steps can be varied to generate the desired frequency.

For example, many values of the sine function table can be stored at successive addresses in memory, corresponding to successive phase angles.

The storage device it is accessed by a "staircase" addressing function at a summing rate determined by the clock. The sine wave values are read from memory in digital form in five steps along a sine function table. The read continuous sample values are transferred to a digital/analog converter (
(DAC) to an analog voltage, and the resulting waveform is smoothed by a filter to produce a relatively perfect sine wave.

To obtain an output at twice the previous frequency, the sample values are read out at the same sampling rate as before, but in steps of 10 along the stored waveform. A conventional DDS of this type is disclosed in Goldpelk US Pat. No. 4,752,902, issued June 21, 1988, which is incorporated herein by reference.

A similar synthesizer is disclosed in Jackson US Pat. No. 4,735.269, issued May 22, 1973, which is also incorporated herein by reference.

This subject is based on the paper “Digital Frequency Synthesizer #” (IEEE Bulletin on Acoustics and Electroacoustics, Vol. AU-19,
No. 1, page 4856, March 1971, edited by Tierney).

(Problems to be Solved by the Invention) The present invention solves the following problems of digital data synthesizers.

The first object of the invention is to provide a synthesizer having a register stage made up of vibrating lines and capable of obtaining a relatively high maximum output frequency which increases speed.

The second object is to provide a synthesizer that has a plurality of DACs, all of which are manufactured on the same chip, which equalizes the internal delay time and improves the resolution of the analog output signal. , Thirdly, a random access memory (R
The purpose is to make it possible to easily change the waveform using AM).

Fourth, having multiple look-up tables for the same waveform stored between addresses at different phase intervals, and automatically selecting to utilize said look-up table that yields the highest efficiency for a particular output frequency determined by the input. To provide a DDS with a selective address decoder.

Fifth, it is to provide a DDS that has, in addition to a normal main lookup table and associated main DAC, an auxiliary lookup table containing predetermined correction data and an auxiliary AC. The outputs of the main and correction channels are combined to generate a reduced distortion analog signal. A plurality of automatically addressable modification channels can be provided.

Another object is to provide both a plurality of main lookup tables and a plurality of modification channels, each of which is automatically addressable.

(Means and effects for solving the problems) The present invention has each structure described in the claims in order to solve the above problems.

A summary of these configurations along with their functions is as follows.

The digital data synthesizer of the present invention is a v! The four adjustable step increments have an internally clocked phase accumulator. The output of this phase accumulator is connected to address a memory in which the waveform function is stored digitally. Samples read from memory at successive addresses are converted to analog form and filtered to produce a final output signal at the desired frequency.

The register stages of the phase accumulator are pipelined to increase their speed. The synthesizer has multiple digital-to-analog converters, all placed on a single chip to equalize the internally occurring delay times to increase resolution and limit noise.几A
A variety of output waveforms can be transferred and generated by the M-lookup table.

One embodiment includes multiple lookup tables for the same waveform stored with different phase intervals between addresses and a decoder that automatically selects the lookup table for the highest efficiency at a particular output frequency. / address designator.

A modified search table containing predetermined modified data is also provided.

The outputs of the main table and correction table are combined to generate a reduced distortion analog signal. A plurality of such automatically addressable modification channels are provided.

(Embodiment) Referring to FIG. 1 which is an embodiment of the invention, terminal details 2.4
．． Binary code 1 where 6 specifies the desired output frequency of the DDS.
Receives input data in decimal code (BCD). The lowest (
The decimal) digit (LSD) is entered at terminal #2 and the most significant digit (MSD) is entered at terminal 6. The data is stored in each input latch 8.10.12 and represents the number of steps taken on each clock period when the memory is successively addressed.

Clock 14 generally controls the timing of events within the DDS.

BCD adder for each decimal digit, i.e. adder 16.18
．． 20 each are provided. The adder is arranged as a feedback adder to function as an accumulator. The entries to be accumulated are the data from the output of latch 8.10.12. Data is input at terminals 22.24.26 of the BCI) 71111 calculator. Each adder has a second input data terminal 28.30.
52 and output terminals 34, 36, and 58.

Feedback lines 40.42.44 are connected to terminals 34.36.
38 to the second data input terminal 28.38.
Transmit at 30.52. The data contents of adder 34.36.5B continue to be used as addressing, each such address representing a phase angle of a stored waveform, as will be explained in more detail below.

Spillover data, or carry-out data, from LSD adder stage 16 is transmitted to carry latch 46, which is controlled by clock 14. Carry latch 4
The output data from 6 is input on line 48 for a carry to adder 18, where it is added to the other input data of adder 18. Similarly, carry latch 50 receives the carry out data from adder 18 and transmits it via line 52 to the input of MSD adder 20.

From the output terminals 34, 36, 38 of the adders 16, 18, 20, the data is transferred to the respective latches 54, as shown in FIG.
．． 56.58 input. Latch 54 provides its output data to pipeline latch 60, whose output is in turn connected to another pipeline latch 62;
Its output terminal is indicated by 66. Data from the output terminal of latch 56 is provided to the input of latch 64, whose output is indicated by Vi68. The output data from latch 58 applied to terminal 70 does not pass through any other latches.

In this way, the data from LSD adder 16 is transferred to latch 5.
The output terminal 66 of the pipeline consisting of 4.60.62 is reached after three clock periods. Since the carry output data from adder 16 has a delay of one clock period in latch 46 and adder 18, latch 56
and 64 have a delay of two clock cycles. Therefore, this output data reaches the output 68 of the pipeline after three clock periods. Also, regarding the MSD, the carry output data from the adder 16 is stored in the latch 46.
and adder 1 day D with a delay of 1 clock period, and
The latch 50 and the adder 20 also have a delay of one clock period, and the latch 58 has a delay of one clock period. Thus, the length of the MSD is 3 clock cycles M-M, similar to the other two pipelines.

Therefore, the data buttoned to the output of latches 62, 64, 58 is time synchronized data. Due to the action of the parallel pipeline of latches, terminals 66, 68, 70 in each clock period
A new complete set of address data is simultaneously output. A phase accumulator, consisting of an input latch, an adder, and a pipeline, receives input data in BCD format, and its various stages contain BCD addresses.

(The final stage allows for binary rollout at the highest frequency.) represents the CD address.l(AM is accessed by these addresses and the data content located at each AM address is output to terminals 74, 76, 78.LS
D is in terminal group 74 and MSD is in terminal group 78. The data present at terminals 74, 76, 78 represents one value of a collectively stored waveform, for example a sine wave, in terms of the phase angle represented by the corresponding address in the RAM.

A conventional loading (transfer) circuit for inputting the selected waveform into the AM is shown as block 80. During operation, the waveform required at the output is loaded into the RAM 72 during operation by the data transfer circuit 80. is preset to .

FIG. 2 is a drawing that continues from the right side of FIG. 1. Second
Terminals 74, 76, 78 are shown in the figure. New data appears there each clock cycle. The series of digital samples therein has one complete cycle of the waveform (at the selected output frequency) stored during a period of time equal to one complete period. Digital data at terminal 74 is provided to 1) AC820 input; The most significant data at terminal 74 is supplied to DAC 84, and the most significant data at terminal 78 is supplied to DAC 86. All three independently operable DACs 82, 84, 86 are constructed on the same space of semiconductor substrate. They are a collection of circuits manufactured at the same time, from the same materials, and by the same process, and are therefore closely matched. The time delays in which the three DACs perform their conversion functions are thus much more similar and approximately equal to each other than the time delays of DACs constructed on separate chips. By using such a triple DAC, the resolution of the DDS is improved. The improved resolution, on the other hand, reduces the output noise and spurs (5purs)
Transient distortion, known as oscillation, is reduced, allowing the device to operate at higher speeds.

For synthesizers whose DAC is on a single chip, D
Although the AC resolution is not as high, it provides the same fidelity as a synthesizer with narrower sampling intervals. This type of triplex DAC is manufactured by Practical Corporation, 9950 Sun Diego Barneschanitan, California. Suitable types for this application are the models Btl (J9 and Bt453).

Digital to analog data conversion at the DAC is initiated by a pulse transmitted from clock 14 to clock bus terminal 90. Output analog data is provided at terminals 92, 92, and 96 of DkC82, 84, and 86, respectively.
appears in

The MSD signal on terminal 96 is connected directly to summing resistor 104 . The intermediate signal at terminal 94 is attenuated by resistor 100, which is also connected to resistor j04. The LSD signal at terminal 92 is attenuated by a resistor 98 connected from terminal 92 to terminal 94. By appropriately choosing the values of the resistors, the outputs of the three DACs are properly weighted according to their effectiveness at resistor 104.

Resistor 104 is connected to an input terminal 106 of an electrical filter 108, preferably a bandpass filter.

Filter 108 can pass the desired output signal waveform with slight attenuation and severely attenuate unwanted high and low frequencies present in the digital-to-analog approximation. Final output terminal 110 has a relatively perfectly shaped search output signal.

The output frequency can be changed by changing the number of phase steps (ie address steps) at input terminal 2.4.6.

The time sequence of operation of the device is as follows: The desired waveform is transferred from transfer circuit 80 to RAM 72. The frequency of the output is selected by selecting the number of phase steps to input at the input terminal 2.4.6. clock 14
When activated, the data for the number of steps Vi is input from the input latch 8.10.12 to the BCD adder 16.18.2.
0, where it is accumulated (integrated) into a stepped digital function representing the address.

The address from the output of adder 16.1,20 passes through pipeline latch stages 54-64 and stores RAM 72 in B.
Used for addressing in CD format. This address steps forward in time along the waveform stored in the AM, reading a sample of the waveform's amplitude at each address.

The resulting digital amplitude data is output from RAM 72 to the inputs of matched triple DACs 82, 84, 86. , DAC converts digital data into an analog signal that approximates the desired smooth output waveform by a step function. I) The AC outputs are appropriately weighted, attenuated and combined and passed through an output filter 108 to produce the desired smoothed waveform at the selected frequency.

In the embodiment of the invention shown in FIG. 3, a plurality of sine look-up tables are stored in memory, each look-up table being suitable for a particular frequency or band of frequencies. For example, several banks of sine lookup tables have been used to improve the quality of the output sine wave of a DDS. Each bank is best for a particular frequency range. The decoder/selector automatically selects the best bank based on the requested frequency.

Data specifying the frequency to be synthesized is sent to terminal 22 in Figure 1.
．． It is on 24.26. These terminals are also shown in FIG. 5, where they are connected to the inputs of block 114. Block 114 is a decoder/addresser. This examines the specified frequency to determine which sine wave data is best to synthesize it with. Decoder/addresser 114 then enables that memory bank.

The decoder/addresser 114 of the embodiment of FIG. 5 has several outputs 116a, 116b, 116c--.
-...116n. Each of which has a respective memory bank 118a, 118b, 118cm.
-...-118n is connected to the chip selection input (CS). The memory banks are all driven at the data input terminals by BCD addresses output by the pipeline latches 58, 62, and 64 of the phase system X unit.

Memory bank 118a other output data terminal j20a,
120b, 120cm----12On is terminal 74'
.

76' and 78', that is, a set of BCD code terminals are connected to each other. Only the currently selected memory bank will generate an output signal. Other banks are temporarily in a state where activation is stopped. Therefore, the memory bank most suitable for the selected frequency is operative to provide the data for constructing the waveform for that frequency.

The waveform data at terminals 74', 76', 78' are connected (as in the previous embodiment) to DACs 82, 84° 86 of FIG. (similar to the embodiment) converting the data into an analog signal. Since the sine wave coat used is made for accurate reproduction of a specific range or band of frequencies to be synthesized, the resulting final output signal at terminal 110 is significantly different from that of the previous embodiment. In good condition.

Another aspect of the invention is shown in FIGS. 4 and 5. Fourth
The figure shows an undistorted, single-frequency sine wave 122, with an approximation to the same graph as sometimes produced by the embodiments of FIGS. 1 and 2 (which have only a fundamental frequency search table).
That is, it also shows a distorted sine wave.

Distorted sine wave 124 has two fundamental components. That is, (a) a true single-frequency sinusoidal component; and (b)
) superimposed on this is an error signal component that often takes on the appearance of a higher frequency sinusoid. The error signal components are: (a) the phase spacing between adjacent addresses in memory of the stored lookup table, which is related to the number of memory addresses within one complete cycle of the waveform being synthesized; This is the result of the relationship between the phase interval or the number of memory addresses spaced by the number of steps input into the input registers 8, 10, 12.

FIG. 5 shows a modified 1 DAC having a sine function lookup table and a modified lookup table, a first DAC cooperating with an AM, and a second 2
f) shows the use of main RAM with AC;

In FIG. 5, the data from the phase accumulator vibe line is at terminals 66", 68", 70". These are l(, AM
Sine search table bank 126 and RAM modified search memory
It is connected to the input terminal of bank 128. These memory banks are addressed by this data and deliver the data that is the contents of the address. The output data from the sine search bank 126 is transmitted to the basic sine DAC, and the output data from the modified search table 128 is transmitted to the modified f)
Head to AC.

In the case of output from DAC152, the signal is sent to DAC15.
A resistor 134 is inserted in series to attenuate the zero signal. After this attenuation, the outputs of DACs 130, 132 are additively combined at terminal 136. This terminal 13
The output of 6 operates an output filter 108 (FIG. 2), which in this embodiment preferably has a different transfer characteristic.

The operation of the embodiment of FIG. 5 is as follows. When the sine search table is transferred to main memory 126 during storage,
The modified lookup table is also transferred to second memory bank 128.

Modified search table RAM128 and its auxiliary 1) AC132i
j. Output filter 108 forms an active filter that interrupts the modified signal component to eliminate distortion before receiving the signal.

The values utilized in the correction table can be verified by mathematical analysis or empirically. As an example of an empirical approach, the modification channel is temporarily disabled and the main DAC1
3o (or the output of filter 108) can be recorded. The deviation between the recorded output and the desired waveform can be measured point by point (corresponding to the address at which the data was stored in memory 126), and the deviation can be corrected with the opposite sign. Table 128 can be entered. For routine operation, the modification channel is then available. The composite output of DAC130°132 is DAC13
An output of only 0 is also close to the desired waveform.

A simple modification table can be used for common use for multiple desired frequencies. Additionally, a plurality of modified lookup tables automatically selected by an addresser/decoder of the type shown in FIG. 3 can select the lookup table appropriate for the frequency group in which the desired output frequency is included. The selected lookup table can be used with a single main lookup table 130.

Alternatively, the embodiment of FIG. 3 can be utilized in conjunction with the multiple pergerons of the embodiment of FIG. 5 to optimally correlate both the primary lookup tables and the modified lookup tables with the output frequency range. . Such a combination of embodiments provides a higher degree of fidelity in the output signal than can be obtained with either embodiment.

Although the invention has been described in terms of a single preferred embodiment,
The technical idea can be used in various embodiments. The technical scope of the invention is encompassed by the claims.

(Effects of the Invention) The present invention has a decoder/addresser that can select between lookup tables for the same waveform stored at different phase intervals and a lookup table that provides the highest efficiency at a particular output frequency. The register stage of the calculator is configured with a pipeline to increase its speed, improve the resolution of multiple digital-to-analog converters, easily change waveforms of different shapes, and obtain a high output frequency.

[Brief explanation of drawings]

FIG. 1 is a configuration diagram of an input section according to an embodiment of the present invention, FIG. 2 is a configuration diagram of an output section of an embodiment related to FIG. 1, and FIG. 5 is a concrete diagram of a plurality of automatically addressable lookup tables. Figure 4 is a graph diagram showing an undistorted sine wave output and a distorted sine wave output to explain the embodiment of Figure 5. Figure 5 is a main search table and a modification. This is a DDS circuit having a lookup table. 2, 4.6----one terminal, 8, 10.12...
......Input latch 14--Clock, 16, 18.20...-, BCD adder (accumulator) 46.50--Carry latch 54,
56.58.60.62.64...Latch 72...--RAM, 74,76.78--
...--Output terminal 80---Transfer circuit, 82.
84.86...--DAC108--Song filter

Claims (1)

Claims: 1) an input storage device for storing input data determining the frequencies to be synthesized; a clock device for periodically transferring the input data from the input storage device to an accumulator; It has a register stage configured as a pipeline, an accumulator for accumulating received input data and outputting an address, and a digital output when accessed by an address from this accumulator. A memory that stores digitally displayed waveforms through multiple addresses to output data, and a digital-to-analog converter (DAC) that accepts said digital data output and converts it to an analog signal.
A digital data synthesizer comprising: 2) The digital signal generator according to claim 1, further comprising filter means for receiving an analog signal, cutting unnecessary components of the signal, and outputting a synthesized frequency.
Data synthesizer. 3) The digital data synthesizer of claim 1, wherein the memory comprises random access memory (RAM). 4) The digital data synthesizer of claim 3, wherein the frequency instruction, accumulator, and memory operate on binary coded decimal code (BCD) data. 5) The DAC of claim 1, wherein the DAC comprises a plurality of single-chip digital-to-analog converters, each converting a portion of the output digital data having a different significance weight than the others.・Data synthesizer. 6) a device for storing input data that determines the frequencies to be synthesized; a clock device for periodically transferring said input data from said input storage to an accumulator; and registers configured by pipelines to increase speed. an accumulator for accumulating received input data and outputting an address; and an accumulator for accumulating received input data and outputting an address; a plurality of memories in which a plurality of addresses cooperate to store digitally displayed waveforms; and a plurality of memories responsive to said input data to synthesize said frequencies so as to determine the frequency at which said input data should be synthesized. a decoder/addresser for selectively activating a plurality of predetermined memories for use in a digital data synthesizer. 7) The digital data synthesizer of claim 6, wherein the accumulator includes register stages arranged by pipelines to increase speed. 8) The digital signal generator according to claim 6, further comprising filter means for receiving an analog signal, cutting unnecessary components of the signal, and outputting a synthesized frequency.
Data synthesizer. 9) The digital data synthesizer of claim 6, wherein the memory comprises random access memory (RAM). 10) The digital data synthesizer of claim 9, wherein the input data storage, the accumulator, and the memory operate with binary coded decimal code (BCD) data. 11) The digital converter of claim 6, wherein the DAC comprises a plurality of single-chip digital-to-analog converters, each converting a portion of the output digital data having a different significance weight than the others.・Data synthesizer. 12) The digital data synthesizer of claim 6, wherein the at least two memories contain different digital representations of the same waveform. 13) The digital data synthesizer of claim 12, wherein the at least two memories include digital representations having different numbers of addresses utilized to store waveforms. 14) a device for storing input data that determines the frequencies to be synthesized; a clock device for periodically transferring said input data from said input storage to an accumulator; and registers configured by pipelines to increase speed. an accumulator for accumulating received input data and outputting an address; and an accumulator for storing waveform representations at a plurality of addresses and accessed by the addresses from the accumulator. a first memory that stores a predetermined correction table at a plurality of addresses and outputs second data when accessed by an address from the accumulator; a combining device that combines the data and the second data to generate a composite output signal;
A digital data synthesizer comprising: 15) The combining device comprises a digital device for combining the first and second data, further comprising a digital-to-analog converter (DAC) for receiving a composite output signal of said data and converting this signal into an analog composite output signal. 15. The digital data synthesizer according to claim 14. 16) The digital converter of claim 15, wherein the DAC comprises a plurality of single-chip digital-to-analog converters, each converting a portion of the output digital data having a different significance weight than the others. ·data·
synthesizer. 17) a first digital-to-analog converter (DAC1) that accepts the first data and converts it to a first analog signal;
), and a second digital-to-analog converter (DAC2) that accepts the second data and converts it into a second analog signal.
15. The digital data synthesizer of claim 14, further comprising: said combining device comprising an analog device for combining said first and second analog signals. 18) DAC1 and DAC2 are comprised of a plurality of single-chip digital-to-analog converters, each converting a portion of the output digital data having a different significance weight than the others. digital data synthesizer. 19) A digital data synthesizer according to claim 14, characterized in that the accumulator has register stages organized by pipelines to increase speed. 20) The digital data synthesizer according to claim 14, further comprising filter means for accepting an analog signal, cutting unnecessary components of the signal, and outputting a synthesized frequency. 21) A digital data synthesizer according to claim 14, characterized in that the memory comprises random access memory (RAM). 22) Input data storage, accumulator, and memory are 2
22. The digital data synthesizer of claim 21, wherein the digital data synthesizer operates with data in evolved decimal code (BCD). 23) at least one further memory storing a predetermined correction table at a plurality of addresses and outputting data when accessed by an address from an accumulator; a decoder/addresser for selectively activating a particular correction table memory predetermined for use in synthesizing the frequencies to determine the frequencies to be synthesized. 16. The digital data synthesizer according to claim 15. 24) at least one further memory for storing a representation of a waveform at a plurality of addresses and outputting data when accessed by an address from the accumulator; a decoder/addresser for selectively activating a particular predetermined waveform display memory for use in synthesizing the frequencies to determine the frequency at which the data is to be synthesized. 25. The digital computer according to claim 24, characterized in that:
Data synthesizer.