JPH0361721U - - Google Patents

Info

Publication number
JPH0361721U
JPH0361721U JP12327989U JP12327989U JPH0361721U JP H0361721 U JPH0361721 U JP H0361721U JP 12327989 U JP12327989 U JP 12327989U JP 12327989 U JP12327989 U JP 12327989U JP H0361721 U JPH0361721 U JP H0361721U
Authority
JP
Japan
Prior art keywords
circuit
frequency
attenuation
tuning circuit
scanning
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP12327989U
Other languages
Japanese (ja)
Other versions
JPH0611652Y2 (en
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1989123279U priority Critical patent/JPH0611652Y2/en
Publication of JPH0361721U publication Critical patent/JPH0361721U/ja
Application granted granted Critical
Publication of JPH0611652Y2 publication Critical patent/JPH0611652Y2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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  • Channel Selection Circuits, Automatic Tuning Circuits (AREA)
  • Input Circuits Of Receivers And Coupling Of Receivers And Audio Equipment (AREA)

Description

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本考案の一実施例である自動同調受信
機30の簡略化した構成を示すブロツク図、第2
図はアツテネータ32を簡略化した構成を示すブ
ロツク図、第3図は第1自動利得制御回路39の
要所における信号レベルを示す図、第4図は検知
電圧Vr2と減衰量Aとの関係を示す図、第5図
は本実施例での高周波信号レベルの抑圧を説明す
るための図、第6図は従来の自動同調受信機1の
簡略化した構成を示すブロツク図、第7図は従来
の課題を説明するための図である。 30……自動同調受信機、31……アンテナ、
32……アツテネータ、33……電圧制御形増幅
回路、36……高周波同調回路、39……第1自
動利得制御回路、40……処理回路、43……中
間周波同調回路、46……低周波増幅回路、49
……第2自動利得制御回路、50……レベル弁別
回路、52……操作スイツチ、A……減衰量、f
……受信周波数、LO……制御実行レベル、L2
……サーチレベル、S……減衰制御信号、Vr2
……検知電圧、W2……超過量。
FIG. 1 is a block diagram showing a simplified configuration of an automatic tuning receiver 30 which is an embodiment of the present invention, and FIG.
The figure is a block diagram showing a simplified configuration of the attenuator 32, FIG. 3 is a diagram showing signal levels at key points of the first automatic gain control circuit 39, and FIG. 4 is a diagram showing the relationship between the detection voltage Vr2 and the attenuation amount A. 5 is a diagram for explaining the suppression of high frequency signal level in this embodiment, FIG. 6 is a block diagram showing a simplified configuration of the conventional automatic tuning receiver 1, and FIG. 7 is a diagram for explaining the suppression of the high frequency signal level in this embodiment. FIG. 30... automatic tuning receiver, 31... antenna,
32... Attenuator, 33... Voltage controlled amplifier circuit, 36... High frequency tuning circuit, 39... First automatic gain control circuit, 40... Processing circuit, 43... Intermediate frequency tuning circuit, 46... Low frequency Amplification circuit, 49
... Second automatic gain control circuit, 50 ... Level discrimination circuit, 52 ... Operation switch, A ... Attenuation amount, f
...Reception frequency, LO...Control execution level, L2
...Search level, S...Attenuation control signal, Vr2
...Detection voltage, W2...Excess amount.

Claims (1)

【実用新案登録請求の範囲】 減衰制御信号に応じて、受信される高周波信号
を減衰する減衰回路と、 前記減衰回路を介する高周波信号の受信周波数
帯域にわたつて検出される信号レベルのいずれか
が予め定める制御実行レベル以上であるとき、利
得を低減する第1自動利得制御回路と、 前記第1自動利得制御回路からの高周波信号に
同調する同調回路と、 前記同調回路の出力を復調する復調回路と、 前記同調回路の出力に応答して、前記同調回路
の出力が一定値となるように、同調回路または同
調回路より前段の利得を制御する第2自動利得制
御回路と、 前記同調回路の受信周波数を走査して変化させ
る周波数走査制御回路と、 前記同調回路の出力に応答し、同調している受
信周波数の搬送波のレベルが予め定める走査判定
レベル以上であるとき、前記周波数走査制御回路
による走査を停止させる判定手段と、 前記周波数走査制御回路によつて同調回路が受
信周波数を走査している期間中、前記減衰回路へ
前記減衰制御信号を与える減衰制御回路とを含む
ことを特徴とする自動同調受信機。
[Claims for Utility Model Registration] An attenuation circuit that attenuates a received high-frequency signal according to an attenuation control signal; and a signal level detected over a reception frequency band of the high-frequency signal via the attenuation circuit. a first automatic gain control circuit that reduces the gain when the gain is equal to or higher than a predetermined control execution level; a tuning circuit that tunes to the high frequency signal from the first automatic gain control circuit; and a demodulation circuit that demodulates the output of the tuning circuit. a second automatic gain control circuit that controls the gain of the tuning circuit or a stage preceding the tuning circuit in response to the output of the tuning circuit so that the output of the tuning circuit becomes a constant value; and a receiver of the tuning circuit. a frequency scanning control circuit that scans and changes the frequency; and in response to the output of the tuning circuit, when the level of the carrier wave of the tuned reception frequency is equal to or higher than a predetermined scanning determination level, the frequency scanning control circuit performs scanning. and an attenuation control circuit that applies the attenuation control signal to the attenuation circuit during a period in which the tuning circuit is scanning the receiving frequency by the frequency scanning control circuit. Tuned receiver.
JP1989123279U 1989-10-21 1989-10-21 Automatic tuning receiver Expired - Lifetime JPH0611652Y2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1989123279U JPH0611652Y2 (en) 1989-10-21 1989-10-21 Automatic tuning receiver

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1989123279U JPH0611652Y2 (en) 1989-10-21 1989-10-21 Automatic tuning receiver

Publications (2)

Publication Number Publication Date
JPH0361721U true JPH0361721U (en) 1991-06-17
JPH0611652Y2 JPH0611652Y2 (en) 1994-03-23

Family

ID=31671266

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1989123279U Expired - Lifetime JPH0611652Y2 (en) 1989-10-21 1989-10-21 Automatic tuning receiver

Country Status (1)

Country Link
JP (1) JPH0611652Y2 (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5739139U (en) * 1980-08-15 1982-03-02

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5739139U (en) * 1980-08-15 1982-03-02

Also Published As

Publication number Publication date
JPH0611652Y2 (en) 1994-03-23

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Legal Events

Date Code Title Description
EXPY Cancellation because of completion of term