JPH0361341U - - Google Patents
Info
- Publication number
- JPH0361341U JPH0361341U JP1989121859U JP12185989U JPH0361341U JP H0361341 U JPH0361341 U JP H0361341U JP 1989121859 U JP1989121859 U JP 1989121859U JP 12185989 U JP12185989 U JP 12185989U JP H0361341 U JPH0361341 U JP H0361341U
- Authority
- JP
- Japan
- Prior art keywords
- lead
- bonding pads
- circuit
- signal input
- external signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 claims description 3
- 238000010586 diagram Methods 0.000 description 2
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05554—Shape in top view being square
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
- H01L2224/49113—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting different bonding areas on the semiconductor or solid-state body to a common bonding area outside the body, e.g. converging wires
Landscapes
- Semiconductor Integrated Circuits (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
Description
第1図は本考案の一実施例の半導体集積回路の
外部信号入出力部分の回路図、第2図は従来の半
導体集積回路の外部信号入出力部の回路図である
。
11,21……外部信号入出力端子、12,2
2……ケース内部のリード(ケース側のボンデイ
ング・ワイヤ接続部)、13,13′,23……
ボンデイングワイヤ、14,14′,24……ボ
ンデイングパツド、15,15′,25……内部
回路。
FIG. 1 is a circuit diagram of an external signal input/output section of a semiconductor integrated circuit according to an embodiment of the present invention, and FIG. 2 is a circuit diagram of an external signal input/output section of a conventional semiconductor integrated circuit. 11, 21...External signal input/output terminal, 12, 2
2... Lead inside the case (bonding wire connection part on the case side), 13, 13', 23...
Bonding wire, 14, 14', 24... Bonding pad, 15, 15', 25... Internal circuit.
Claims (1)
に対して、複数のボンデイングパツドが形成され
、前記複数のボンデイングパツドのそれぞれに回
路が接続され、前記複数のボンデイングパツドの
うち一個のパツドと前記リードとを電気的に接続
するボンデイングワイヤが形成されていることを
特徴とする半導体集積回路。 A plurality of bonding pads are formed for one lead connected to an external signal input/output terminal, a circuit is connected to each of the plurality of bonding pads, and a circuit is connected to one of the plurality of bonding pads. A semiconductor integrated circuit characterized in that a bonding wire is formed to electrically connect the lead and the lead.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1989121859U JPH0361341U (en) | 1989-10-17 | 1989-10-17 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1989121859U JPH0361341U (en) | 1989-10-17 | 1989-10-17 |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH0361341U true JPH0361341U (en) | 1991-06-17 |
Family
ID=31669880
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP1989121859U Pending JPH0361341U (en) | 1989-10-17 | 1989-10-17 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0361341U (en) |
-
1989
- 1989-10-17 JP JP1989121859U patent/JPH0361341U/ja active Pending
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