JPH0360360A - Gate driving circuit - Google Patents

Abstract

PURPOSE:To avoide the delay of a switching operation and reduce power consumption for charging and discharging current by making a resonance circuit with a capacitance between the source and gate of a main switching device and an inductance. CONSTITUTION:The one end of an inductor 3 is connected to the gate of a main switching device 1 and the other end is connected to the source of the main switching device 1 through a switching means 4. Semiconductor switching devices 61D and 62D are controlled to open and close through a delay means. The resonance circuit of a gate driving circuit is composed of an inductance and a capacitance between the gate and source of the main switching device. A vibrating current reversed in direction contained in the vibrating current applied to the resonance circuit is blocked by diodes 101 and 102.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a voltage-driven self-extinguishing semiconductor switching element (FET) used in choppers and inverters.

The present invention relates to gate drive circuits for IGBTs, etc.).

[Conventional technology]

FETs and IGBTs (hereinafter referred to as FETs) are on-
Since the off state is determined by the gate voltage and the gate current is small in a steady state, bipolar transistors are called voltage-driven devices in contrast to current-driven devices.

Therefore, in addition to the high switching speed,
The advantage of requiring low gate drive power is emphasized.

FIG. 7 is a block diagram of a conventional gate drive circuit for driving this type of voltage-driven semiconductor switching element, and FIG. 8 is a waveform diagram showing the operation of the device shown in FIG. 7.

The driving pulse generating means is a DC power source 22. , 22□ and a switching element 616□.

DC power supply 22. , 222 constitute a DC power source with a positive voltage VCC and a negative voltage -VCC with reference to the source potential of the main switching element 1 consisting of an FET. (Generally, the magnitude of the positive voltage and the negative voltage do not have to be equal, but here they will be explained as having the same voltage VCC.) Switching element 61.
6□ is controlled on/off by a timing signal,
When the timing signal is at a high level, the switching element 61 is turned on, the switching element 6□ is turned off, and a positive voltage pulse (hereinafter referred to as a positive pulse) whose amplitude is the positive voltage VCC and whose source potential is the baseline is generated. is output from the drive pulse generating means 2A, and the gate current limiting resistor 8 (
(hereinafter referred to as resistor 8), the main switching element l
is applied to the gate of When the timing signal is at a low level, the switching element 6° is turned off and the switching element 6°2 is turned on, and a negative voltage pulse (
A negative pulse (hereinafter referred to as a negative pulse) is output from the drive pulse generating means 2A and applied to the gate. Therefore, the main switching element 1 is turned on when the timing signal is high level, and turned off when the timing signal is low level.

As is well known, there is a large capacitance (between the gate and source) between the gate and source of an FET (in the case of an IGBT, this is the emitter, but hereinafter referred to as the source, including the case of an IGBT) compared to a bipolar transistor. (electrostatic capacitance or input capacitance), the size of which is determined by the size of the source region, impurity concentration, etc. This input capacitance is represented by a gate-source capacitor 5 (hereinafter referred to as capacitor 5) in FIG. Therefore, when the output of the drive pulse generating means 2A transitions from a negative voltage -VCC to a positive voltage Vcc or from a positive voltage VCC to a negative voltage -VCC, a current flows through the resistor R to charge and discharge the capacitor 5. flows, and power is consumed.

Now, if we consider the transient state when the timing signal transitions from low level to high level at time to, that is, when the outputs of the two drive pulse generators go from -VCC to +VCC, the following Ohm's law is established. .

iR+ Va: Vcc (1
) Here, i is the output current of the drive pulse generation means 2A, and v
o is the gate voltage and is equal to the charging voltage Q/C of the capacitor 5. The solution to equation (1) that satisfies the initial condition of VG = -vcc at t = to is expressed by the following equation (Figure 8 CB
)reference).

i = (2Vcc/Rye-(t-""Ro(2
) Therefore, the gate voltage VO is expressed by the following equation (see FIG. 8(C)).

VG: Vcc (1-2e-”-””RC)
(3) Also, the DC power supply 22. The power P consumed by is expressed by the following equation.

P=l　Vcc　1(1t t.

ψ − (ttJ/RC = (2Vcc/R) l e 1° = 2CVcc
(4) t, when the timing signal is inverted. Sometimes, the same amount of power is consumed by the DC power supply 22□, so
The average power W when operating at frequency f is W = 2P
f = 4CVcc f (5). However, f << 1/(CR).

[Problem to be Solved by the Invention 1] As mentioned above, since the gate-source capacitance of the FET is relatively large, in the device shown in FIG. 7, (1) the gate voltage V. rises with a relatively large time constant RC (8th
(See Figure (C)), this causes a delay in the switching operation, and (2) when changing the gate voltage, the charging and discharging current of the capacitor 5 flows through the resistor R, which consumes a large amount of power. If high-frequency operation is attempted by taking advantage of the switching performance, there is a problem in that one characteristic of low driving power is lost.

An object of the present invention is to drive a voltage-driven semiconductor switching element at an arbitrary frequency while reducing switching delay caused by charging the gate-source capacitance and power consumption due to charging/discharging current. The purpose of the present invention is to provide a gate drive circuit that can perform the following steps.

[Means to solve the problem]

A first gate drive circuit of the present invention has a drive pulse generation means for generating positive and negative voltage pulses using a source as a reference potential, and outputs the output of the drive pulse generation means to a voltage voltage via a gate current limiting resistor. A gate drive circuit for switching the main switching element by applying a voltage to the gate of the main switching element made of a drive type semiconductor element, the inductor having one terminal connected to the gate of the main switching element; a first rectifier circuit consisting of a series connection of a diode and a first switching element; a second rectification circuit consisting of a series connection of a second diode and a second switching element; The second rectifier circuit is connected between them with the direction from the source of the switching element toward the other terminal of the inductor as the forward direction, and the second rectifier circuit has the direction from the other terminal of the inductor toward the source as the forward direction. The first switching element is connected between them, and is closed for a period from the trailing edge of the negative level of the voltage pulse to a predetermined time before the trailing edge of the next positive level, and the second switching element is connected between: a period from the trailing edge of the positive level of the voltage pulse to a predetermined time before the trailing edge of the next negative level;
A switching means is provided to close the circuit.

A second gate drive circuit of the present invention further includes a capacitor having one electrode connected to the gate of the main switching element and the other electrode connected to the source in the first gate drive circuit, Between the capacitor and the source/gate of the main switching element (as described above,
When an IGBT is used, the capacitance between the emitter and gate (hereinafter referred to as source and gate, including the case of IGBT) and the inductor are connected in parallel when viewed from the drive pulse generation means side. A resonant circuit is constructed.

[Effect]

The first gate drive circuit of the present invention utilizes electric oscillations caused by a resonant circuit to invert the gate voltage VG.

That is, an inductor with an inductance L is connected between the gate and the source, and a resonant circuit is formed by this inductor and the capacitance C between the gate and the source of the main switching element. However, electrical oscillations are utilized only for a period of % cycles of the resonant frequency from the position of the trailing edge of the positive and negative levels of the voltage pulse, as shown below.

Now, at time t<to, the voltage pulse is at a negative level (corresponding to the on state of the semiconductor switching element 6□D in FIG. 3. FIG. 3 will be explained in detail in the embodiment), and the gate voltage VG Assume that =-VCC. Next, after the voltage pulse transitions to the reference level (baseline) at time ○, the oscillating current i flows through the resonant circuit. and gate voltage Va are expressed by the following equation.

io = Ipo sinω(t-to)
(6) VG = -Vcc cosω(t-to)
(7) However, H ω= (LC), Ipo = (C/L)' V
cc (8)H Therefore, when the period =π (LC) ends (at time 0+), va=+Vcc and the gate voltage is inverted. Therefore, if you use the electrical oscillations over the period, the gate voltage V. can be reversed.

In order to utilize this electric vibration, the switching means of the present invention operates as follows.

Now, when the voltage pulse transitions from the negative level -VCC to the reference level at time 0, the first switching element is turned on in a closed circuit during the period from the transition edge (trailing edge of the negative level) to a predetermined time. ) A resonant circuit is completed in the forward direction of the first diode. As a result, an oscillating current flows from the source to the gate of the main switching element, and the gate voltage V increases at time to+τ when the period τ has elapsed as described above. becomes +VCC. However, as is clear from equation (6), since the direction of the oscillating current 10 is reversed after time 00, the oscillating current 10 is blocked by the first diode. As a result, time t. After +, the oscillating current i0 does not flow even if the first switching element is turned on, and the same holds true when the voltage pulse transitions from the positive level to the baseline (at the trailing edge of the positive level). The switching means therefore conduct the oscillating current only during the period from the transition time of the voltage pulse.

However, complete reversal of the gate voltage due to such electrical oscillations can be achieved if the resonant circuit is ideal, but it is usually due to winding resistance of the inductor, magnetic flux leakage, and resistance included in the resonant circuit. Because of this power loss, which cannot be fully realized due to power losses (internal losses) due to (for example, on-resistance of semiconductor elements included in the switching means), the maximum oscillating current will be smaller than Ipo; The final value of gate voltage V (H (value when period τ has elapsed) Va also does not reach +VCC and becomes an intermediate value. In order to supplement this power loss, the drive pulse generation means uses a gate current control resistor ( An additional charging current iA for charging the gate-source capacitance is output via the resistor value R), and power PA is consumed.According to the present invention, only for this additional charging, the driving pulse generating means is used. electricity supply will be required.

When the drive pulse generating means outputs a positive level, the additional charging current iA and the additional charging power PA are expressed as follows.

, -+t-t+1/RC IA = IAOe (
9) However, Lo = (Vcc - Va) /R (1
0), tl is the time of the leading edge of the positive level.

= CVcc (Vcc-Vo)
(Ill FIG. 9 is a graph showing the value of the additional charging power PA for various values of the final value V of the gate voltage V which is inverted by electric oscillation from the initial value -Vcc.

Gate voltage V. is completely reversed by electric vibration and becomes +V
If it becomes cc (if there is no power loss in the resonant circuit), select ■. = 10vcc and PA=O. Furthermore, when there is no electrical vibration, the gate voltage va remains at the initial value -VCC even after the period elapses. =-vc
c, and PA=2CV2. This coincides with equation (4) for the device shown in FIG. 7 (conventional example). In this way, the power of the driving power source is reduced in proportion to the gate voltage v0 reversed by the electric vibration.

Further, by increasing the resonant frequency of the resonant circuit and setting the period to be small, the rise of the gate voltage Va can be made faster, so that the delay in operation of the main switching element can be shortened.

In the second gate drive circuit of the present invention, a capacitor is connected in parallel to the gate-source capacitance. Assuming that C1 is the capacitance between the gate and source, C is the capacitance of the capacitor connected in parallel to the capacitance, and L is the inductance of the inductor, the resonance frequency f is expressed by the following equation.

f = (C+C,)L (
+21 Now, if C3 is set so large that C can be ignored with respect to C1, the resonant frequency f becomes almost equal to LCI and becomes independent of the gate-source capacitance C.

Therefore, it is possible to prevent errors in the period from occurring due to variations in voltage-driven semiconductor products constituting the main switching element.

Furthermore, if L is made smaller according to the degree to which CI increases with respect to C, the resonant frequency f becomes approximately the same as that of the first gate drive circuit of the present invention, so the second gate drive circuit of the present invention operates similarly to the first gate drive circuit.

[Example 1 Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 and FIG. 2 are a basic configuration diagram and a circuit diagram, respectively, of a first embodiment of a gate drive circuit of the present invention.

FIG. 3 is a waveform diagram showing the operation of each part of the device of FIG. 2.

As shown in FIG. 1, the basic configuration of the gate drive circuit of this embodiment is that an inductor 3 is added to the gate drive circuit of FIG. 7, with one end of the inductor 3 connected to the gate of the main switching element 1. The other end is connected to the source of the main switching element 1 via the switching means 4. Further, the semiconductor switching element 6 of the drive pulse generating means 2. D.
ago is the same as the switching elements 61 and 62 in FIG.
(not shown) by a timing signal.

The inductance of the inductor 3 is L, the inductor 3 and the input capacitance of the main switching element 1 (represented by the capacitor 5) form a parallel resonant circuit, and the resonant frequency f is equal to [2π(LC)']" .

The switching means 4, as shown in FIG.
Differential circuit 21 consisting of diode IO+, 10a, semiconductor switching element +1+, lla, capacitor 12 and resistor 13. It is composed of a base resistor 14 and an inverter 15. Semiconductor switching element 11+.

Reference numerals 112 denote PNP and NPN transistors, respectively, and their emitters are connected to the source (grounded) of the main switching element 1. The timing signal inverted by the inverter 15 is differentiated by the differentiating circuit 21,
It is applied to the bases of the semiconductor switching elements 11+ and llz. The capacitance C1□ of the capacitor 12 and the resistance value of the resistor 13 are the differentiating circuit 2! The pulse width of the differential pulse generated by is determined to be larger than the period T and smaller than the time T between the trailing edge of the negative pulse output by the drive pulse generating means 2 and the trailing edge of the next positive pulse. It will be done. diode 10
The anode of 1 is a semiconductor switching element 11. The cathode of the diode lO3 is connected to the collector of the semiconductor switching element 1h to form a first rectifier circuit. Further, the cathode of the diode IL and the anode of the diode l(h) are connected to the inductor 3. Therefore, the switching means 4 of FIG. A current is conducted from the ground side to the gate side of the main switching element 1 through the first rectifier circuit, and when the timing signal falls,
During the same period, current can be conducted from the gate side to the ground side via the second rectifier circuit. However, since the period during which the direction of the oscillating current is directed in the forward direction of each rectifier circuit is only during the period of 1 ri, the switching means 4
C) Conduct an oscillating current 10 only for a period equal to ', and gate voltage ■. Reverse the polarity of

The drive pulse generating means 2 is a semiconductor switching element 610
．． 62D, delay means 7, buffer 19 and voltage +v
It is composed of a DC power supply that supplies cc, -VCC.

Semiconductor switching elements 610.6□0 are each NP
N, PNP transistor, the collector is connected to DC power supply +VCC and -VCC respectively, and the emitter is
It is connected to the output terminal of the drive pulse generating means 2. The delay means 7 is an integrating circuit composed of a resistor 18 and a capacitor 17, and its integrated output is connected to the base of the semiconductor switching element 610.6zD. The resistance value R16 of the resistor 18 and the capacitance CI7 of the capacitor 17 have a time constant C+tLa of τ. is set to be approximately equal to . In this delay means 7, the capacitor 17 is charged through the resistor 18, but the capacitor 17 is discharged through the semiconductor switching element 6. Since the base current of either D or fi□ is carried out via the base and emitter, the time (discharge time) for the voltage of the capacitor 17 to go from VCC to O is short, and the voltage of the capacitor is It takes longer time to reach ±VCC (C+7
R+a), L/ Therefore, as shown in FIG. 3, the position t+ of the front line of the positive pulse and negative pulse outputted by the drive pulse generating means 2 is the rising and falling position jo of the timing signal. , t+. After 0 hours,
The trailing edge positions t+o and to are synchronized with the falling and rising edges of the timing signal.

Next, the operation of this embodiment will be explained.

First, when the timing signal is at a negative level, the output of the differentiating circuit 21 of the switching means 4 (the voltage across the resistor 13)
becomes O, and the semiconductor switching element 11,, +tz
is turned off. On the other hand, the semiconductor switching element 6 of the drive pulse generating means 2. D is off and 6□D is on, so
The level of the output signal 20 of the drive pulse generating means 2 is 1■c
c, and the gate voltage v0 becomes Vcc.

Next, when the timing signal rises at time to, a period after that rise occurs. Until , the semiconductor switching elements 6+D and 6J are both turned off, so the output of the drive pulse generation means 2 becomes high impedance, and the conduction of current from the drive pulse generation means 2 to the gate of the main switching element 1 is cut off. be done. On the other hand, the differentiating circuit 21 of the switching means 4 outputs a negative pulse with a single pulse width, so the semiconductor switching element ttz is turned off, and the semiconductor switching element II+ is turned on for a period τ, and the main signal is input from the ground side. To the gate side of the switching element l, the formula (6
) flows. This current 10 flows for a period of % cycle = π (Lcp =) and reverses the gate voltage VO.During this period, the conduction between the drive pulse generating means 2 and the resonant circuit is cut off, so the electric current generated in the resonant circuit is The vibration is not affected by the drive pulse generating means 2, and as a result, when there is no power loss in the resonant circuit, as shown by the dotted line of the oscillating current i0 curve in FIG. 3, Equation (6) The 1/2 cycle oscillating current i given by
o flows, thereby increasing the gate voltage V, as represented by the dotted line of the gate voltage VO curve. is reversed (Equation (7)
However, if there is power loss, the gate voltage Va will only rise up to VO at time t0+. Therefore, after time 1+ (0 at 70+), the drive pulse generating means 2 will increase to +Vcc. is output, and an additional charging current iA is supplied to the gate of the main switching element l via the resistor 8 (see equation (9)). In this way, the gate voltage VG becomes +VCC. At the falling edge t+o of the timing signal, the gate voltage ■ changes in a similar manner. is +VCC to -Vc
Flip to c. Also, the final value V of the gate voltage. is set to a value sufficient to turn on the main switching element 1.

As mentioned above, if L is determined so that π(LC)" is sufficiently small, the main switching element l operates without delay from the timing signal, and the power consumed by the drive pulse generating means 2 is additionally reduced. The charging power PA alone is very small (see equation (+1)). Figure 3 shows the case where t = .τ. In this case, the electrical oscillation and the additional charging operation overlap, so the power saving effect is reduced.3 Normally, the gate current limiting resistance R is large and the time constant RC is large compared to the above, so the basic principle of the present invention is Operation is not impaired thereby.

FIG. 4 is a circuit diagram of a second embodiment of the gate drive circuit of the present invention.

In the first embodiment, the inductor 3 is connected in parallel with the capacitor 5 when viewed from the output side of the drive pulse generating means 2, but they can also be connected in series. This example is such a case.

One terminal of the inductor 3A is connected to the gate of the main switching element l, and the other terminal is connected to the switching means 4 and the resistor 8. Other connections are exactly the same as the circuit shown in FIG.

At a given period of time from the transition edge of the timing signal.

Since there is no conduction between the drive pulse generating means 2 and the resonant circuit until the time period elapses, the resonant circuits shown in FIGS. 2 and 4 operate in exactly the same way. But with a delay period. After , power dissipation by inductor 3A occurs because inductor 3A is in the bus of additional charging current. However, since the resistance value of the inductor 3A is usually small, it can be ignored.

Therefore, the gate drive circuits of FIGS. 2 and 4 operate in the same way.

FIGS. 5 and 6 are a basic configuration diagram and a circuit diagram, respectively, of a third embodiment of the gate drive circuit of the present invention.

The gate drive circuit of this embodiment has a capacitor 25 connected in parallel to the capacitor 5 of the first embodiment.

In the first embodiment, the period is equal to π(LC)', but since the input capacitance C varies depending on the product of the main switching element 1, the problem is that the period differs for each element of the main switching element 1. There is.

In this embodiment, the capacitance C3 of the capacitor 25 is made sufficiently large compared to the input capacitance C.し tail, te = π old c + c +)) = π (t, c,
)' and does not depend on the input capacitance C. Also, ff1
By reducing the inductance L in accordance with the degree to which c+ is increased, the resonant frequency f is made to be approximately the same as in the first embodiment. Other aspects are exactly the same as in the first embodiment.

[Effects of the Invention] As explained above, the present invention provides a circuit in which a resonant circuit including a gate-source capacitance is configured in the gate circuit of a voltage-driven semiconductor switching element so that its resonant frequency is sufficiently high. By selecting a constant and, when inverting the gate voltage, generating a local cycle electric oscillation in the resonant circuit to substantially invert the gate voltage, and then applying the output of the drive pulse generating means to the gate, the following effects can be obtained.

(1) Operation delay of the main switching element can be reduced.

(2) The power for driving the main switching element can be reduced.

(3) The miniaturization of the multi-output isolated power supply required when applied to bridge circuits is expected to contribute to lower costs and improved reliability.

(4) There is no need to change the gate drive circuit depending on the current capacity of the main switching element, which is advantageous in terms of series arrangement.

[Brief explanation of drawings]

1 and 2 are respectively a basic configuration diagram and a circuit diagram of a first embodiment of the gate drive circuit of the present invention, FIG. 3 is a waveform diagram showing the operation of each part of the device in FIG. 2, and FIG. 4 5 is a circuit diagram of a second embodiment of the gate drive circuit of the present invention, FIGS. 5 and 6 are a basic configuration diagram and a circuit diagram of a third embodiment of the gate drive circuit of the present invention, and FIG. 7 is a circuit diagram of a third embodiment of the gate drive circuit of the present invention. A configuration diagram of a conventional example of a gate drive circuit that drives a voltage-driven semiconductor switching element, FIG. 8 is a waveform diagram showing the operation of the device in FIG. 7, and FIG. 9 is a waveform diagram showing the operation of the device shown in FIG. 7. It is a graph showing the value of additional charging power PA for various values of gate voltage vo. 1... Main switching element, 2...
.......Drive pulse generating means, 3.3A...
...Inductor, 4...Switching means, 5...
......Capacitor (gate-source capacitance), 7...Delay means, 8...Resistor (gate current limiting resistance) 9
・・・・・・・・・Timing signal, L, low'
...Diode, 2, 17.25...Capacitor, 3, 14.18...Resistor, 5...Inverter, 9... ...Buffer, 20.......Drive pulse generation means output, 2
1・・・・・・・・・Differential circuit, 22+, 22□・・・DC power supply.

Claims (1)

[Claims] 1. The source or emitter is set to a reference potential, and has drive pulse generation means for generating positive and negative voltage pulses, and the output of the drive pulse generation means is voltage driven through a gate current limiting resistor. A gate drive circuit that applies an electric current to the gate of a main switching element made of a shaped semiconductor element to cause the main switching element to perform a switching operation, comprising: an inductor having one terminal connected to the gate of the main switching element; a first diode; The first rectifier circuit includes a first rectifier circuit configured by connecting a first switching element in series, and a second rectifier circuit configured by a series connection of a second diode and a second switching element, and the first rectifier circuit includes a main switching element. The second rectifier circuit is connected between them with the direction from the source or emitter of the inductor toward the other terminal of the inductor as the forward direction, and the second rectifier circuit is connected between them with the direction from the other terminal of the inductor toward the source or emitter as the forward direction. The first switching element is connected between them, and is closed for a period from the trailing edge of the negative level of the voltage pulse to a predetermined time before the trailing edge of the next positive level, and the second switching element is connected to the voltage pulse. 1. A gate drive circuit comprising switching means that is closed during a period from a trailing edge of a positive level of a voltage pulse to a predetermined time before a trailing edge of the next negative level. 2. The capacitor further includes one electrode connected to the gate of the main switching element and the other electrode connected to the source, and the capacitor and the source-gate capacitance of the main switching element and the inductor are 2. The gate drive circuit according to claim 1, wherein the gate drive circuit is connected in parallel when viewed from the drive pulse generating means side to form a resonant circuit.