JPH0360211B2 - - Google Patents

Description

[Detailed description of the invention]

The present invention relates to a synchronous burst transmission phase control system, and in particular, to a synchronous burst transmission phase control system, which is capable of transmitting SDMA/TDMA via communication satellites.
This invention relates to a synchronous burst transmission phase control method for establishing and maintaining a TDMA frame between multiple earth stations that perform communication using the (space division multiple access/time division multiple access) method. Recently, the SDMA/SS-TDMA system is one of the satellite communication systems formed between multiple earth stations using large-capacity communication satellites, and there are strong expectations that it will adapt to future demands for satellite communication systems. ing. What is shown in Figure 1 is this SDMA/SS
- A conceptual diagram of the TDMA system, showing the related main parts in the communication satellite and the corresponding 4 as an example.
It shows the relative relationship between the spot area and the earth station. For convenience of explanation, only one earth station is set in each spot area on the earth corresponding to each spot beam of a communication satellite in FIG. , without any impediment to its generality. In FIG. 1, the communication satellite side is equipped with an onboard receiver 1, an onboard transmitter 2, a matrix switch circuit 3, a matrix switch control circuit 4, and spot beam antennas 5-1 to 4. On the earth side, 4 spot area A,
Earth stations 6-1 to 6-4 corresponding to B, C, and D are provided. Now, earth station 6-1 in spot area A is
It is assumed that this station is a predetermined reference station in this SDMA/SS-TDMA system. When a given TDMA frame is established and in normal operation, the earth stations 6-1 in each spot area A, B, C and D
The communication radio waves received from ~4 are received by the corresponding spot beam antennas 5-1~4, frequency converted and amplified by the onboard receiver 1, and input to the matrix switch circuit 3. . These received signals are input to the onboard transmitter 2 via the matrix switch circuit 3 whose switching is controlled by the matrix switch control circuit 4, and after being amplified to a predetermined transmission power, the corresponding signals are transmitted to the onboard transmitter 2. Via the spot beams 7-1 to 4 by the spot beam antennas 5-1 to 4, the corresponding spot areas A,
B, C and D. In this case, as an example, the connection mode, and, as shown in FIG. 3, are set for each of the up link and down link, corresponding to the TDMA frame shown in FIG. 2. In addition, a method is used in which switching control of the communication circuit is periodically controlled in a time-division manner. Note that an example of the TDMA frame shown in FIG.
A synchronization window 105 forms a time slot for time synchronization between the communication satellite side and the reference station side, and a time slot for connecting predetermined stations of participating earth stations 6-1 to 6-4. data windows 106, 107, 108 and 1
It is composed of 09. In addition, in Figure 3, the abbreviation shown as SBA is the spot
means a beam antenna, and therefore:
SBA(1), SBA(2), SBA(3) and SBA(4) correspond to spot beam antennas 5-1, 2, 3 and 4 in FIG. 1, respectively. Third
In an example of the connection mode shown in the figure, communication lines between each spot area formed in a time-division manner via communication satellites are as follows, corresponding to the connection modes and. ...A→A, B→B, C→C, D→D ...A→B, B→C, C→D, D→A ...A→C, B→D, C→A, D→ B...A→D, B→A, C→B, D→C In other words, based on each time slot in the TDMA frame of FIG. 2, spot areas A, B, Between C and D, the above-mentioned communication satellite is used as a medium.
SDMA/SS-TDMA system is formed. As mentioned above, establishing and maintaining the TDMA frame is a prerequisite for forming the SDMA/SS-TDMA system. In the case of the conventional TDMA satellite communication system, one or several of the participating earth stations serves as a reference station, and transmits a reference burst signal according to a reference time signal provided within this reference station.
A time slot standard for the TDMA system is established by transmitting a reference burst signal using a cycle corresponding to a TDMA frame as a reference, and receiving this reference burst signal at the participating station via a communication satellite.
However, in the case of SDMA/SS-TDMA method,
Switching control of the matrix switch circuit 3 according to a predetermined connection mode is performed in synchronization with the reference time signal built into the matrix switch control circuit 4. Therefore, first, the reference station sets the time reference of its own station. , must be generated in synchronization with the reference time signal of the matrix switch control circuit 4 in the communication satellite. Needless to say, the distance between the communication satellite and the reference station varies slowly over time even when a geostationary satellite is used as the communication satellite, so the synchronization described above means that the reference station The time reference of the reference station itself is constantly controlled by referring to the time reference within the communication satellite so that the signal transmitted according to the time reference of the own station is always in synchronization with the time reference within the communication satellite. It means adjusting. As a countermeasure for this, TDMA in SDMA/SS-TDMA system
As a means of establishing and maintaining a frame,
A synchronous burst transmission phase control method is being considered. FIG. 4 is a conceptual system block diagram showing only the relevant main parts in the synchronous burst transmission phase control method. In FIG. 4, the reference station on earth is equipped with a synchronization burst generation means 8, a modulation transmission system 9, a reception demodulation system 10, a phase error detection means 11, and a metric pattern phase control means 12. Equivalent gate means 14 is provided inside. Also, in the diagram, up links and down links are shown.
Equivalent delay lines 15 and 16 are shown for the propagation paths corresponding to the links, respectively. In FIG. 4, the synchronous burst generating means 8 outputs a predetermined synchronous burst signal generated based on the reference time signal in the reference station, and passes through the modulation transmission system 9 and the equivalent delay line 15.
It is input to the equivalent gate means 14. In the equivalent gate means 14, the synchronized burst signal is gated by a synchronization window generated and input based on the reference time signal in the communication satellite, and is sent back to the reference station via the equivalent delay line 16. . As shown in FIG. 5a as an example, the synchronous burst signal is a commonly used PSK signal.
(Phase Shift Keying) Corresponding to the case where a modulation method is applied to a carrier wave, an unmodulated carrier wave portion (Continuous Wave: (abbreviated as CW) and a predetermined code time series signal (abbreviated as Bit Timing Recovery: BTR) that acts for clock pulse extraction.
It is equipped with a preamble consisting of a part modulated by a preamble, a part modulated by a predetermined synchronization signal (Unique Word: UW), and a part modulated by a predetermined synchronization signal (Unique Word: abbreviated as UW). used. A metric pattern (Me-
The modulation part by tric pattern (abbreviated as METRIC) continues. When the synchronous burst transmission phase control system is in a normal operating state, the synchronous burst signal returned to the predetermined reference station via the equivalent delay transmission line 16 is as shown in FIG. 5b, as described above. shown,
This synchronization burst is input to the reception demodulation system 10 in a gated-off form with the latter half of the metric pattern bounded by the trailing edge 100 of the synchronization window generated based on the time reference within the communication satellite. In the reception demodulation system 10, the signal is
The unique word (UW), shown in solid line in FIG. A synchronous burst signal formed by the metric pattern (METRIC) is generated and sent to the phase error detection means 11. The phase error detection means 11 detects the trailing edge 100 of the synchronization window in FIG. 5b and the metric pattern (METRIC) of the synchronization burst signal shown in FIG. 5c, which corresponds to this trailing edge 100. The gated trailing edge time position 102 is detected and the metric
The time difference from the reference time position set at the center time position of the pattern (METRIC) is extracted and output as a phase error signal in the synchronous burst transmission phase control method. This phase error signal is sent to the synchronization burst generation means 8 via the metric pattern phase control means 12, and controls the phase of the synchronization burst signal generated in the synchronization burst generation means 8. The subsequent operation is as described above, and the phase error signal output from the phase error detection means 11 is made to be zero by the synchronous burst transmission phase control method formed by the closed loop shown in FIG. , the phase of the synchronization burst signal is controlled and adjusted to establish and maintain a TDMA frame synchronized to a synchronization window within the communications satellite. Note that as a phase control method in the synchronous burst generating means 8, for example, a voltage controlled oscillator may be used, or a frequency divider may be used. For the specific details of the above-mentioned synchronous burst transmission phase control method, please refer to the literature RARAPUANO,
AND N.SHIMASAKI,
“SYNCHRONIZATION OF EARTH
STATIONS TO SATELLITE−SWITCHED
SEQUENCES，”AIAA4TH
COMMUNICATIONS SATELLITE
As detailed in SYSTEMS CONFERENCE, APRIL 1972, when detecting the time position 102 of the trailing edge of gate off in the measurement metric pattern (METRIC),
Signal-to-noise ratio and synchronization window trailing edge 10 in transmission systems including link and downlink
0 (FIG. 5b), an uncertain time region occurs at the time position of the trailing edge of the detected metric pattern (METRIC). In order to remove this uncertainty, a predetermined metric pattern constituting a part of the synchronous burst signal is stored in a metric pattern storage means for a predetermined number of measurements n (an integer greater than 1), and then,
Metric pattern storage means
The pattern is read out and compared for each symbol with a predetermined reference metric pattern, and the comparison result is simply integrated for each symbol or converted into a predetermined weighting coefficient to correct the characteristics of error occurrence in the transmission path. A method is used in which the symbol length of a correctly received metric pattern is determined by performing subsequent integration and comparing and checking the integrated value for each symbol with a predetermined reference level value. This synchronous burst is typically around 1 μs long,
The metric pattern is selected to be approximately 16 symbols, and the synchronization window length is selected to be approximately 5 μs. If the synchronization burst is correctly synchronized with the synchronization window, control is performed as shown in FIG. 5 as described above. However, when an earth station transmits a synchronization burst to a satellite for the first time, it usually uses a low-power signal to find the synchronization window position, uses the low-power signal to determine the approximate position of the transmission timing, and then transmits the synchronization burst. Send. The method of determining the approximate transmission timing using this low power signal is disclosed in Japanese Patent Publication No. 56-1817, so it will not be described in detail here. By the way, in determining the transmission timing using this low power signal, in order to improve the signal-to-noise ratio, the signal is received by using a narrow band signal and limiting the band, so there is a considerable error (for example, about ±1 μs). Therefore, when transmitting a synchronization burst for the first time after determining the transmission timing using low power, it is controlled to be near the center of the synchronization window as shown in FIG. 6b, and the unique word ( After UW) is detected, Figure 6c
The synchronization burst is moved backward by a fixed number of symbols until the normal synchronization state is reached. However, FIG. 6a shows the timing of the synchronization window. Since metric pattern detection is performed based on the new word (UW) reception timing, synchronization bursts must be moved so that the unique word (UW) is always within the synchronization window. Also, before entering the normal synchronization state, the clock frequency that controls the matrix switch on the satellite and the clock frequency of the synchronizer on the ground cannot be precisely matched, so the synchronization window and synchronization burst have nothing to do with each other. Even without control, there will be some drift due to differences in clock frequencies. Therefore, to avoid the unique word falling outside the synchronization window due to drift due to this clock frequency difference, moving the synchronization burst from state b to state c in Figure 6 requires: This is done by moving backward by 1/2 the length of the metric pattern. The movement of this synchronous burst requires multiple measurements and control, and control is determined by adding the transmission timing error detection time to the round trip delay time (approximately 0.3 seconds) between the earth station and the satellite (hereinafter referred to as transmission control). Since the process is carried out in cycles (referred to as "periods"), it has the disadvantage that it takes a long time to reach the state shown in FIG. 6c. In addition, in the conventional method, when the clock frequency difference is large, even after controlling the rear end of the flat synchronization window to be located in the center of the metric, the unique word moves outside the synchronization window and a synchronization burst is detected. This has the disadvantage that there is a situation where the synchronization window becomes impossible or the rear end of the synchronization window deviates from the metric pattern. Furthermore, the clock frequency difference between the satellite's clock frequency and the ground synchronizer is determined by integrating the difference between the corrected transmission timing amount and the measured transmission timing error, and converting this into a frequency difference. The two clocks are synchronized by correcting and removing the oscillation wave number of the clock oscillator of the synchronizer. However, as mentioned above, if the synchronization window goes outside the metric pattern, and if the new word goes outside the synchronization window,
Since transmission timing errors could not be measured, the difference between the satellite's clock frequency and the clock frequency of the synchronizer on the ground had to be kept extremely small. In the following explanation, the normal synchronization state is the state in which the trailing edge of the synchronization window can be detected in the metric pattern and the above control is performed to synchronize the clock frequency of the satellite and the clock frequency of the synchronizer on the ground. It's called. The object of the present invention is to eliminate the above-mentioned drawbacks and to make it possible to quickly synchronize a synchronization burst to a synchronization window, even when there is a relatively large frequency difference between the satellite clock frequency and the ground synchronizer. Another object of the present invention is to provide a synchronous burst transmission phase control method that enables stable normal synchronous state to be reached. The present invention uses a sufficiently long metric pattern to reduce the number of transmission controls required until the metric pattern reaches the rear end of the synchronization window, as shown in FIGS. , divide the metric pattern into two areas (MET1 and MET2), and if the synchronization state of the synchronization burst and the synchronization window is unstable,
The first feature is that the time required to reach a normal synchronization state is shortened by monitoring the reception status of both patterns in the two areas of the metric pattern and controlling transmission. However, FIG. 8a shows the timing of the synchronization window. After normal synchronization, as shown in Figure 8c, the transmission timing is controlled so that the rear end of the synchronization window is located in the center of the area behind the metric pattern (MET2), and the window exits the synchronization window. The second feature is that the time required for metric pattern detection is shortened by keeping the burst length short and limiting metric pattern detection to the area behind the metric pattern (MET2). In other words, by making the total symbol length of MET1 and MET2 sufficiently long, it is possible to detect the rear end of the synchronization window in the metric pattern (MET1 or MET2) with one or several measurements. . Also, even if there is a difference between the clock frequency of the satellite and the clock frequency of the synchronizer on the ground, the unique
Words can be prevented from falling outside the sync window, and the trailing edge of the sync window can be prevented from falling outside the metric pattern. The difference in frequency between the satellite's clock and the synchronizer on the ground can be determined by integrating the difference between the corrected transmission timing amount and the measured transmission timing error and converting this into a frequency difference, as has been conventionally done.
This can be eliminated by correcting the oscillation frequency of the satellite's clock oscillator or the ground synchronizer's clock oscillator. In this way, after the transmission timing and the difference between the satellite's clock frequency and the ground synchronizer's clock frequency become sufficiently small, the amount by which the rear end of the synchronization window deviates from the reference position in one transmission control cycle is:
Usually within a few symbols. At this time, if we continue to control the transmission timing so that the synchronization window is in the center of the metric pattern, the synchronization window will be approximately 1/1/2 of the metric pattern.
2 will be outside the synchronization window, and this portion cannot be used for actual communication performed by other stations. As can be seen from Figure 8, the metric pattern requires about 3 μs, and as 1/2 of this,
This is 1.5 μs, which corresponds to approximately 100 symbols when the clock frequency used for communication is 65 MHz. In the present invention, after a normal synchronization state is reached, the rear end of the synchronization window is controlled to be located at the center of the area behind the metric pattern (MET2). Since the length of MET2 is approximately 16 symbols, the number of metric patterns that go outside the synchronization window in this state can be kept to approximately 8 symbols. In addition, the length of the correctly received part of the metric pattern is detected by processing the reception status multiple times for each symbol as described above, so if the length of the metric pattern becomes long, this processing The time also becomes longer, which means that the transmission control period becomes longer. As the transmission control period becomes longer, the transmission timing error of the synchronous burst becomes larger. In the normal synchronization state, the present invention limits the metric pattern detection processing to only MET2, thereby shortening the processing time and making it possible to shorten the synchronization burst transmission control period. Hereinafter, the present invention will be explained in detail with reference to the drawings. FIG. 9 is a block diagram showing a main part of an embodiment of the time phase error detection means applied to the present invention, and shows a case where the timing error is determined by averaging measurement values for n frames. FIG. 10 is a diagram conceptually showing the timing relationship of the operations of each part in the embodiment of FIG. 9. As shown in Figure 9,
The time phase error detection means applied to the present invention includes a shift register (P) 17, a shift register (Q) 18, a UW detection circuit 19, a timing signal generation circuit 20, an AND gate 21, and a memory. (P) 22 and memory (Q) 23, metric pattern weighting means 30 consisting of a reference metric pattern generation circuit 24 and weighting circuits 25-1 to _m2 , and an integration circuit 26- 27-1 to _m2 , symbol threshold value determining means 32 comprising threshold value determining circuits 27-1 to _m2 , and a symbol timing determining circuit 27-1. Note that this phase error detection means is
The modulation method for the carrier wave corresponds to the case where 4-phase PSK is applied. In the figure, m ₁ represents the number of symbols in the area in front of the metric pattern (MET1), and m ₂ denotes the number of symbols forming the entire metric pattern (MET1 and MET2), which is generally an integer value greater than one. In FIG. 9, from terminals 51 and 52,
Synchronous burst signals corresponding to the P and Q channels sent from the reception demodulation system are input to the shift registers (P) 17 and 17, respectively.
UW detection circuit 19 and shift register (Q) 1
8 and the UW detection circuit 19. In the shift register (P) 17 and shift register (Q) 18, the metric pattern (METRIC) in the synchronous burst signal of each channel is temporarily stored. Also,
In the UW detection circuit 19, the synchronized burst signals of both P and Q channels inputted from terminals 51 and 52 via the reference clock signal inputted from terminal 53 are converted into a unique signal as shown in FIG.
Each word (UW) is detected, a UW detection signal is output, and the timing signal generation circuit 20
sent to. The timing signal generation circuit 20 receives the UW detection signal and a predetermined reference clock signal input from the terminal 53, generates a predetermined first timing signal, and outputs it to the AND gate 21. Similarly, second, third, and fourth timing signals are sent from the timing signal generation circuit 20 to the integration circuit 26-1, respectively.
~m ₂ , threshold value determination circuits 27-1 to m ₂ and symbol timing determination circuit 28, and a predetermined address signal and write/read control signal are sent to memory (P) 22 and memory (P) 22, respectively. (Q) It was sent to 23. Here, with reference to FIG. 10, the mutual time relationship of the first to fourth timing signals will be explained. In FIG. 10, a indicates the timing at which the unique word (UW), the first metric pattern (MET1), and the second metric pattern (MET2) are supplied. 9b shows the operation, timing, or operation start timing of each circuit in FIG.
The period for writing MET1 and MET2 is the period for reading stored data from the metric pattern storage means, and the period for writing MET1 and MET2 is the metric pattern weight determining means 30.
is the operating period of the weighting coefficient accumulating means 31, is the operating period of the symbol threshold determining means 32, and is the operating period of the symbol timing determining circuit 28. FIG. 10c shows the first timing signal, which inputs MET1 and MET2 to the input signals 51 and 52 upon receiving the output of the unique word detection circuit.
The period for extracting the data from the metric pattern storage means 2 and writing it into the metric pattern storage means 2 is specified. A second timing signal d in the figure instructs the timing at which the weighting coefficient accumulating means 31 should perform processing at the time when the processing of the metric pattern weighting means is completed. When the integration process for the reception metric pattern for n frames is completed, the timing signal generation circuit outputs a third timing signal shown at 10e to instruct the symbol threshold value determining means 32 to start processing. Furthermore, at the timing when the processing ends, the timing signal generation circuit
A fourth timing signal shown in FIG. 0f is output to instruct the symbol timing determination circuit to start operation. The AND gate 21 inputs the reference clock signal input from the terminal 53 and the first timing signal sent from the timing signal generation circuit 20, and generates a reference clock signal corresponding to the first timing signal. A signal is output and sent to shift register (P) 17 and shift register (Q) 18. Shift register (P) 17
and in shift register (Q) 18,
The metric patterns (METRIC) of the P and Q channels input from the terminals 51 and 52 and temporarily stored are sequentially outputted via the reference clock signal to the memory (P) 22 and the memory, respectively. (Q) Sent to 23.
In the memory (P) 22 and memory (Q) 23, each channel of P and Q is sent to a predetermined address via the address signal and write control signal sent from the timing signal generation circuit 20, respectively. A metric pattern (METRIC) is stored a predetermined number of times. Thereafter, the metric pattern (METRIC) for a predetermined n number of times stored at predetermined addresses in the memory (P) 22 and memory (Q) 23 is stored in the address signal and The signals are sequentially read out in the form of parallel signals via the readout control signal and sent symbol by symbol to the weighting circuits 25-1 to _m2, respectively. In this case, the metric pattern (MET1 and
Since the number of symbols of MET2) (METRIC) is assumed to be _m2 , _m2 weighting circuits are required.
Similarly, m2 integration circuits 26-1 to _m2 and threshold determination circuits 27-1 _{to m2} connected to the weighting circuits 25-1 to m are required. In the weighting circuits 25-1 to _m2 , the metrics of the respective channels read out from the memory (P) 22 and the memory (Q) 23 via the readout control signal output from the timing signal generation circuit 20 are used. Parallel outputs of the pattern (METRIC) are inputted one bit at a time in the form of symbols, and a predetermined reference metric pattern (METRIC) output from the reference metric pattern generation circuit 24 is inputted to generate both metric patterns. The pattern (METRIC) is compared and verified symbol by symbol, and predetermined weighting coefficient values are set and extracted in accordance with the comparison and verification results, and sent to the corresponding integration circuits 26-1 to _m2 . This weighting factor value is
For example, the settings are as follows. Now, memory (P) 22 and memory (Q) 23
Let the symbol corresponding to the j-th bit of the metric pattern (METRIC) read from the i-th measurement time be (a _ij , b _ij ), and a _ij and
Let the symbol of b _ij after comparison with the reference metric pattern (METRIC) be ( _ij , _ij ). In this case, weighting coefficient values α ₀ , α ₁ , α ₂ and α ₃ are set as shown in the table below according to the appearance rate of 1 or 0 in _ij and _ij .

[Table] As an example, the weighting coefficient values α ₀ , α ₁ , α ₂ and α ₃ shown in the above table correspond to the symbols (a _ij , b _ij )
Correspondingly, the signals are sent to the integration circuits 26-1 to 26-m, respectively, and are added up for each symbol over the number of measurements via the control signal input from the timing signal generation circuit 20. When the number of measurements is n, weighting coefficient values for n times are added. In general, the weighting coefficient addition values output from the integration circuits 26-1 to _m2 are expressed by the following equation in the above example. _o 〓 ⁱ⁼¹ α _k {(a _i , _j , b _i , _j )} (k=0 to 3) i=1, 2,..., n j=1, 2,..., n Threshold judgment circuit In 27-1~ _m2 ,
By inputting the weighting coefficient addition values output for each symbol from the integrating circuits 26-1 to _m2 ,
Through a control signal input from the timing signal generation circuit 20, for example, a three-value identification value is outputted from each of the threshold determination circuits 27-1 to _m2 by comparison with a predetermined reference level value. Metric pattern (METRIC) in Figure 8c
The time positions 103 and 104 are the correspondence relationship between the time position on the metric pattern (METRIC) and the ternary identification value when the outputs of the threshold determination circuits 27-1 to _m2 are ternary identification values. For example, the three-value discrimination reference level is L ₁ and L ₂
Then, the following formula holds true as a general formula. _o 〓 ⁱ⁼¹ α _k {(a _i , _j , b _i , _j )}<L ₁ (k=0 to 3) (j=1, 2,..., l) L ₁ ≦ _o 〓 ⁱ⁼¹ α _k {(a _i , _j , b _i , _j )}<L ₂ (k=0~3) (j=l+1, l+2,..., l+p) L ₂ ≦ _o 〓 ⁱ⁼¹ α _k {(a _i , _j , _bi , _j )} (k=0~3) (j=l+p+1, l+p+2,..., _m2 ) That is, the time positions 103 and 104 in FIG. As shown in FIG. After the synchronization burst reaches a normal synchronization state, a normal synchronization display signal 55 is inputted from an external control circuit to the threshold judgment circuits 27-1 to _27m1 corresponding to the area in front of the metric pattern (MET1).
The outputs of the threshold judgment circuits 27-1 to _27m1 are hit so that they do not exceed _L1 regardless of the inputs of the integration circuits 26-1 to _26m1 , that is, all symbols are correctly received. . As mentioned above, for each symbol, the m ₂ three-value identification values output from the corresponding threshold judgment circuits 27-1 to m ₂ are input to the symbol timing judgment circuit 28, and these The time position gated off by the synchronization window (102 in 8b and c) in the metric pattern (METRIC) is detected by arithmetic processing that refers to the m ₂ ternary identification values, and The symbol lengths corresponding to time positions 101 and 102 are measured, a predetermined reference symbol length and time displacement amount are extracted, and the error voltage corresponding to this time displacement amount is calculated as the phase error in the synchronous burst transmission phase control method. Output as voltage. This phase error voltage is sent to the metric pattern phase control means 12 shown in FIG. 4, which controls and adjusts the phase of the synchronous burst signal generated by the synchronous burst generating means 8, so that the phase error voltage becomes zero. The synchronous burst transmission phase control method operates so that
The time position corresponding to the reference symbol length of the metric pattern (METRIC) is the time position 102 (8th
(see Figures b and c), the transmission phase of the synchronized burst signal is maintained at a predetermined phase,
As described above, the TDMA frame in the SDMA/SS-TDMA system is established and maintained. Note that the standard symbol length of the metric pattern is the entire metric pattern (MET1 and MET2) before the synchronization burst enters the normal synchronization state.
After the synchronization burst enters a normal synchronization state, the symbol length up to the center of the area behind the metric pattern (MET2) is selected. In addition, even after entering normal synchronization state, if it becomes necessary to make a major correction to the transmission timing, such as when the clock frequency of the satellite and the clock frequency of the synchronizer on the ground deviate, the operation before entering normal synchronization state will be repeated. If you do this, you can return to normal synchronization in a short time. In addition, in the above explanation, the modulation method is SDMA/SS-1, which uses 4-phase PSK modulation method.
Although the case where the present invention is applied to the TDMA system has been described, it goes without saying that the present invention can also be effectively applied to cases where a polyphase PSK modulation system of four or more phases is generally used. Furthermore, in the present invention, the metric pattern is stored in memory and then sequentially subjected to logical processing, so the process of reading out the metric pattern is
It can be processed independently of the TDM frame and TDMA symbol rate, and this part can be processed at the speed of a microprocessor. When a microprocessor is applied to the present invention, all of the aforementioned m weighting circuits, m threshold judgment circuits, symbol timing judgment circuits are realized by software using one microprocessor. You can also do that. In this case, after the synchronization burst enters the normal synchronization state, processing corresponding to the m weighting circuits and m threshold determination circuits described above is performed on the region corresponding to the area behind the metric pattern (MET2). By limiting the processing time to the following, the processing time can be significantly shortened. The present invention can also be implemented in such a manner that after the synchronization burst reaches a normal synchronization state, a short synchronization burst having a metric pattern of only the symbol length of MET2 is transmitted as shown in FIG. 8d. As explained in detail above, the present invention
The SDMA/SS-TDMA method is applied to satellite communication systems, and uses low-power signals to significantly shorten the time it takes to precisely synchronize the synchronization burst to the synchronization window after determining the approximate transmission timing. do. That is, this has the effect of significantly shortening the time required to recover synchronization of the system, and has the effect of significantly improving the reliability of the system. Further, since the present invention can be applied to a system using a microprocessor, it is possible to downsize the device, and parameters can be changed economically.

[Brief explanation of drawings]

Figure 1 is a system conceptual diagram of the SDMA/SS-TDMA system, Figure 2 is a diagram showing an example of a TDMA frame, Figure 3 is a diagram showing an example of a connection mode, and Figure 4 is a diagram of the synchronous burst transmission phase control system. Conceptual system block diagram; Figures 5a, b, and c are waveform conceptual diagrams of the metric pattern during transmission, the synchronization window, and the metric pattern during reception demodulation, respectively; Figures 6a, b, and c are respectively the synchronization window. , a conceptual diagram showing a synchronization burst sent out immediately after determining the approximate transmission timing using a low-power signal, and a synchronization burst in a normal synchronization state;
FIG. 7 is a conceptual diagram of a synchronization burst used in the present invention, and FIGS. 8a, b, and c are a synchronization window and b a low-power signal sent immediately after the rough transmission timing is determined, respectively. 3 shows a synchronization burst of the present invention in a normal synchronization state, c a synchronization burst of the present invention in a normal synchronization state, and d a synchronization burst in different embodiments of the present invention in a normal synchronization state. FIG. 9 is a block diagram showing a main part of an embodiment of the phase error detection means applied to the present invention, and FIG. 10 is a diagram showing an example of the operation timing of each part of the circuit of FIG. 9. In the figure, 1...onboard receiver, 2...onboard transmitter, 3...matrix switch circuit, 4...
Matrix switch circuit control circuit, 5-1 to 4
...Spot beam antenna, 6-1 to 4...
...Earth station, 7-1~4...Spot beam, 8
...Synchronized burst generating means, 9...Modulation transmission system,
10... Reception demodulation system, 11... Phase error detection means, 12... Metric pattern phase control means, 13... Communication satellite, 14... Equivalent gate means, 15, 16... Equivalent delay line, 17... Shift register (P), 18...Shift register (Q), 19...UW detection circuit, 20...Timing signal generation circuit, 21...AND gate, 22...
...Memory (P), 23...Memory (Q), 24...
Reference metric pattern generation circuit, 25-1~
m... Weighting circuit, 26-1~m... Integration circuit, 27-1~m... Threshold determination circuit, 28...
...Symbol timing judgment circuit, 29...Metric pattern storage means, 30...Metric pattern weighting means, 31...Weighting coefficient accumulation means, 32...Symbol threshold judgment means.

Claims (1)

[Claims] 1 A communication satellite equipped with a plurality of spot beams corresponding to up links and down links, and having a function of switching and controlling line connections between the up rings and down links via a predetermined connection mode. SMDA/SS-TDMA (Space Division
Multiple Access/Satellite Switching-Time
In a satellite communication system based on the division multiple access system, a predetermined satellite communication reference station establishes and maintains a TDMA frame for an earth station corresponding to a plurality of different spot areas. , a synchronization burst including a metric pattern in which the first half is a first metric pattern and the second half is a second metric pattern, and this synchronization burst is based on a predetermined reference time in the satellite communication. The received signal is gated off by a synchronization window for regulating TDMA frames and sent back, and the symbol length of the metric pattern received without being gated off by the synchronization window is measured, and the symbol length of the metric pattern is measured according to a predetermined standard. first means for measuring a transmission timing error by comparison with a symbol length; second means for controlling the transmission timing of a synchronization burst in response to the output of said first means; A synchronous burst transmission phase control system comprising: third means for controlling said first means so that only said second metric pattern is subject to measurement when the metric pattern is within the range.